1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AHCI SATA Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
11 Each SATA controller should have its own node.
13 It is possible, but not required, to represent each port as a sub-node.
14 It allows to enable each port independently when dealing with multiple
18 - Hans de Goede <hdegoede@redhat.com>
19 - Jens Axboe <axboe@kernel.dk>
27 - cavium,octeon-7130-ahci
30 - marvell,armada-3700-ahci
31 - marvell,armada-8k-ahci
32 - marvell,berlin2q-ahci
37 - $ref: "ahci-common.yaml#"
45 - marvell,armada-8k-ahci
46 - marvell,berlin2-ahci
47 - marvell,berlin2q-ahci
50 - cavium,octeon-7130-ahci
53 - marvell,armada-3700-ahci
80 "^sata-port@[0-9a-f]+$":
81 $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port
85 - required: [ target-supply ]
87 unevaluatedProperties: false
94 unevaluatedProperties: false
99 compatible = "snps,spear-ahci";
100 reg = <0xffe08000 0x1000>;
104 #include <dt-bindings/interrupt-controller/arm-gic.h>
105 #include <dt-bindings/clock/berlin2q.h>
106 #include <dt-bindings/ata/ahci.h>
109 compatible = "marvell,berlin2q-ahci", "generic-ahci";
110 reg = <0xf7e90000 0x1000>;
111 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&chip CLKID_SATA>;
113 #address-cells = <1>;
116 hba-cap = <HBA_SMPS>;
121 phys = <&sata_phy 0>;
122 target-supply = <®_sata0>;
124 hba-port-cap = <(HBA_PORT_FBSCP | HBA_PORT_ESP)>;
130 phys = <&sata_phy 1>;
131 target-supply = <®_sata1>;
133 hba-port-cap = <(HBA_PORT_HPCP | HBA_PORT_MPSP | HBA_PORT_FBSCP)>;