1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner Memory Bus (MBUS) controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The MBUS controller drives the MBUS that other devices in the SoC
15 will use to perform DMA. It also has a register interface that
16 allows to monitor and control the bandwidth and priorities for
19 Each device having to perform their DMA through the MBUS must have
20 the interconnects and interconnect-names properties set to the MBUS
21 controller and with "dma-mem" as the interconnect name.
24 "#interconnect-cells":
27 The content of the cell is the MBUS ID.
31 - allwinner,sun5i-a13-mbus
32 - allwinner,sun8i-a33-mbus
33 - allwinner,sun8i-a50-mbus
34 - allwinner,sun8i-a83t-mbus
35 - allwinner,sun8i-h3-mbus
36 - allwinner,sun8i-r40-mbus
37 - allwinner,sun8i-v3s-mbus
38 - allwinner,sun8i-v536-mbus
39 - allwinner,sun20i-d1-mbus
40 - allwinner,sun50i-a64-mbus
41 - allwinner,sun50i-a100-mbus
42 - allwinner,sun50i-h5-mbus
43 - allwinner,sun50i-h6-mbus
44 - allwinner,sun50i-h616-mbus
45 - allwinner,sun50i-r329-mbus
50 - description: MBUS interconnect/bandwidth limit/PMU registers
51 - description: DRAM controller/PHY registers
62 - description: MBUS interconnect module clock
63 - description: DRAM controller/PHY module clock
64 - description: Register bus clock, shared by MBUS and DRAM
76 MBUS PMU activity interrupt.
80 See section 2.3.9 of the DeviceTree Specification.
82 '#address-cells': true
87 - "#interconnect-cells"
99 - allwinner,sun5i-a13-mbus
100 - allwinner,sun8i-r40-mbus
134 additionalProperties: false
138 #include <dt-bindings/clock/sun50i-a64-ccu.h>
139 #include <dt-bindings/interrupt-controller/arm-gic.h>
141 dram-controller@1c01000 {
142 compatible = "allwinner,sun5i-a13-mbus";
143 reg = <0x01c01000 0x1000>;
144 clocks = <&ccu CLK_MBUS>;
145 #address-cells = <1>;
147 dma-ranges = <0x00000000 0x40000000 0x20000000>;
148 #interconnect-cells = <1>;
152 dram-controller@1c62000 {
153 compatible = "allwinner,sun50i-a64-mbus";
154 reg = <0x01c62000 0x1000>,
156 reg-names = "mbus", "dram";
157 clocks = <&ccu CLK_MBUS>,
160 clock-names = "mbus", "dram", "bus";
161 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
162 #address-cells = <1>;
164 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
165 #interconnect-cells = <1>;