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[releases.git] / Documentation / devicetree / bindings / arm / sp810.yaml
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/arm/sp810.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: ARM Versatile Express SP810 System Controller
8
9 maintainers:
10   - Andre Przywara <andre.przywara@arm.com>
11
12 description:
13   The Arm SP810 system controller provides clocks, timers and a watchdog.
14
15 # We need a select here so we don't match all nodes with 'arm,primecell'
16 select:
17   properties:
18     compatible:
19       contains:
20         const: arm,sp810
21   required:
22     - compatible
23
24 properties:
25   compatible:
26     items:
27       - const: arm,sp810
28       - const: arm,primecell
29
30   reg:
31     maxItems: 1
32
33   clock-names:
34     items:
35       - const: refclk
36       - const: timclk
37       - const: apb_pclk
38
39   clocks:
40     items:
41       - description: reference clock
42       - description: timer clock
43       - description: APB register access clock
44
45   "#clock-cells":
46     const: 1
47
48   clock-output-names:
49     maxItems: 4
50
51   assigned-clocks:
52     maxItems: 4
53
54   assigned-clock-parents:
55     maxItems: 4
56
57 additionalProperties: false
58
59 required:
60   - compatible
61   - reg
62   - clocks
63   - clock-names
64   - "#clock-cells"
65
66 examples:
67   - |
68     sysctl@20000 {
69         compatible = "arm,sp810", "arm,primecell";
70         reg = <0x020000 0x1000>;
71         clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
72         clock-names = "refclk", "timclk", "apb_pclk";
73         #clock-cells = <1>;
74         clock-output-names = "timerclken0", "timerclken1",
75                              "timerclken2", "timerclken3";
76         assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>,
77                           <&v2m_sysctl 3>, <&v2m_sysctl 3>;
78         assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>,
79                                  <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
80     };