1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/arm/pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Performance Monitor Units
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
14 ARM cores often have a PMU for counting cpu and cache events like cache misses
15 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
16 representation in the device tree should be done as under:-
25 - arm,armv8-pmuv3 # Only for s/w models
63 - qcom,scorpion-mp-pmu
66 # Don't know how many CPUs, so no constraints to specify
67 description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
70 $ref: /schemas/types.yaml#/definitions/phandle-array
74 When using SPIs, specifies a list of phandles to CPU
75 nodes corresponding directly to the affinity of
76 the SPIs listed in the interrupts property.
78 When using a PPI, specifies a list of phandles to CPU
79 nodes corresponding to the set of CPUs which have
80 a PMU of this type signalling the PPI listed in the
81 interrupts property, unless this is already specified
82 by the PPI interrupt specifier itself (in which case
83 the interrupt-affinity property shouldn't be present).
85 This property should be present when there is more than
91 Indicates that this PMU doesn't support the 0xc and 0xd events.
96 Indicates that the ARMv7 Secure Debug Enable Register
97 (SDER) is accessible. This will cause the driver to do
98 any setup required that is only possible in ARMv7 secure
99 state. If not present the ARMv7 SDER will not be touched,
100 which means the PMU may fail to operate unless external
101 code (bootloader or security monitor) has performed the
102 appropriate initialisation. Note that this property is
103 not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
109 additionalProperties: false