1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/arm/pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Performance Monitor Units
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
14 ARM cores often have a PMU for counting cpu and cache events like cache misses
15 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
16 representation in the device tree should be done as under:-
27 - arm,armv8-pmuv3 # Only for s/w models
70 - qcom,scorpion-mp-pmu
73 # Don't know how many CPUs, so no constraints to specify
74 description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
77 $ref: /schemas/types.yaml#/definitions/phandle-array
81 When using SPIs, specifies a list of phandles to CPU
82 nodes corresponding directly to the affinity of
83 the SPIs listed in the interrupts property.
85 When using a PPI, specifies a list of phandles to CPU
86 nodes corresponding to the set of CPUs which have
87 a PMU of this type signalling the PPI listed in the
88 interrupts property, unless this is already specified
89 by the PPI interrupt specifier itself (in which case
90 the interrupt-affinity property shouldn't be present).
92 This property should be present when there is more than
98 Indicates that this PMU doesn't support the 0xc and 0xd events.
103 Indicates that the ARMv7 Secure Debug Enable Register
104 (SDER) is accessible. This will cause the driver to do
105 any setup required that is only possible in ARMv7 secure
106 state. If not present the ARMv7 SDER will not be touched,
107 which means the PMU may fail to operate unless external
108 code (bootloader or security monitor) has performed the
109 appropriate initialisation. Note that this property is
110 not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
116 additionalProperties: false