1 * ARM Performance Monitor Units
3 ARM cores often have a PMU for counting cpu and cache events like cache misses
4 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
5 representation in the device tree should be done as under:-
9 - compatible : should be one of
25 "qcom,scorpion-mp-pmu"
27 - interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
28 interrupt (PPI) then 1 interrupt should be specified.
32 - interrupt-affinity : When using SPIs, specifies a list of phandles to CPU
33 nodes corresponding directly to the affinity of
34 the SPIs listed in the interrupts property.
36 When using a PPI, specifies a list of phandles to CPU
37 nodes corresponding to the set of CPUs which have
38 a PMU of this type signalling the PPI listed in the
41 This property should be present when there is more than
45 - qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
51 compatible = "arm,cortex-a9-pmu";
52 interrupts = <100 101>;