Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Last Level Cache Controller
   8
   9 maintainers:
  10   - Rishabh Bhatnagar <rishabhb@codeaurora.org>
  11   - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
  12
  13 description: |
  14   LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
  15   that can be shared by multiple clients. Clients here are different cores in the
  16   SoC, the idea is to minimize the local caches at the clients and migrate to
  17   common pool of memory. Cache memory is divided into partitions called slices
  18   which are assigned to clients. Clients can query the slice details, activate
  19   and deactivate them.
  20
  21 properties:
  22   compatible:
  23     enum:
  24       - qcom,sc7180-llcc
  25       - qcom,sc7280-llcc
  26       - qcom,sc8180x-llcc
  27       - qcom,sc8280xp-llcc
  28       - qcom,sdm845-llcc
  29       - qcom,sm6350-llcc
  30       - qcom,sm8150-llcc
  31       - qcom,sm8250-llcc
  32       - qcom,sm8350-llcc
  33       - qcom,sm8450-llcc
  34
  35   reg:
  36     items:
  37       - description: LLCC base register region
  38       - description: LLCC broadcast base register region
  39
  40   reg-names:
  41     items:
  42       - const: llcc_base
  43       - const: llcc_broadcast_base
  44
  45   interrupts:
  46     maxItems: 1
  47
  48 required:
  49   - compatible
  50   - reg
  51   - reg-names
  52
  53 additionalProperties: false
  54
  55 examples:
  56   - |
  57     #include <dt-bindings/interrupt-controller/arm-gic.h>
  58
  59     system-cache-controller@1100000 {
  60       compatible = "qcom,sdm845-llcc";
  61       reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
  62       reg-names = "llcc_base", "llcc_broadcast_base";
  63       interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
  64     };