Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: MediaTek Functional Clock Controller for MT8192
   8
   9 maintainers:
  10   - Chun-Jie Chen <chun-jie.chen@mediatek.com>
  11
  12 description:
  13   The Mediatek functional clock controller provides various clocks on MT8192.
  14
  15 properties:
  16   compatible:
  17     items:
  18       - enum:
  19           - mediatek,mt8192-scp_adsp
  20           - mediatek,mt8192-imp_iic_wrap_c
  21           - mediatek,mt8192-imp_iic_wrap_e
  22           - mediatek,mt8192-imp_iic_wrap_s
  23           - mediatek,mt8192-imp_iic_wrap_ws
  24           - mediatek,mt8192-imp_iic_wrap_w
  25           - mediatek,mt8192-imp_iic_wrap_n
  26           - mediatek,mt8192-msdc_top
  27           - mediatek,mt8192-mfgcfg
  28           - mediatek,mt8192-imgsys
  29           - mediatek,mt8192-imgsys2
  30           - mediatek,mt8192-vdecsys_soc
  31           - mediatek,mt8192-vdecsys
  32           - mediatek,mt8192-vencsys
  33           - mediatek,mt8192-camsys
  34           - mediatek,mt8192-camsys_rawa
  35           - mediatek,mt8192-camsys_rawb
  36           - mediatek,mt8192-camsys_rawc
  37           - mediatek,mt8192-ipesys
  38           - mediatek,mt8192-mdpsys
  39
  40   reg:
  41     maxItems: 1
  42
  43   '#clock-cells':
  44     const: 1
  45
  46 required:
  47   - compatible
  48   - reg
  49
  50 additionalProperties: false
  51
  52 examples:
  53   - |
  54     scp_adsp: clock-controller@10720000 {
  55         compatible = "mediatek,mt8192-scp_adsp";
  56         reg = <0x10720000 0x1000>;
  57         #clock-cells = <1>;
  58     };
  59
  60   - |
  61     imp_iic_wrap_c: clock-controller@11007000 {
  62         compatible = "mediatek,mt8192-imp_iic_wrap_c";
  63         reg = <0x11007000 0x1000>;
  64         #clock-cells = <1>;
  65     };
  66
  67   - |
  68     imp_iic_wrap_e: clock-controller@11cb1000 {
  69         compatible = "mediatek,mt8192-imp_iic_wrap_e";
  70         reg = <0x11cb1000 0x1000>;
  71         #clock-cells = <1>;
  72     };
  73
  74   - |
  75     imp_iic_wrap_s: clock-controller@11d03000 {
  76         compatible = "mediatek,mt8192-imp_iic_wrap_s";
  77         reg = <0x11d03000 0x1000>;
  78         #clock-cells = <1>;
  79     };
  80
  81   - |
  82     imp_iic_wrap_ws: clock-controller@11d23000 {
  83         compatible = "mediatek,mt8192-imp_iic_wrap_ws";
  84         reg = <0x11d23000 0x1000>;
  85         #clock-cells = <1>;
  86     };
  87
  88   - |
  89     imp_iic_wrap_w: clock-controller@11e01000 {
  90         compatible = "mediatek,mt8192-imp_iic_wrap_w";
  91         reg = <0x11e01000 0x1000>;
  92         #clock-cells = <1>;
  93     };
  94
  95   - |
  96     imp_iic_wrap_n: clock-controller@11f02000 {
  97         compatible = "mediatek,mt8192-imp_iic_wrap_n";
  98         reg = <0x11f02000 0x1000>;
  99         #clock-cells = <1>;
 100     };
 101
 102   - |
 103     msdc_top: clock-controller@11f10000 {
 104         compatible = "mediatek,mt8192-msdc_top";
 105         reg = <0x11f10000 0x1000>;
 106         #clock-cells = <1>;
 107     };
 108
 109   - |
 110     mfgcfg: clock-controller@13fbf000 {
 111         compatible = "mediatek,mt8192-mfgcfg";
 112         reg = <0x13fbf000 0x1000>;
 113         #clock-cells = <1>;
 114     };
 115
 116   - |
 117     imgsys: clock-controller@15020000 {
 118         compatible = "mediatek,mt8192-imgsys";
 119         reg = <0x15020000 0x1000>;
 120         #clock-cells = <1>;
 121     };
 122
 123   - |
 124     imgsys2: clock-controller@15820000 {
 125         compatible = "mediatek,mt8192-imgsys2";
 126         reg = <0x15820000 0x1000>;
 127         #clock-cells = <1>;
 128     };
 129
 130   - |
 131     vdecsys_soc: clock-controller@1600f000 {
 132         compatible = "mediatek,mt8192-vdecsys_soc";
 133         reg = <0x1600f000 0x1000>;
 134         #clock-cells = <1>;
 135     };
 136
 137   - |
 138     vdecsys: clock-controller@1602f000 {
 139         compatible = "mediatek,mt8192-vdecsys";
 140         reg = <0x1602f000 0x1000>;
 141         #clock-cells = <1>;
 142     };
 143
 144   - |
 145     vencsys: clock-controller@17000000 {
 146         compatible = "mediatek,mt8192-vencsys";
 147         reg = <0x17000000 0x1000>;
 148         #clock-cells = <1>;
 149     };
 150
 151   - |
 152     camsys: clock-controller@1a000000 {
 153         compatible = "mediatek,mt8192-camsys";
 154         reg = <0x1a000000 0x1000>;
 155         #clock-cells = <1>;
 156     };
 157
 158   - |
 159     camsys_rawa: clock-controller@1a04f000 {
 160         compatible = "mediatek,mt8192-camsys_rawa";
 161         reg = <0x1a04f000 0x1000>;
 162         #clock-cells = <1>;
 163     };
 164
 165   - |
 166     camsys_rawb: clock-controller@1a06f000 {
 167         compatible = "mediatek,mt8192-camsys_rawb";
 168         reg = <0x1a06f000 0x1000>;
 169         #clock-cells = <1>;
 170     };
 171
 172   - |
 173     camsys_rawc: clock-controller@1a08f000 {
 174         compatible = "mediatek,mt8192-camsys_rawc";
 175         reg = <0x1a08f000 0x1000>;
 176         #clock-cells = <1>;
 177     };
 178
 179   - |
 180     ipesys: clock-controller@1b000000 {
 181         compatible = "mediatek,mt8192-ipesys";
 182         reg = <0x1b000000 0x1000>;
 183         #clock-cells = <1>;
 184     };
 185
 186   - |
 187     mdpsys: clock-controller@1f000000 {
 188         compatible = "mediatek,mt8192-mdpsys";
 189         reg = <0x1f000000 0x1000>;
 190         #clock-cells = <1>;
 191     };