1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: MediaTek System Clock Controller for MT8186
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The clock architecture in MediaTek like below
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
22 The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
23 The mcusys provides mux control to select the clock source in AP MCU.
24 The device nodes also provide the system control capacity for configuration.
30 - mediatek,mt8186-mcusys
31 - mediatek,mt8186-topckgen
32 - mediatek,mt8186-infracfg_ao
33 - mediatek,mt8186-apmixedsys
49 additionalProperties: false
53 topckgen: syscon@10000000 {
54 compatible = "mediatek,mt8186-topckgen", "syscon";
55 reg = <0x10000000 0x1000>;