1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Functional Clock Controller for MT8186
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The clock architecture in MediaTek like below
20 The devices provide clock gate control in different IP blocks.
26 - mediatek,mt8186-imp_iic_wrap
27 - mediatek,mt8186-mfgsys
28 - mediatek,mt8186-wpesys
29 - mediatek,mt8186-imgsys1
30 - mediatek,mt8186-imgsys2
31 - mediatek,mt8186-vdecsys
32 - mediatek,mt8186-vencsys
33 - mediatek,mt8186-camsys
34 - mediatek,mt8186-camsys_rawa
35 - mediatek,mt8186-camsys_rawb
36 - mediatek,mt8186-mdpsys
37 - mediatek,mt8186-ipesys
48 additionalProperties: false
52 imp_iic_wrap: clock-controller@11017000 {
53 compatible = "mediatek,mt8186-imp_iic_wrap";
54 reg = <0x11017000 0x1000>;