Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: MediaTek Infrastructure System Configuration Controller
   8
   9 maintainers:
  10   - Matthias Brugger <matthias.bgg@gmail.com>
  11
  12 description:
  13   The Mediatek infracfg controller provides various clocks and reset outputs
  14   to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
  15   and reset values in <dt-bindings/reset/mt*-reset.h> and
  16   <dt-bindings/reset/mt*-resets.h>.
  17
  18 properties:
  19   compatible:
  20     oneOf:
  21       - items:
  22           - enum:
  23               - mediatek,mt2701-infracfg
  24               - mediatek,mt2712-infracfg
  25               - mediatek,mt6765-infracfg
  26               - mediatek,mt6795-infracfg
  27               - mediatek,mt6779-infracfg_ao
  28               - mediatek,mt6797-infracfg
  29               - mediatek,mt7622-infracfg
  30               - mediatek,mt7629-infracfg
  31               - mediatek,mt7981-infracfg
  32               - mediatek,mt7986-infracfg
  33               - mediatek,mt7988-infracfg
  34               - mediatek,mt8135-infracfg
  35               - mediatek,mt8167-infracfg
  36               - mediatek,mt8173-infracfg
  37               - mediatek,mt8183-infracfg
  38               - mediatek,mt8516-infracfg
  39           - const: syscon
  40       - items:
  41           - const: mediatek,mt7623-infracfg
  42           - const: mediatek,mt2701-infracfg
  43           - const: syscon
  44
  45   reg:
  46     maxItems: 1
  47
  48   '#clock-cells':
  49     const: 1
  50
  51   '#reset-cells':
  52     const: 1
  53
  54 required:
  55   - compatible
  56   - reg
  57   - '#clock-cells'
  58
  59 if:
  60   properties:
  61     compatible:
  62       contains:
  63         enum:
  64           - mediatek,mt2701-infracfg
  65           - mediatek,mt2712-infracfg
  66           - mediatek,mt6795-infracfg
  67           - mediatek,mt7622-infracfg
  68           - mediatek,mt7986-infracfg
  69           - mediatek,mt8135-infracfg
  70           - mediatek,mt8173-infracfg
  71           - mediatek,mt8183-infracfg
  72 then:
  73   required:
  74     - '#reset-cells'
  75
  76 additionalProperties: false
  77
  78 examples:
  79   - |
  80     infracfg: clock-controller@10001000 {
  81         compatible = "mediatek,mt8173-infracfg", "syscon";
  82         reg = <0x10001000 0x1000>;
  83         #clock-cells = <1>;
  84         #reset-cells = <1>;
  85     };