1 Marvell Armada AP80x System Controller
2 ======================================
4 The AP806/AP807 is one of the two core HW blocks of the Marvell Armada
5 7K/8K/931x SoCs. It contains system controllers, which provide several
6 registers giving access to numerous features: clocks, pin-muxing and
7 many other SoC configuration items. This DT binding allows to describe
8 these system controllers.
10 For the top level node:
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
21 The Device Tree node representing the AP806/AP807 system controller
22 provides a number of clocks:
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
31 - compatible: must be one of:
32 * "marvell,ap806-clock"
33 * "marvell,ap807-clock"
34 - #clock-cells: must be set to 1
39 For common binding part and usage, refer to
40 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
43 - compatible must be "marvell,ap806-pinctrl",
45 Available mpp pins/groups and functions:
46 Note: brackets (x) are not part of the mpp name for marvell,function and given
47 only for more detailed description in this document.
50 ================================================================================
51 mpp0 0 gpio, sdio(clk), spi0(clk)
52 mpp1 1 gpio, sdio(cmd), spi0(miso)
53 mpp2 2 gpio, sdio(d0), spi0(mosi)
54 mpp3 3 gpio, sdio(d1), spi0(cs0n)
55 mpp4 4 gpio, sdio(d2), i2c0(sda)
56 mpp5 5 gpio, sdio(d3), i2c0(sdk)
58 mpp7 7 gpio, sdio(d4), uart1(rxd)
59 mpp8 8 gpio, sdio(d5), uart1(txd)
60 mpp9 9 gpio, sdio(d6), spi0(cs1n)
61 mpp10 10 gpio, sdio(d7)
62 mpp11 11 gpio, uart0(txd)
63 mpp12 12 gpio, sdio(pw_off), sdio(hw_rst)
70 mpp19 19 gpio, uart0(rxd), sdio(pw_off)
74 For common binding part and usage, refer to
75 Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml.
79 - compatible: "marvell,armada-8k-gpio"
81 - offset: offset address inside the syscon block
85 - marvell,pwm-offset: offset address of PWM duration control registers inside
89 ap_syscon: system-controller@6f4000 {
90 compatible = "syscon", "simple-mfd";
91 reg = <0x6f4000 0x1000>;
94 compatible = "marvell,ap806-clock";
99 compatible = "marvell,ap806-pinctrl";
103 compatible = "marvell,armada-8k-gpio";
108 gpio-ranges = <&ap_pinctrl 0 0 19>;
109 marvell,pwm-offset = <0x10c0>;
111 clocks = <&ap_clk 3>;
121 For common binding part and usage, refer to
122 Documentation/devicetree/bindings/thermal/thermal*.yaml
124 The thermal IP can probe the temperature all around the processor. It
125 may feature several channels, each of them wired to one sensor.
127 It is possible to setup an overheat interrupt by giving at least one
128 critical point to any subnode of the thermal-zone node.
131 - compatible: must be one of:
132 * marvell,armada-ap806-thermal
133 - reg: register range associated with the thermal functions.
136 - interrupts: overheat interrupt handle. Should point to line 18 of the
137 SEI irqchip. See interrupt-controller/interrupts.txt
138 - #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
139 to this IP and represents the channel ID. There is one sensor per
140 channel. O refers to the thermal IP internal channel, while positive
141 IDs refer to each CPU.
144 ap_syscon1: system-controller@6f8000 {
145 compatible = "syscon", "simple-mfd";
146 reg = <0x6f8000 0x1000>;
148 ap_thermal: thermal-sensor@80 {
149 compatible = "marvell,armada-ap806-thermal";
151 interrupt-parent = <&sei>;
153 #thermal-sensor-cells = <1>;
160 Device Tree Clock bindings for cluster clock of Marvell
161 AP806/AP807. Each cluster contain up to 2 CPUs running at the same
165 - compatible: must be one of:
166 * "marvell,ap806-cpu-clock"
167 * "marvell,ap807-cpu-clock"
168 - #clock-cells : should be set to 1.
170 - clocks : shall be the input parent clock(s) phandle for the clock
173 - reg: register range associated with the cluster clocks
175 ap_syscon1: system-controller@6f8000 {
176 compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd";
177 reg = <0x6f8000 0x1000>;
179 cpu_clk: clock-cpu@278 {
180 compatible = "marvell,ap806-cpu-clock";
181 clocks = <&ap_clk 0>, <&ap_clk 1>;