1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/arm/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 The device tree allows to describe the layout of CPUs in a system through
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
19 https://www.devicetree.org/specifications/
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
23 ================================
24 Convention used in this document
25 ================================
27 This document follows the conventions described in the Devicetree
28 Specification, with the addition:
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
33 =====================================
34 cpus and cpu node bindings definition
35 =====================================
37 The ARM architecture, in accordance with the Devicetree Specification,
38 requires the cpus and cpu nodes to be present and contain the properties
45 Usage and definition depend on ARM architecture version and
48 On uniprocessor ARM architectures previous to v7
49 this property is required and must be set to 0.
51 On ARM 11 MPcore based systems this property is
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
59 On 32-bit ARM v7 or later systems this property is
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
66 All other bits in the reg cell must be set to 0.
68 On ARM v8 64-bit systems this property is required
69 and matches the MPIDR_EL1 register affinity bits.
71 * If cpus node's #address-cells property is set to 2
73 The first reg cell bits [7:0] must be set to
74 bits [39:32] of MPIDR_EL1.
76 The second reg cell bits [23:0] must be set to
77 bits [23:0] of MPIDR_EL1.
79 * If cpus node's #address-cells property is set to 1
81 The reg cell bits [23:0] must be set to bits [23:0]
84 All other bits in the reg cells must be set to 0.
122 - arm,armv8 # Only for s/w models
182 - nvidia,tegra132-denver
183 - nvidia,tegra186-denver
184 - nvidia,tegra194-carmel
204 $ref: /schemas/types.yaml#/definitions/string
206 # On ARM v8 64-bit this property is required
210 # On ARM 32-bit systems this property is optional
213 - allwinner,sun6i-a31
214 - allwinner,sun8i-a23
215 - allwinner,sun9i-a80-smp
216 - allwinner,sun8i-a83t-smp
218 - amlogic,meson8b-smp
221 - brcm,bcm11351-cpu-method
227 - marvell,armada-375-smp
228 - marvell,armada-380-smp
229 - marvell,armada-390-smp
230 - marvell,armada-xp-smp
231 - marvell,98dx3236-smp
233 - mediatek,mt6589-smp
234 - mediatek,mt81xx-tz-smp
240 # Only valid on ARM 32-bit, see above for ARM v8 64-bit
243 - renesas,r9a06g032-smp
244 - rockchip,rk3036-smp
245 - rockchip,rk3066-smp
246 - socionext,milbeaut-m10v-smp
253 - $ref: /schemas/types.yaml#/definitions/uint32
254 - $ref: /schemas/types.yaml#/definitions/uint64
256 The DT specification defines this as 64-bit always, but some 32-bit Arm
257 systems have used a 32-bit value which must be supported.
258 Required for systems that have an "enable-method"
259 property value of "spin-table".
262 $ref: /schemas/types.yaml#/definitions/phandle-array
266 List of phandles to idle state nodes supported
267 by this cpu (see ./idle-states.yaml).
271 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
272 DMIPS/MHz, relative to highest capacity-dmips-mhz
275 cci-control-port: true
277 dynamic-power-coefficient:
278 $ref: /schemas/types.yaml#/definitions/uint32
280 A u32 value that represents the running time dynamic
281 power coefficient in units of uW/MHz/V^2. The
282 coefficient can either be calculated from power
283 measurements or derived by analysis.
285 The dynamic power consumption of the CPU is
286 proportional to the square of the Voltage (V) and
287 the clock frequency (f). The coefficient is used to
288 calculate the dynamic power as below -
290 Pdyn = dynamic-power-coefficient * V^2 * f
292 where voltage is in V, frequency is in MHz.
297 List of phandles and performance domain specifiers, as defined by
298 bindings of the performance domain provider. See also
299 dvfs/performance-domain.yaml.
303 List of phandles and PM domain specifiers, as defined by bindings of the
304 PM domain provider (see also ../power_domain.txt).
308 A list of power domain name strings sorted in the same order as the
309 power-domains property.
311 For PSCI based platforms, the name corresponding to the index of the PSCI
312 PM domain provider, must be "psci". For SCMI based platforms, the name
313 corresponding to the index of an SCMI performance domain provider, must be
317 $ref: /schemas/types.yaml#/definitions/phandle
319 Specifies the SAW* node associated with this CPU.
321 Required for systems that have an "enable-method" property
322 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
324 * arm/msm/qcom,saw2.txt
327 $ref: /schemas/types.yaml#/definitions/phandle
329 Specifies the ACC* node associated with this CPU.
331 Required for systems that have an "enable-method" property
332 value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
335 * arm/msm/qcom,kpss-acc.txt
338 $ref: /schemas/types.yaml#/definitions/phandle
340 Specifies the syscon node controlling the cpu core power domains.
342 Optional for systems that have an "enable-method"
343 property value of "rockchip,rk3066-smp"
344 While optional, it is the preferred way to get access to
345 the cpu-core power-domains.
348 $ref: /schemas/types.yaml#/definitions/uint32
350 Required for systems that have an "enable-method" property value of
351 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
353 This includes the following SoCs: |
354 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
355 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
357 The secondary-boot-reg property is a u32 value that specifies the
358 physical address of the register used to request the ROM holding pen
359 code release a secondary CPU. The value written to the register is
360 formed by encoding the target CPU id into the low bits of the
361 physical start address it should jump to.
364 # If the enable-method property contains one of those values
369 - brcm,bcm11351-cpu-method
372 # and if enable-method is present
386 rockchip,pmu: [enable-method]
388 additionalProperties: true
394 #address-cells = <1>;
398 compatible = "arm,cortex-a15";
404 compatible = "arm,cortex-a15";
410 compatible = "arm,cortex-a7";
416 compatible = "arm,cortex-a7";
422 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
425 #address-cells = <1>;
429 compatible = "arm,cortex-a8";
435 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
438 #address-cells = <1>;
442 compatible = "arm,arm926ej-s";
448 // Example 4 (ARM Cortex-A57 64-bit system):
451 #address-cells = <2>;
455 compatible = "arm,cortex-a57";
457 enable-method = "spin-table";
458 cpu-release-addr = <0 0x20000000>;
463 compatible = "arm,cortex-a57";
465 enable-method = "spin-table";
466 cpu-release-addr = <0 0x20000000>;
471 compatible = "arm,cortex-a57";
473 enable-method = "spin-table";
474 cpu-release-addr = <0 0x20000000>;
479 compatible = "arm,cortex-a57";
481 enable-method = "spin-table";
482 cpu-release-addr = <0 0x20000000>;
487 compatible = "arm,cortex-a57";
489 enable-method = "spin-table";
490 cpu-release-addr = <0 0x20000000>;
495 compatible = "arm,cortex-a57";
497 enable-method = "spin-table";
498 cpu-release-addr = <0 0x20000000>;
503 compatible = "arm,cortex-a57";
505 enable-method = "spin-table";
506 cpu-release-addr = <0 0x20000000>;
511 compatible = "arm,cortex-a57";
513 enable-method = "spin-table";
514 cpu-release-addr = <0 0x20000000>;
519 compatible = "arm,cortex-a57";
521 enable-method = "spin-table";
522 cpu-release-addr = <0 0x20000000>;
527 compatible = "arm,cortex-a57";
529 enable-method = "spin-table";
530 cpu-release-addr = <0 0x20000000>;
535 compatible = "arm,cortex-a57";
537 enable-method = "spin-table";
538 cpu-release-addr = <0 0x20000000>;
543 compatible = "arm,cortex-a57";
545 enable-method = "spin-table";
546 cpu-release-addr = <0 0x20000000>;
551 compatible = "arm,cortex-a57";
553 enable-method = "spin-table";
554 cpu-release-addr = <0 0x20000000>;
559 compatible = "arm,cortex-a57";
561 enable-method = "spin-table";
562 cpu-release-addr = <0 0x20000000>;
567 compatible = "arm,cortex-a57";
569 enable-method = "spin-table";
570 cpu-release-addr = <0 0x20000000>;
575 compatible = "arm,cortex-a57";
577 enable-method = "spin-table";
578 cpu-release-addr = <0 0x20000000>;