1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/arm/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM CPUs bindings
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 The device tree allows to describe the layout of CPUs in a system through
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
19 https://www.devicetree.org/specifications/
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
23 ================================
24 Convention used in this document
25 ================================
27 This document follows the conventions described in the Devicetree
28 Specification, with the addition:
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
33 =====================================
34 cpus and cpu node bindings definition
35 =====================================
37 The ARM architecture, in accordance with the Devicetree Specification,
38 requires the cpus and cpu nodes to be present and contain the properties
45 Usage and definition depend on ARM architecture version and
48 On uniprocessor ARM architectures previous to v7
49 this property is required and must be set to 0.
51 On ARM 11 MPcore based systems this property is
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
59 On 32-bit ARM v7 or later systems this property is
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
66 All other bits in the reg cell must be set to 0.
68 On ARM v8 64-bit systems this property is required
69 and matches the MPIDR_EL1 register affinity bits.
71 * If cpus node's #address-cells property is set to 2
73 The first reg cell bits [7:0] must be set to
74 bits [39:32] of MPIDR_EL1.
76 The second reg cell bits [23:0] must be set to
77 bits [23:0] of MPIDR_EL1.
79 * If cpus node's #address-cells property is set to 1
81 The reg cell bits [23:0] must be set to bits [23:0]
84 All other bits in the reg cells must be set to 0.
120 - arm,armv8 # Only for s/w models
164 - nvidia,tegra132-denver
165 - nvidia,tegra186-denver
166 - nvidia,tegra194-carmel
178 $ref: '/schemas/types.yaml#/definitions/string'
180 # On ARM v8 64-bit this property is required
184 # On ARM 32-bit systems this property is optional
187 - allwinner,sun6i-a31
188 - allwinner,sun8i-a23
189 - allwinner,sun9i-a80-smp
190 - allwinner,sun8i-a83t-smp
192 - amlogic,meson8b-smp
195 - brcm,bcm11351-cpu-method
201 - marvell,armada-375-smp
202 - marvell,armada-380-smp
203 - marvell,armada-390-smp
204 - marvell,armada-xp-smp
205 - marvell,98dx3236-smp
207 - mediatek,mt6589-smp
208 - mediatek,mt81xx-tz-smp
213 - renesas,r9a06g032-smp
214 - rockchip,rk3036-smp
215 - rockchip,rk3066-smp
216 - socionext,milbeaut-m10v-smp
222 $ref: '/schemas/types.yaml#/definitions/uint64'
225 Required for systems that have an "enable-method"
226 property value of "spin-table".
227 On ARM v8 64-bit systems must be a two cell
228 property identifying a 64-bit zero-initialised
232 $ref: '/schemas/types.yaml#/definitions/phandle-array'
234 List of phandles to idle state nodes supported
235 by this cpu (see ./idle-states.yaml).
239 u32 value representing CPU capacity (see ./cpu-capacity.txt) in
240 DMIPS/MHz, relative to highest capacity-dmips-mhz
243 dynamic-power-coefficient:
244 $ref: '/schemas/types.yaml#/definitions/uint32'
246 A u32 value that represents the running time dynamic
247 power coefficient in units of uW/MHz/V^2. The
248 coefficient can either be calculated from power
249 measurements or derived by analysis.
251 The dynamic power consumption of the CPU is
252 proportional to the square of the Voltage (V) and
253 the clock frequency (f). The coefficient is used to
254 calculate the dynamic power as below -
256 Pdyn = dynamic-power-coefficient * V^2 * f
258 where voltage is in V, frequency is in MHz.
263 List of phandles and performance domain specifiers, as defined by
264 bindings of the performance domain provider. See also
265 dvfs/performance-domain.yaml.
269 List of phandles and PM domain specifiers, as defined by bindings of the
270 PM domain provider (see also ../power_domain.txt).
274 A list of power domain name strings sorted in the same order as the
275 power-domains property.
277 For PSCI based platforms, the name corresponding to the index of the PSCI
278 PM domain provider, must be "psci".
281 $ref: '/schemas/types.yaml#/definitions/phandle'
283 Specifies the SAW* node associated with this CPU.
285 Required for systems that have an "enable-method" property
286 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
288 * arm/msm/qcom,saw2.txt
291 $ref: '/schemas/types.yaml#/definitions/phandle'
293 Specifies the ACC* node associated with this CPU.
295 Required for systems that have an "enable-method" property
296 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
298 * arm/msm/qcom,kpss-acc.txt
301 $ref: '/schemas/types.yaml#/definitions/phandle'
303 Specifies the syscon node controlling the cpu core power domains.
305 Optional for systems that have an "enable-method"
306 property value of "rockchip,rk3066-smp"
307 While optional, it is the preferred way to get access to
308 the cpu-core power-domains.
311 $ref: '/schemas/types.yaml#/definitions/uint32'
313 Required for systems that have an "enable-method" property value of
314 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
316 This includes the following SoCs: |
317 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
318 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
320 The secondary-boot-reg property is a u32 value that specifies the
321 physical address of the register used to request the ROM holding pen
322 code release a secondary CPU. The value written to the register is
323 formed by encoding the target CPU id into the low bits of the
324 physical start address it should jump to.
327 # If the enable-method property contains one of those values
332 - brcm,bcm11351-cpu-method
335 # and if enable-method is present
349 rockchip,pmu: [enable-method]
351 additionalProperties: true
357 #address-cells = <1>;
361 compatible = "arm,cortex-a15";
367 compatible = "arm,cortex-a15";
373 compatible = "arm,cortex-a7";
379 compatible = "arm,cortex-a7";
385 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
388 #address-cells = <1>;
392 compatible = "arm,cortex-a8";
398 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
401 #address-cells = <1>;
405 compatible = "arm,arm926ej-s";
411 // Example 4 (ARM Cortex-A57 64-bit system):
414 #address-cells = <2>;
418 compatible = "arm,cortex-a57";
420 enable-method = "spin-table";
421 cpu-release-addr = <0 0x20000000>;
426 compatible = "arm,cortex-a57";
428 enable-method = "spin-table";
429 cpu-release-addr = <0 0x20000000>;
434 compatible = "arm,cortex-a57";
436 enable-method = "spin-table";
437 cpu-release-addr = <0 0x20000000>;
442 compatible = "arm,cortex-a57";
444 enable-method = "spin-table";
445 cpu-release-addr = <0 0x20000000>;
450 compatible = "arm,cortex-a57";
452 enable-method = "spin-table";
453 cpu-release-addr = <0 0x20000000>;
458 compatible = "arm,cortex-a57";
460 enable-method = "spin-table";
461 cpu-release-addr = <0 0x20000000>;
466 compatible = "arm,cortex-a57";
468 enable-method = "spin-table";
469 cpu-release-addr = <0 0x20000000>;
474 compatible = "arm,cortex-a57";
476 enable-method = "spin-table";
477 cpu-release-addr = <0 0x20000000>;
482 compatible = "arm,cortex-a57";
484 enable-method = "spin-table";
485 cpu-release-addr = <0 0x20000000>;
490 compatible = "arm,cortex-a57";
492 enable-method = "spin-table";
493 cpu-release-addr = <0 0x20000000>;
498 compatible = "arm,cortex-a57";
500 enable-method = "spin-table";
501 cpu-release-addr = <0 0x20000000>;
506 compatible = "arm,cortex-a57";
508 enable-method = "spin-table";
509 cpu-release-addr = <0 0x20000000>;
514 compatible = "arm,cortex-a57";
516 enable-method = "spin-table";
517 cpu-release-addr = <0 0x20000000>;
522 compatible = "arm,cortex-a57";
524 enable-method = "spin-table";
525 cpu-release-addr = <0 0x20000000>;
530 compatible = "arm,cortex-a57";
532 enable-method = "spin-table";
533 cpu-release-addr = <0 0x20000000>;
538 compatible = "arm,cortex-a57";
540 enable-method = "spin-table";
541 cpu-release-addr = <0 0x20000000>;