5 The device tree allows to describe the layout of CPUs in a system through
6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7 defining properties for every cpu.
9 Bindings for CPU nodes follow the Devicetree Specification, available from:
11 https://www.devicetree.org/specifications/
13 with updates for 32-bit and 64-bit ARM systems provided in this document.
15 ================================
16 Convention used in this document
17 ================================
19 This document follows the conventions described in the Devicetree
20 Specification, with the addition:
22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
23 the reg property contained in bits 7 down to 0
25 =====================================
26 cpus and cpu node bindings definition
27 =====================================
29 The ARM architecture, in accordance with the Devicetree Specification,
30 requires the cpus and cpu nodes to be present and contain the properties
35 Description: Container of cpu nodes
37 The node name must be "cpus".
39 A cpus node must define the following properties:
45 Definition depends on ARM architecture version and
48 # On uniprocessor ARM architectures previous to v7
49 value must be 1, to enable a simple enumeration
50 scheme for processors that do not have a HW CPU
51 identification register.
52 # On 32-bit ARM 11 MPcore, ARM v7 or later systems
53 value must be 1, that corresponds to CPUID/MPIDR
55 # On ARM v8 64-bit systems value should be set to 2,
56 that corresponds to the MPIDR_EL1 register size.
57 If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
58 in the system, #address-cells can be set to 1, since
59 MPIDR_EL1[63:32] bits are not used for CPUs
64 Definition: must be set to 0
68 Description: Describes a CPU in an ARM based system
75 Definition: must be "cpu"
77 Usage and definition depend on ARM architecture version and
80 # On uniprocessor ARM architectures previous to v7
81 this property is required and must be set to 0.
83 # On ARM 11 MPcore based systems this property is
84 required and matches the CPUID[11:0] register bits.
86 Bits [11:0] in the reg cell must be set to
87 bits [11:0] in CPU ID register.
89 All other bits in the reg cell must be set to 0.
91 # On 32-bit ARM v7 or later systems this property is
92 required and matches the CPU MPIDR[23:0] register
95 Bits [23:0] in the reg cell must be set to
98 All other bits in the reg cell must be set to 0.
100 # On ARM v8 64-bit systems this property is required
101 and matches the MPIDR_EL1 register affinity bits.
103 * If cpus node's #address-cells property is set to 2
105 The first reg cell bits [7:0] must be set to
106 bits [39:32] of MPIDR_EL1.
108 The second reg cell bits [23:0] must be set to
109 bits [23:0] of MPIDR_EL1.
111 * If cpus node's #address-cells property is set to 1
113 The reg cell bits [23:0] must be set to bits [23:0]
116 All other bits in the reg cells must be set to 0.
121 Definition: should be one of:
184 "nvidia,tegra132-denver"
185 "nvidia,tegra186-denver"
186 "nvidia,tegra194-carmel"
192 Value type: <stringlist>
193 Usage and definition depend on ARM architecture version.
194 # On ARM v8 64-bit this property is required and must
198 # On ARM 32-bit systems this property is optional and
201 "allwinner,sun6i-a31"
202 "allwinner,sun8i-a23"
203 "allwinner,sun9i-a80-smp"
205 "amlogic,meson8b-smp"
207 "brcm,bcm11351-cpu-method"
212 "marvell,armada-375-smp"
213 "marvell,armada-380-smp"
214 "marvell,armada-390-smp"
215 "marvell,armada-xp-smp"
216 "marvell,98dx3236-smp"
217 "mediatek,mt6589-smp"
218 "mediatek,mt81xx-tz-smp"
223 "renesas,r9a06g032-smp"
224 "rockchip,rk3036-smp"
225 "rockchip,rk3066-smp"
229 Usage: required for systems that have an "enable-method"
230 property value of "spin-table".
231 Value type: <prop-encoded-array>
233 # On ARM v8 64-bit systems must be a two cell
234 property identifying a 64-bit zero-initialised
238 Usage: required for systems that have an "enable-method"
239 property value of "qcom,kpss-acc-v1" or
241 Value type: <phandle>
242 Definition: Specifies the SAW[1] node associated with this CPU.
245 Usage: required for systems that have an "enable-method"
246 property value of "qcom,kpss-acc-v1" or
248 Value type: <phandle>
249 Definition: Specifies the ACC[2] node associated with this CPU.
253 Value type: <prop-encoded-array>
255 # List of phandles to idle state nodes supported
262 # u32 value representing CPU capacity [4] in
263 DMIPS/MHz, relative to highest capacity-dmips-mhz
267 Usage: optional for systems that have an "enable-method"
268 property value of "rockchip,rk3066-smp"
269 While optional, it is the preferred way to get access to
270 the cpu-core power-domains.
271 Value type: <phandle>
272 Definition: Specifies the syscon node controlling the cpu core
275 - dynamic-power-coefficient
277 Value type: <prop-encoded-array>
278 Definition: A u32 value that represents the running time dynamic
279 power coefficient in units of mW/MHz/uV^2. The
280 coefficient can either be calculated from power
281 measurements or derived by analysis.
283 The dynamic power consumption of the CPU is
284 proportional to the square of the Voltage (V) and
285 the clock frequency (f). The coefficient is used to
286 calculate the dynamic power as below -
288 Pdyn = dynamic-power-coefficient * V^2 * f
290 where voltage is in uV, frequency is in MHz.
292 Example 1 (dual-cluster big.LITTLE system 32-bit):
296 #address-cells = <1>;
300 compatible = "arm,cortex-a15";
306 compatible = "arm,cortex-a15";
312 compatible = "arm,cortex-a7";
318 compatible = "arm,cortex-a7";
323 Example 2 (Cortex-A8 uniprocessor 32-bit system):
327 #address-cells = <1>;
331 compatible = "arm,cortex-a8";
336 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
340 #address-cells = <1>;
344 compatible = "arm,arm926ej-s";
349 Example 4 (ARM Cortex-A57 64-bit system):
353 #address-cells = <2>;
357 compatible = "arm,cortex-a57";
359 enable-method = "spin-table";
360 cpu-release-addr = <0 0x20000000>;
365 compatible = "arm,cortex-a57";
367 enable-method = "spin-table";
368 cpu-release-addr = <0 0x20000000>;
373 compatible = "arm,cortex-a57";
375 enable-method = "spin-table";
376 cpu-release-addr = <0 0x20000000>;
381 compatible = "arm,cortex-a57";
383 enable-method = "spin-table";
384 cpu-release-addr = <0 0x20000000>;
389 compatible = "arm,cortex-a57";
391 enable-method = "spin-table";
392 cpu-release-addr = <0 0x20000000>;
397 compatible = "arm,cortex-a57";
399 enable-method = "spin-table";
400 cpu-release-addr = <0 0x20000000>;
405 compatible = "arm,cortex-a57";
407 enable-method = "spin-table";
408 cpu-release-addr = <0 0x20000000>;
413 compatible = "arm,cortex-a57";
415 enable-method = "spin-table";
416 cpu-release-addr = <0 0x20000000>;
421 compatible = "arm,cortex-a57";
423 enable-method = "spin-table";
424 cpu-release-addr = <0 0x20000000>;
429 compatible = "arm,cortex-a57";
431 enable-method = "spin-table";
432 cpu-release-addr = <0 0x20000000>;
437 compatible = "arm,cortex-a57";
439 enable-method = "spin-table";
440 cpu-release-addr = <0 0x20000000>;
445 compatible = "arm,cortex-a57";
447 enable-method = "spin-table";
448 cpu-release-addr = <0 0x20000000>;
453 compatible = "arm,cortex-a57";
455 enable-method = "spin-table";
456 cpu-release-addr = <0 0x20000000>;
461 compatible = "arm,cortex-a57";
463 enable-method = "spin-table";
464 cpu-release-addr = <0 0x20000000>;
469 compatible = "arm,cortex-a57";
471 enable-method = "spin-table";
472 cpu-release-addr = <0 0x20000000>;
477 compatible = "arm,cortex-a57";
479 enable-method = "spin-table";
480 cpu-release-addr = <0 0x20000000>;
485 [1] arm/msm/qcom,saw2.txt
486 [2] arm/msm/qcom,kpss-acc.txt
487 [3] ARM Linux kernel documentation - idle states bindings
488 Documentation/devicetree/bindings/arm/idle-states.txt
489 [4] ARM Linux kernel documentation - cpu capacity bindings
490 Documentation/devicetree/bindings/arm/cpu-capacity.txt