Documentation/devicetree/bindings/arm/cpus.txt

   1 =================
   2 ARM CPUs bindings
   3 =================
   4
   5 The device tree allows to describe the layout of CPUs in a system through
   6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
   7 defining properties for every cpu.
   8
   9 Bindings for CPU nodes follow the Devicetree Specification, available from:
  10
  11 https://www.devicetree.org/specifications/
  12
  13 with updates for 32-bit and 64-bit ARM systems provided in this document.
  14
  15 ================================
  16 Convention used in this document
  17 ================================
  18
  19 This document follows the conventions described in the Devicetree
  20 Specification, with the addition:
  21
  22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
  23   the reg property contained in bits 7 down to 0
  24
  25 =====================================
  26 cpus and cpu node bindings definition
  27 =====================================
  28
  29 The ARM architecture, in accordance with the Devicetree Specification,
  30 requires the cpus and cpu nodes to be present and contain the properties
  31 described below.
  32
  33 - cpus node
  34
  35         Description: Container of cpu nodes
  36
  37         The node name must be "cpus".
  38
  39         A cpus node must define the following properties:
  40
  41         - #address-cells
  42                 Usage: required
  43                 Value type: <u32>
  44
  45                 Definition depends on ARM architecture version and
  46                 configuration:
  47
  48                         # On uniprocessor ARM architectures previous to v7
  49                           value must be 1, to enable a simple enumeration
  50                           scheme for processors that do not have a HW CPU
  51                           identification register.
  52                         # On 32-bit ARM 11 MPcore, ARM v7 or later systems
  53                           value must be 1, that corresponds to CPUID/MPIDR
  54                           registers sizes.
  55                         # On ARM v8 64-bit systems value should be set to 2,
  56                           that corresponds to the MPIDR_EL1 register size.
  57                           If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
  58                           in the system, #address-cells can be set to 1, since
  59                           MPIDR_EL1[63:32] bits are not used for CPUs
  60                           identification.
  61         - #size-cells
  62                 Usage: required
  63                 Value type: <u32>
  64                 Definition: must be set to 0
  65
  66 - cpu node
  67
  68         Description: Describes a CPU in an ARM based system
  69
  70         PROPERTIES
  71
  72         - device_type
  73                 Usage: required
  74                 Value type: <string>
  75                 Definition: must be "cpu"
  76         - reg
  77                 Usage and definition depend on ARM architecture version and
  78                 configuration:
  79
  80                         # On uniprocessor ARM architectures previous to v7
  81                           this property is required and must be set to 0.
  82
  83                         # On ARM 11 MPcore based systems this property is
  84                           required and matches the CPUID[11:0] register bits.
  85
  86                           Bits [11:0] in the reg cell must be set to
  87                           bits [11:0] in CPU ID register.
  88
  89                           All other bits in the reg cell must be set to 0.
  90
  91                         # On 32-bit ARM v7 or later systems this property is
  92                           required and matches the CPU MPIDR[23:0] register
  93                           bits.
  94
  95                           Bits [23:0] in the reg cell must be set to
  96                           bits [23:0] in MPIDR.
  97
  98                           All other bits in the reg cell must be set to 0.
  99
 100                         # On ARM v8 64-bit systems this property is required
 101                           and matches the MPIDR_EL1 register affinity bits.
 102
 103                           * If cpus node's #address-cells property is set to 2
 104
 105                             The first reg cell bits [7:0] must be set to
 106                             bits [39:32] of MPIDR_EL1.
 107
 108                             The second reg cell bits [23:0] must be set to
 109                             bits [23:0] of MPIDR_EL1.
 110
 111                           * If cpus node's #address-cells property is set to 1
 112
 113                             The reg cell bits [23:0] must be set to bits [23:0]
 114                             of MPIDR_EL1.
 115
 116                           All other bits in the reg cells must be set to 0.
 117
 118         - compatible:
 119                 Usage: required
 120                 Value type: <string>
 121                 Definition: should be one of:
 122                             "arm,arm710t"
 123                             "arm,arm720t"
 124                             "arm,arm740t"
 125                             "arm,arm7ej-s"
 126                             "arm,arm7tdmi"
 127                             "arm,arm7tdmi-s"
 128                             "arm,arm9es"
 129                             "arm,arm9ej-s"
 130                             "arm,arm920t"
 131                             "arm,arm922t"
 132                             "arm,arm925"
 133                             "arm,arm926e-s"
 134                             "arm,arm926ej-s"
 135                             "arm,arm940t"
 136                             "arm,arm946e-s"
 137                             "arm,arm966e-s"
 138                             "arm,arm968e-s"
 139                             "arm,arm9tdmi"
 140                             "arm,arm1020e"
 141                             "arm,arm1020t"
 142                             "arm,arm1022e"
 143                             "arm,arm1026ej-s"
 144                             "arm,arm1136j-s"
 145                             "arm,arm1136jf-s"
 146                             "arm,arm1156t2-s"
 147                             "arm,arm1156t2f-s"
 148                             "arm,arm1176jzf"
 149                             "arm,arm1176jz-s"
 150                             "arm,arm1176jzf-s"
 151                             "arm,arm11mpcore"
 152                             "arm,cortex-a5"
 153                             "arm,cortex-a7"
 154                             "arm,cortex-a8"
 155                             "arm,cortex-a9"
 156                             "arm,cortex-a12"
 157                             "arm,cortex-a15"
 158                             "arm,cortex-a17"
 159                             "arm,cortex-a53"
 160                             "arm,cortex-a57"
 161                             "arm,cortex-a72"
 162                             "arm,cortex-a73"
 163                             "arm,cortex-m0"
 164                             "arm,cortex-m0+"
 165                             "arm,cortex-m1"
 166                             "arm,cortex-m3"
 167                             "arm,cortex-m4"
 168                             "arm,cortex-r4"
 169                             "arm,cortex-r5"
 170                             "arm,cortex-r7"
 171                             "brcm,brahma-b15"
 172                             "brcm,vulcan"
 173                             "cavium,thunder"
 174                             "cavium,thunder2"
 175                             "faraday,fa526"
 176                             "intel,sa110"
 177                             "intel,sa1100"
 178                             "marvell,feroceon"
 179                             "marvell,mohawk"
 180                             "marvell,pj4a"
 181                             "marvell,pj4b"
 182                             "marvell,sheeva-v5"
 183                             "nvidia,tegra132-denver"
 184                             "nvidia,tegra186-denver"
 185                             "qcom,krait"
 186                             "qcom,kryo"
 187                             "qcom,scorpion"
 188         - enable-method
 189                 Value type: <stringlist>
 190                 Usage and definition depend on ARM architecture version.
 191                         # On ARM v8 64-bit this property is required and must
 192                           be one of:
 193                              "psci"
 194                              "spin-table"
 195                         # On ARM 32-bit systems this property is optional and
 196                           can be one of:
 197                             "actions,s500-smp"
 198                             "allwinner,sun6i-a31"
 199                             "allwinner,sun8i-a23"
 200                             "arm,realview-smp"
 201                             "brcm,bcm11351-cpu-method"
 202                             "brcm,bcm23550"
 203                             "brcm,bcm2836-smp"
 204                             "brcm,bcm-nsp-smp"
 205                             "brcm,brahma-b15"
 206                             "marvell,armada-375-smp"
 207                             "marvell,armada-380-smp"
 208                             "marvell,armada-390-smp"
 209                             "marvell,armada-xp-smp"
 210                             "marvell,98dx3236-smp"
 211                             "mediatek,mt6589-smp"
 212                             "mediatek,mt81xx-tz-smp"
 213                             "qcom,gcc-msm8660"
 214                             "qcom,kpss-acc-v1"
 215                             "qcom,kpss-acc-v2"
 216                             "renesas,apmu"
 217                             "rockchip,rk3036-smp"
 218                             "rockchip,rk3066-smp"
 219                             "ste,dbx500-smp"
 220
 221         - cpu-release-addr
 222                 Usage: required for systems that have an "enable-method"
 223                        property value of "spin-table".
 224                 Value type: <prop-encoded-array>
 225                 Definition:
 226                         # On ARM v8 64-bit systems must be a two cell
 227                           property identifying a 64-bit zero-initialised
 228                           memory location.
 229
 230         - qcom,saw
 231                 Usage: required for systems that have an "enable-method"
 232                        property value of "qcom,kpss-acc-v1" or
 233                        "qcom,kpss-acc-v2"
 234                 Value type: <phandle>
 235                 Definition: Specifies the SAW[1] node associated with this CPU.
 236
 237         - qcom,acc
 238                 Usage: required for systems that have an "enable-method"
 239                        property value of "qcom,kpss-acc-v1" or
 240                        "qcom,kpss-acc-v2"
 241                 Value type: <phandle>
 242                 Definition: Specifies the ACC[2] node associated with this CPU.
 243
 244         - cpu-idle-states
 245                 Usage: Optional
 246                 Value type: <prop-encoded-array>
 247                 Definition:
 248                         # List of phandles to idle state nodes supported
 249                           by this cpu [3].
 250
 251         - capacity-dmips-mhz
 252                 Usage: Optional
 253                 Value type: <u32>
 254                 Definition:
 255                         # u32 value representing CPU capacity [4] in
 256                           DMIPS/MHz, relative to highest capacity-dmips-mhz
 257                           in the system.
 258
 259         - rockchip,pmu
 260                 Usage: optional for systems that have an "enable-method"
 261                        property value of "rockchip,rk3066-smp"
 262                        While optional, it is the preferred way to get access to
 263                        the cpu-core power-domains.
 264                 Value type: <phandle>
 265                 Definition: Specifies the syscon node controlling the cpu core
 266                             power domains.
 267
 268         - dynamic-power-coefficient
 269                 Usage: optional
 270                 Value type: <prop-encoded-array>
 271                 Definition: A u32 value that represents the running time dynamic
 272                             power coefficient in units of mW/MHz/uV^2. The
 273                             coefficient can either be calculated from power
 274                             measurements or derived by analysis.
 275
 276                             The dynamic power consumption of the CPU  is
 277                             proportional to the square of the Voltage (V) and
 278                             the clock frequency (f). The coefficient is used to
 279                             calculate the dynamic power as below -
 280
 281                             Pdyn = dynamic-power-coefficient * V^2 * f
 282
 283                             where voltage is in uV, frequency is in MHz.
 284
 285 Example 1 (dual-cluster big.LITTLE system 32-bit):
 286
 287         cpus {
 288                 #size-cells = <0>;
 289                 #address-cells = <1>;
 290
 291                 cpu@0 {
 292                         device_type = "cpu";
 293                         compatible = "arm,cortex-a15";
 294                         reg = <0x0>;
 295                 };
 296
 297                 cpu@1 {
 298                         device_type = "cpu";
 299                         compatible = "arm,cortex-a15";
 300                         reg = <0x1>;
 301                 };
 302
 303                 cpu@100 {
 304                         device_type = "cpu";
 305                         compatible = "arm,cortex-a7";
 306                         reg = <0x100>;
 307                 };
 308
 309                 cpu@101 {
 310                         device_type = "cpu";
 311                         compatible = "arm,cortex-a7";
 312                         reg = <0x101>;
 313                 };
 314         };
 315
 316 Example 2 (Cortex-A8 uniprocessor 32-bit system):
 317
 318         cpus {
 319                 #size-cells = <0>;
 320                 #address-cells = <1>;
 321
 322                 cpu@0 {
 323                         device_type = "cpu";
 324                         compatible = "arm,cortex-a8";
 325                         reg = <0x0>;
 326                 };
 327         };
 328
 329 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
 330
 331         cpus {
 332                 #size-cells = <0>;
 333                 #address-cells = <1>;
 334
 335                 cpu@0 {
 336                         device_type = "cpu";
 337                         compatible = "arm,arm926ej-s";
 338                         reg = <0x0>;
 339                 };
 340         };
 341
 342 Example 4 (ARM Cortex-A57 64-bit system):
 343
 344 cpus {
 345         #size-cells = <0>;
 346         #address-cells = <2>;
 347
 348         cpu@0 {
 349                 device_type = "cpu";
 350                 compatible = "arm,cortex-a57";
 351                 reg = <0x0 0x0>;
 352                 enable-method = "spin-table";
 353                 cpu-release-addr = <0 0x20000000>;
 354         };
 355
 356         cpu@1 {
 357                 device_type = "cpu";
 358                 compatible = "arm,cortex-a57";
 359                 reg = <0x0 0x1>;
 360                 enable-method = "spin-table";
 361                 cpu-release-addr = <0 0x20000000>;
 362         };
 363
 364         cpu@100 {
 365                 device_type = "cpu";
 366                 compatible = "arm,cortex-a57";
 367                 reg = <0x0 0x100>;
 368                 enable-method = "spin-table";
 369                 cpu-release-addr = <0 0x20000000>;
 370         };
 371
 372         cpu@101 {
 373                 device_type = "cpu";
 374                 compatible = "arm,cortex-a57";
 375                 reg = <0x0 0x101>;
 376                 enable-method = "spin-table";
 377                 cpu-release-addr = <0 0x20000000>;
 378         };
 379
 380         cpu@10000 {
 381                 device_type = "cpu";
 382                 compatible = "arm,cortex-a57";
 383                 reg = <0x0 0x10000>;
 384                 enable-method = "spin-table";
 385                 cpu-release-addr = <0 0x20000000>;
 386         };
 387
 388         cpu@10001 {
 389                 device_type = "cpu";
 390                 compatible = "arm,cortex-a57";
 391                 reg = <0x0 0x10001>;
 392                 enable-method = "spin-table";
 393                 cpu-release-addr = <0 0x20000000>;
 394         };
 395
 396         cpu@10100 {
 397                 device_type = "cpu";
 398                 compatible = "arm,cortex-a57";
 399                 reg = <0x0 0x10100>;
 400                 enable-method = "spin-table";
 401                 cpu-release-addr = <0 0x20000000>;
 402         };
 403
 404         cpu@10101 {
 405                 device_type = "cpu";
 406                 compatible = "arm,cortex-a57";
 407                 reg = <0x0 0x10101>;
 408                 enable-method = "spin-table";
 409                 cpu-release-addr = <0 0x20000000>;
 410         };
 411
 412         cpu@100000000 {
 413                 device_type = "cpu";
 414                 compatible = "arm,cortex-a57";
 415                 reg = <0x1 0x0>;
 416                 enable-method = "spin-table";
 417                 cpu-release-addr = <0 0x20000000>;
 418         };
 419
 420         cpu@100000001 {
 421                 device_type = "cpu";
 422                 compatible = "arm,cortex-a57";
 423                 reg = <0x1 0x1>;
 424                 enable-method = "spin-table";
 425                 cpu-release-addr = <0 0x20000000>;
 426         };
 427
 428         cpu@100000100 {
 429                 device_type = "cpu";
 430                 compatible = "arm,cortex-a57";
 431                 reg = <0x1 0x100>;
 432                 enable-method = "spin-table";
 433                 cpu-release-addr = <0 0x20000000>;
 434         };
 435
 436         cpu@100000101 {
 437                 device_type = "cpu";
 438                 compatible = "arm,cortex-a57";
 439                 reg = <0x1 0x101>;
 440                 enable-method = "spin-table";
 441                 cpu-release-addr = <0 0x20000000>;
 442         };
 443
 444         cpu@100010000 {
 445                 device_type = "cpu";
 446                 compatible = "arm,cortex-a57";
 447                 reg = <0x1 0x10000>;
 448                 enable-method = "spin-table";
 449                 cpu-release-addr = <0 0x20000000>;
 450         };
 451
 452         cpu@100010001 {
 453                 device_type = "cpu";
 454                 compatible = "arm,cortex-a57";
 455                 reg = <0x1 0x10001>;
 456                 enable-method = "spin-table";
 457                 cpu-release-addr = <0 0x20000000>;
 458         };
 459
 460         cpu@100010100 {
 461                 device_type = "cpu";
 462                 compatible = "arm,cortex-a57";
 463                 reg = <0x1 0x10100>;
 464                 enable-method = "spin-table";
 465                 cpu-release-addr = <0 0x20000000>;
 466         };
 467
 468         cpu@100010101 {
 469                 device_type = "cpu";
 470                 compatible = "arm,cortex-a57";
 471                 reg = <0x1 0x10101>;
 472                 enable-method = "spin-table";
 473                 cpu-release-addr = <0 0x20000000>;
 474         };
 475 };
 476
 477 --
 478 [1] arm/msm/qcom,saw2.txt
 479 [2] arm/msm/qcom,kpss-acc.txt
 480 [3] ARM Linux kernel documentation - idle states bindings
 481     Documentation/devicetree/bindings/arm/idle-states.txt
 482 [4] ARM Linux kernel documentation - cpu capacity bindings
 483     Documentation/devicetree/bindings/arm/cpu-capacity.txt