3 Chipid required properties:
4 - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid"
5 - reg : Should contain registers location and length
7 PIT Timer required properties:
8 - compatible: Should be "atmel,at91sam9260-pit"
9 - reg: Should contain registers location and length
10 - interrupts: Should contain interrupt for the PIT which is the IRQ line
11 shared across all System Controller members.
13 PIT64B Timer required properties:
14 - compatible: Should be "microchip,sam9x60-pit64b"
15 - reg: Should contain registers location and length
16 - interrupts: Should contain interrupt for PIT64B timer
17 - clocks: Should contain the available clock sources for PIT64B timer.
19 System Timer (ST) required properties:
20 - compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"
21 - reg: Should contain registers location and length
22 - interrupts: Should contain interrupt for the ST which is the IRQ line
23 shared across all System Controller members.
24 - clocks: phandle to input clock.
26 - watchdog: compatible should be "atmel,at91rm9200-wdt"
28 RAMC SDRAM/DDR Controller required properties:
29 - compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
30 "atmel,at91sam9260-sdramc",
31 "atmel,at91sam9g45-ddramc",
32 "atmel,sama5d3-ddramc",
33 "microchip,sam9x60-ddramc",
34 "microchip,sama7g5-uddrc"
35 - reg: Should contain registers location and length
39 ramc0: ramc@ffffe800 {
40 compatible = "atmel,at91sam9g45-ddramc";
41 reg = <0xffffe800 0x200>;
44 RAMC PHY Controller required properties:
45 - compatible: Should be "microchip,sama7g5-ddr3phy", "syscon"
46 - reg: Should contain registers location and length
50 ddr3phy: ddr3phy@e3804000 {
51 compatible = "microchip,sama7g5-ddr3phy", "syscon";
52 reg = <0xe3804000 0x1000>;
55 SHDWC Shutdown Controller
58 - compatible: Should be "atmel,<chip>-shdwc".
59 <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
60 - reg: Should contain registers location and length
61 - clocks: phandle to input clock.
64 - atmel,wakeup-mode: String, operation mode of the wakeup mode.
65 Supported values are: "none", "high", "low", "any".
66 - atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
68 optional at91sam9260 properties:
69 - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
71 optional at91sam9rl properties:
72 - atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
73 - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
75 optional at91sam9x5 properties:
76 - atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
81 compatible = "atmel,at91sam9260-shdwc";
82 reg = <0xfffffd10 0x10>;
86 SHDWC SAMA5D2-Compatible Shutdown Controller
91 - compatible: should be "atmel,sama5d2-shdwc", "microchip,sam9x60-shdwc" or
92 "microchip,sama7g5-shdwc"
93 - reg: should contain registers location and length
94 - clocks: phandle to input clock.
95 - #address-cells: should be one. The cell is the wake-up input index.
96 - #size-cells: should be zero.
100 - debounce-delay-us: minimum wake-up inputs debouncer period in
101 microseconds. It's usually a board-related property.
102 - atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up.
104 optional microchip,sam9x60-shdwc or microchip,sama7g5-shdwc properties:
105 - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
107 The node contains child nodes for each wake-up input that the platform uses.
111 Wake-up input nodes are usually described in the "board" part of the Device
112 Tree. Note also that input 0 is linked to the wake-up pin and is frequently
116 - reg: should contain the wake-up input index [0 - 15].
119 - atmel,wakeup-active-high: boolean, the corresponding wake-up input described
120 by the child, forces the wake-up of the core power supply on a high level.
121 The default is to be active low.
127 compatible = "atmel,sama5d2-shdwc";
128 reg = <0xf8048010 0x10>;
130 #address-cells = <1>;
132 atmel,wakeup-rtc-timer;
137 debounce-delay-us = <976>;
145 atmel,wakeup-active-high;
149 Special Function Registers (SFR)
151 Special Function Registers (SFR) manage specific aspects of the integrated
152 memory, bridge implementations, processor and other functionality not controlled
156 - compatible: Should be "atmel,<chip>-sfr", "syscon" or
157 "atmel,<chip>-sfrbu", "syscon"
158 <chip> can be "sama5d3", "sama5d4" or "sama5d2".
159 It also can be "microchip,sam9x60-sfr", "syscon".
160 - reg: Should contain registers location and length
163 compatible = "atmel,sama5d3-sfr", "syscon";
164 reg = <0xf0038000 0x60>;
167 Security Module (SECUMOD)
169 The Security Module macrocell provides all necessary secure functions to avoid
170 voltage, temperature, frequency and mechanical attacks on the chip. It also
171 embeds secure memories that can be scrambled.
173 The Security Module also offers the PIOBU pins which can be used as GPIO pins.
174 Note that they maintain their voltage during Backup/Self-refresh.
177 - compatible: Should be "atmel,<chip>-secumod", "syscon".
178 <chip> can be "sama5d2".
179 - reg: Should contain registers location and length
180 - gpio-controller: Marks the port as GPIO controller.
181 - #gpio-cells: There are 2. The pin number is the
182 first, the second represents additional
183 parameters such as GPIO_ACTIVE_HIGH/LOW.
187 compatible = "atmel,sama5d2-secumod", "syscon";
188 reg = <0xfc040000 0x100>;