1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm CoreSight System Trace MacroCell
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight components are compliant with the ARM CoreSight architecture
17 specification and can be connected in various topologies to suit a particular
18 SoCs tracing needs. These trace components can generally be classified as
19 sinks, links and sources. Trace data produced by one or more sources flows
20 through the intermediate links connecting the source to the currently selected
23 The STM is a trace source that is integrated into a CoreSight system, designed
24 primarily for high-bandwidth trace of instrumentation embedded into software.
25 This instrumentation is made up of memory-mapped writes to the STM Advanced
26 eXtensible Interface (AXI) slave, which carry information about the behavior
33 const: arm,coresight-stm
38 - $ref: /schemas/arm/primecell.yaml#
43 - const: arm,coresight-stm
44 - const: arm,primecell
52 - const: stm-stimulus-base
68 $ref: /schemas/graph.yaml#/properties/ports
69 additionalProperties: false
73 description: Output connection to the CoreSight Trace bus.
74 $ref: /schemas/graph.yaml#/properties/port
84 unevaluatedProperties: false
89 compatible = "arm,coresight-stm", "arm,primecell";
90 reg = <0x20100000 0x1000>,
91 <0x28000000 0x180000>;
92 reg-names = "stm-base", "stm-stimulus-base";
94 clocks = <&soc_smc50mhz>;
95 clock-names = "apb_pclk";
98 stm_out_port: endpoint {
99 remote-endpoint = <&main_funnel_in_port2>;