1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm CoreSight Embedded Trace MacroCell
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight components are compliant with the ARM CoreSight architecture
17 specification and can be connected in various topologies to suit a particular
18 SoCs tracing needs. These trace components can generally be classified as
19 sinks, links and sources. Trace data produced by one or more sources flows
20 through the intermediate links connecting the source to the currently selected
23 The Embedded Trace Macrocell (ETM) is a real-time trace module providing
24 instruction and data tracing of a processor.
33 - arm,coresight-etm4x-sysreg
43 const: arm,coresight-etm4x-sysreg
45 $ref: /schemas/arm/primecell.yaml#
53 Embedded Trace Macrocell with memory mapped access.
58 - const: arm,primecell
60 Embedded Trace Macrocell (version 4.x), with system register access only
61 const: arm,coresight-etm4x-sysreg
79 arm,coresight-loses-context-with-cpu:
82 Indicates that the hardware will lose register context on CPU power down
83 (e.g. CPUIdle). An example of where this may be needed are systems which
84 contain a coresight component and CPU in the same power domain. When the
85 CPU powers down the coresight component also powers down and loses its
91 Must be present if the system accesses ETM/PTM management registers via
97 Indicates that an implementation can skip powering up the trace unit.
98 TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems
99 since ETMs are in the same power domain as their CPU cores. This property
100 is required to identify such systems with hardware errata where the CPU
101 watchdog counter is stopped when TRCPDCR.PU is set.
105 phandle to the cpu this ETM is bound to.
106 $ref: /schemas/types.yaml#/definitions/phandle
109 $ref: /schemas/graph.yaml#/properties/ports
110 additionalProperties: false
114 description: Output connection from the ETM to CoreSight Trace bus.
115 $ref: /schemas/graph.yaml#/properties/port
124 unevaluatedProperties: false
129 compatible = "arm,coresight-etm3x", "arm,primecell";
130 reg = <0x2201c000 0x1000>;
133 clocks = <&oscclk6a>;
134 clock-names = "apb_pclk";
137 ptm0_out_port: endpoint {
138 remote-endpoint = <&funnel_in_port0>;
145 compatible = "arm,coresight-etm3x", "arm,primecell";
146 reg = <0x2201d000 0x1000>;
149 clocks = <&oscclk6a>;
150 clock-names = "apb_pclk";
153 ptm1_out_port: endpoint {
154 remote-endpoint = <&funnel_in_port1>;