1 What: /sys/bus/cxl/flush
4 Contact: linux-cxl@vger.kernel.org
6 (WO) If userspace manually unbinds a port the kernel schedules
7 all descendant memdevs for unbind. Writing '1' to this attribute
11 What: /sys/bus/cxl/devices/memX/firmware_version
14 Contact: linux-cxl@vger.kernel.org
16 (RO) "FW Revision" string as reported by the Identify
17 Memory Device Output Payload in the CXL-2.0
21 What: /sys/bus/cxl/devices/memX/ram/size
24 Contact: linux-cxl@vger.kernel.org
26 (RO) "Volatile Only Capacity" as bytes. Represents the
27 identically named field in the Identify Memory Device Output
28 Payload in the CXL-2.0 specification.
31 What: /sys/bus/cxl/devices/memX/pmem/size
34 Contact: linux-cxl@vger.kernel.org
36 (RO) "Persistent Only Capacity" as bytes. Represents the
37 identically named field in the Identify Memory Device Output
38 Payload in the CXL-2.0 specification.
41 What: /sys/bus/cxl/devices/memX/serial
44 Contact: linux-cxl@vger.kernel.org
46 (RO) 64-bit serial number per the PCIe Device Serial Number
47 capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2
48 Memory Device PCIe Capabilities and Extended Capabilities.
51 What: /sys/bus/cxl/devices/memX/numa_node
54 Contact: linux-cxl@vger.kernel.org
56 (RO) If NUMA is enabled and the platform has affinitized the
57 host PCI device for this memory device, emit the CPU node
58 affinity for this device.
61 What: /sys/bus/cxl/devices/*/devtype
64 Contact: linux-cxl@vger.kernel.org
66 (RO) CXL device objects export the devtype attribute which
67 mirrors the same value communicated in the DEVTYPE environment
68 variable for uevents for devices on the "cxl" bus.
71 What: /sys/bus/cxl/devices/*/modalias
74 Contact: linux-cxl@vger.kernel.org
76 (RO) CXL device objects export the modalias attribute which
77 mirrors the same value communicated in the MODALIAS environment
78 variable for uevents for devices on the "cxl" bus.
81 What: /sys/bus/cxl/devices/portX/uport
84 Contact: linux-cxl@vger.kernel.org
86 (RO) CXL port objects are enumerated from either a platform
87 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
88 port with CXL component registers. The 'uport' symlink connects
89 the CXL portX object to the device that published the CXL port
93 What: /sys/bus/cxl/devices/portX/dportY
96 Contact: linux-cxl@vger.kernel.org
98 (RO) CXL port objects are enumerated from either a platform
99 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
100 port with CXL component registers. The 'dportY' symlink
101 identifies one or more downstream ports that the upstream port
102 may target in its decode of CXL memory resources. The 'Y'
103 integer reflects the hardware port unique-id used in the
104 hardware decoder target list.
107 What: /sys/bus/cxl/devices/decoderX.Y
110 Contact: linux-cxl@vger.kernel.org
112 (RO) CXL decoder objects are enumerated from either a platform
113 firmware description, or a CXL HDM decoder register set in a
114 PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
115 Capability Structure). The 'X' in decoderX.Y represents the
116 cxl_port container of this decoder, and 'Y' represents the
117 instance id of a given decoder resource.
120 What: /sys/bus/cxl/devices/decoderX.Y/{start,size}
123 Contact: linux-cxl@vger.kernel.org
125 (RO) The 'start' and 'size' attributes together convey the
126 physical address base and number of bytes mapped in the
127 decoder's decode window. For decoders of devtype
128 "cxl_decoder_root" the address range is fixed. For decoders of
129 devtype "cxl_decoder_switch" the address is bounded by the
130 decode range of the cxl_port ancestor of the decoder's cxl_port,
131 and dynamically updates based on the active memory regions in
135 What: /sys/bus/cxl/devices/decoderX.Y/locked
138 Contact: linux-cxl@vger.kernel.org
140 (RO) CXL HDM decoders have the capability to lock the
141 configuration until the next device reset. For decoders of
142 devtype "cxl_decoder_root" there is no standard facility to
143 unlock them. For decoders of devtype "cxl_decoder_switch" a
144 secondary bus reset, of the PCIe bridge that provides the bus
145 for this decoders uport, unlocks / resets the decoder.
148 What: /sys/bus/cxl/devices/decoderX.Y/target_list
151 Contact: linux-cxl@vger.kernel.org
153 (RO) Display a comma separated list of the current decoder
154 target configuration. The list is ordered by the current
155 configured interleave order of the decoder's dport instances.
156 Each entry in the list is a dport id.
159 What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}
162 Contact: linux-cxl@vger.kernel.org
164 (RO) When a CXL decoder is of devtype "cxl_decoder_root", it
165 represents a fixed memory window identified by platform
166 firmware. A fixed window may only support a subset of memory
167 types. The 'cap_*' attributes indicate whether persistent
168 memory, volatile memory, accelerator memory, and / or expander
169 memory may be mapped behind this decoder's memory window.
172 What: /sys/bus/cxl/devices/decoderX.Y/target_type
175 Contact: linux-cxl@vger.kernel.org
177 (RO) When a CXL decoder is of devtype "cxl_decoder_switch", it
178 can optionally decode either accelerator memory (type-2) or
179 expander memory (type-3). The 'target_type' attribute indicates
180 the current setting which may dynamically change based on what
181 memory regions are activated in this decode hierarchy.
184 What: /sys/bus/cxl/devices/endpointX/CDAT
187 Contact: linux-cxl@vger.kernel.org
189 (RO) If this sysfs entry is not present no DOE mailbox was
190 found to support CDAT data. If it is present and the length of
191 the data is 0 reading the CDAT data failed. Otherwise the CDAT
195 What: /sys/bus/cxl/devices/decoderX.Y/mode
198 Contact: linux-cxl@vger.kernel.org
200 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
201 translates from a host physical address range, to a device local
202 address range. Device-local address ranges are further split
203 into a 'ram' (volatile memory) range and 'pmem' (persistent
204 memory) range. The 'mode' attribute emits one of 'ram', 'pmem',
205 'mixed', or 'none'. The 'mixed' indication is for error cases
206 when a decoder straddles the volatile/persistent partition
207 boundary, and 'none' indicates the decoder is not actively
208 decoding, or no DPA allocation policy has been set.
210 'mode' can be written, when the decoder is in the 'disabled'
211 state, with either 'ram' or 'pmem' to set the boundaries for the
215 What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource
218 Contact: linux-cxl@vger.kernel.org
220 (RO) When a CXL decoder is of devtype "cxl_decoder_endpoint",
221 and its 'dpa_size' attribute is non-zero, this attribute
222 indicates the device physical address (DPA) base address of the
226 What: /sys/bus/cxl/devices/decoderX.Y/dpa_size
229 Contact: linux-cxl@vger.kernel.org
231 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
232 translates from a host physical address range, to a device local
233 address range. The range, base address plus length in bytes, of
234 DPA allocated to this decoder is conveyed in these 2 attributes.
235 Allocations can be mutated as long as the decoder is in the
236 disabled state. A write to 'dpa_size' releases the previous DPA
237 allocation and then attempts to allocate from the free capacity
238 in the device partition referred to by 'decoderX.Y/mode'.
239 Allocate and free requests can only be performed on the highest
240 instance number disabled decoder with non-zero size. I.e.
241 allocations are enforced to occur in increasing 'decoderX.Y/id'
242 order and frees are enforced to occur in decreasing
243 'decoderX.Y/id' order.
246 What: /sys/bus/cxl/devices/decoderX.Y/interleave_ways
249 Contact: linux-cxl@vger.kernel.org
251 (RO) The number of targets across which this decoder's host
252 physical address (HPA) memory range is interleaved. The device
253 maps every Nth block of HPA (of size ==
254 'interleave_granularity') to consecutive DPA addresses. The
255 decoder's position in the interleave is determined by the
256 device's (endpoint or switch) switch ancestry. For root
257 decoders their interleave is specified by platform firmware and
258 they only specify a downstream target order for host bridges.
261 What: /sys/bus/cxl/devices/decoderX.Y/interleave_granularity
264 Contact: linux-cxl@vger.kernel.org
266 (RO) The number of consecutive bytes of host physical address
267 space this decoder claims at address N before the decode rotates
268 to the next target in the interleave at address N +
269 interleave_granularity (assuming N is aligned to
270 interleave_granularity).
273 What: /sys/bus/cxl/devices/decoderX.Y/create_pmem_region
276 Contact: linux-cxl@vger.kernel.org
278 (RW) Write a string in the form 'regionZ' to start the process
279 of defining a new persistent memory region (interleave-set)
280 within the decode range bounded by root decoder 'decoderX.Y'.
281 The value written must match the current value returned from
282 reading this attribute. An atomic compare exchange operation is
283 done on write to assign the requested id to a region and
284 allocate the region-id for the next creation attempt. EBUSY is
285 returned if the region name written does not match the current
289 What: /sys/bus/cxl/devices/decoderX.Y/delete_region
292 Contact: linux-cxl@vger.kernel.org
294 (WO) Write a string in the form 'regionZ' to delete that region,
295 provided it is currently idle / not bound to a driver.
298 What: /sys/bus/cxl/devices/regionZ/uuid
301 Contact: linux-cxl@vger.kernel.org
303 (RW) Write a unique identifier for the region. This field must
304 be set for persistent regions and it must not conflict with the
305 UUID of another region.
308 What: /sys/bus/cxl/devices/regionZ/interleave_granularity
311 Contact: linux-cxl@vger.kernel.org
313 (RW) Set the number of consecutive bytes each device in the
314 interleave set will claim. The possible interleave granularity
315 values are determined by the CXL spec and the participating
319 What: /sys/bus/cxl/devices/regionZ/interleave_ways
322 Contact: linux-cxl@vger.kernel.org
324 (RW) Configures the number of devices participating in the
325 region is set by writing this value. Each device will provide
326 1/interleave_ways of storage for the region.
329 What: /sys/bus/cxl/devices/regionZ/size
332 Contact: linux-cxl@vger.kernel.org
334 (RW) System physical address space to be consumed by the region.
335 When written trigger the driver to allocate space out of the
336 parent root decoder's address space. When read the size of the
337 address space is reported and should match the span of the
338 region's resource attribute. Size shall be set after the
339 interleave configuration parameters. Once set it cannot be
340 changed, only freed by writing 0. The kernel makes no guarantees
341 that data is maintained over an address space freeing event, and
342 there is no guarantee that a free followed by an allocate
343 results in the same address being allocated.
346 What: /sys/bus/cxl/devices/regionZ/resource
349 Contact: linux-cxl@vger.kernel.org
351 (RO) A region is a contiguous partition of a CXL root decoder
352 address space. Region capacity is allocated by writing to the
353 size attribute, the resulting physical address space determined
354 by the driver is reflected here. It is therefore not useful to
355 read this before writing a value to the size attribute.
358 What: /sys/bus/cxl/devices/regionZ/target[0..N]
361 Contact: linux-cxl@vger.kernel.org
363 (RW) Write an endpoint decoder object name to 'targetX' where X
364 is the intended position of the endpoint device in the region
365 interleave and N is the 'interleave_ways' setting for the
366 region. ENXIO is returned if the write results in an impossible
367 to map decode scenario, like the endpoint is unreachable at that
368 position relative to the root decoder interleave. EBUSY is
369 returned if the position in the region is already occupied, or
370 if the region is not in a state to accept interleave
371 configuration changes. EINVAL is returned if the object name is
372 not an endpoint decoder. Once all positions have been
373 successfully written a final validation for decode conflicts is
374 performed before activating the region.
377 What: /sys/bus/cxl/devices/regionZ/commit
380 Contact: linux-cxl@vger.kernel.org
382 (RW) Write a boolean 'true' string value to this attribute to
383 trigger the region to transition from the software programmed
384 state to the actively decoding in hardware state. The commit
385 operation in addition to validating that the region is in proper
386 configured state, validates that the decoders are being
387 committed in spec mandated order (last committed decoder id +
388 1), and checks that the hardware accepts the commit request.
389 Reading this value indicates whether the region is committed or