1 What: /sys/bus/cxl/flush
4 Contact: linux-cxl@vger.kernel.org
6 (WO) If userspace manually unbinds a port the kernel schedules
7 all descendant memdevs for unbind. Writing '1' to this attribute
10 What: /sys/bus/cxl/devices/memX/firmware_version
13 Contact: linux-cxl@vger.kernel.org
15 (RO) "FW Revision" string as reported by the Identify
16 Memory Device Output Payload in the CXL-2.0
19 What: /sys/bus/cxl/devices/memX/ram/size
22 Contact: linux-cxl@vger.kernel.org
24 (RO) "Volatile Only Capacity" as bytes. Represents the
25 identically named field in the Identify Memory Device Output
26 Payload in the CXL-2.0 specification.
28 What: /sys/bus/cxl/devices/memX/pmem/size
31 Contact: linux-cxl@vger.kernel.org
33 (RO) "Persistent Only Capacity" as bytes. Represents the
34 identically named field in the Identify Memory Device Output
35 Payload in the CXL-2.0 specification.
37 What: /sys/bus/cxl/devices/memX/serial
40 Contact: linux-cxl@vger.kernel.org
42 (RO) 64-bit serial number per the PCIe Device Serial Number
43 capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2
44 Memory Device PCIe Capabilities and Extended Capabilities.
46 What: /sys/bus/cxl/devices/memX/numa_node
49 Contact: linux-cxl@vger.kernel.org
51 (RO) If NUMA is enabled and the platform has affinitized the
52 host PCI device for this memory device, emit the CPU node
53 affinity for this device.
55 What: /sys/bus/cxl/devices/*/devtype
58 Contact: linux-cxl@vger.kernel.org
60 CXL device objects export the devtype attribute which mirrors
61 the same value communicated in the DEVTYPE environment variable
62 for uevents for devices on the "cxl" bus.
64 What: /sys/bus/cxl/devices/*/modalias
67 Contact: linux-cxl@vger.kernel.org
69 CXL device objects export the modalias attribute which mirrors
70 the same value communicated in the MODALIAS environment variable
71 for uevents for devices on the "cxl" bus.
73 What: /sys/bus/cxl/devices/portX/uport
76 Contact: linux-cxl@vger.kernel.org
78 CXL port objects are enumerated from either a platform firmware
79 device (ACPI0017 and ACPI0016) or PCIe switch upstream port with
80 CXL component registers. The 'uport' symlink connects the CXL
81 portX object to the device that published the CXL port
84 What: /sys/bus/cxl/devices/portX/dportY
87 Contact: linux-cxl@vger.kernel.org
89 CXL port objects are enumerated from either a platform firmware
90 device (ACPI0017 and ACPI0016) or PCIe switch upstream port with
91 CXL component registers. The 'dportY' symlink identifies one or
92 more downstream ports that the upstream port may target in its
93 decode of CXL memory resources. The 'Y' integer reflects the
94 hardware port unique-id used in the hardware decoder target
97 What: /sys/bus/cxl/devices/decoderX.Y
100 Contact: linux-cxl@vger.kernel.org
102 CXL decoder objects are enumerated from either a platform
103 firmware description, or a CXL HDM decoder register set in a
104 PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
105 Capability Structure). The 'X' in decoderX.Y represents the
106 cxl_port container of this decoder, and 'Y' represents the
107 instance id of a given decoder resource.
109 What: /sys/bus/cxl/devices/decoderX.Y/{start,size}
112 Contact: linux-cxl@vger.kernel.org
114 The 'start' and 'size' attributes together convey the physical
115 address base and number of bytes mapped in the decoder's decode
116 window. For decoders of devtype "cxl_decoder_root" the address
117 range is fixed. For decoders of devtype "cxl_decoder_switch" the
118 address is bounded by the decode range of the cxl_port ancestor
119 of the decoder's cxl_port, and dynamically updates based on the
120 active memory regions in that address space.
122 What: /sys/bus/cxl/devices/decoderX.Y/locked
125 Contact: linux-cxl@vger.kernel.org
127 CXL HDM decoders have the capability to lock the configuration
128 until the next device reset. For decoders of devtype
129 "cxl_decoder_root" there is no standard facility to unlock them.
130 For decoders of devtype "cxl_decoder_switch" a secondary bus
131 reset, of the PCIe bridge that provides the bus for this
132 decoders uport, unlocks / resets the decoder.
134 What: /sys/bus/cxl/devices/decoderX.Y/target_list
137 Contact: linux-cxl@vger.kernel.org
139 Display a comma separated list of the current decoder target
140 configuration. The list is ordered by the current configured
141 interleave order of the decoder's dport instances. Each entry in
142 the list is a dport id.
144 What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}
147 Contact: linux-cxl@vger.kernel.org
149 When a CXL decoder is of devtype "cxl_decoder_root", it
150 represents a fixed memory window identified by platform
151 firmware. A fixed window may only support a subset of memory
152 types. The 'cap_*' attributes indicate whether persistent
153 memory, volatile memory, accelerator memory, and / or expander
154 memory may be mapped behind this decoder's memory window.
156 What: /sys/bus/cxl/devices/decoderX.Y/target_type
159 Contact: linux-cxl@vger.kernel.org
161 When a CXL decoder is of devtype "cxl_decoder_switch", it can
162 optionally decode either accelerator memory (type-2) or expander
163 memory (type-3). The 'target_type' attribute indicates the
164 current setting which may dynamically change based on what
165 memory regions are activated in this decode hierarchy.