1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * GE SBC610 board support
5 * Author: Martyn Welch <martyn.welch@ge.com>
7 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
9 * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
10 * Copyright 2006 Freescale Semiconductor Inc.
12 * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
15 #include <linux/stddef.h>
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/kdev_t.h>
19 #include <linux/delay.h>
20 #include <linux/seq_file.h>
22 #include <linux/of_address.h>
25 #include <asm/machdep.h>
26 #include <asm/pci-bridge.h>
27 #include <mm/mmu_decl.h>
31 #include <asm/nvram.h>
33 #include <sysdev/fsl_pci.h>
34 #include <sysdev/fsl_soc.h>
35 #include <sysdev/ge/ge_pic.h>
42 #define DBG (fmt...) do { printk(KERN_ERR "SBC610: " fmt); } while (0)
44 #define DBG (fmt...) do { } while (0)
47 void __iomem *sbc610_regs;
49 static void __init gef_sbc610_init_irq(void)
51 struct device_node *cascade_node = NULL;
56 * There is a simple interrupt handler in the main FPGA, this needs
57 * to be cascaded into the MPIC
59 cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic");
61 printk(KERN_WARNING "SBC610: No FPGA PIC\n");
65 gef_pic_init(cascade_node);
66 of_node_put(cascade_node);
69 static void __init gef_sbc610_setup_arch(void)
71 struct device_node *regs;
73 printk(KERN_INFO "GE Intelligent Platforms SBC610 6U VPX SBC\n");
79 fsl_pci_assign_primary();
81 /* Remap basic board registers */
82 regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs");
84 sbc610_regs = of_iomap(regs, 0);
85 if (sbc610_regs == NULL)
86 printk(KERN_WARNING "Unable to map board registers\n");
90 #if defined(CONFIG_MMIO_NVRAM)
95 /* Return the PCB revision */
96 static unsigned int gef_sbc610_get_pcb_rev(void)
100 reg = ioread32(sbc610_regs);
101 return (reg >> 8) & 0xff;
104 /* Return the board (software) revision */
105 static unsigned int gef_sbc610_get_board_rev(void)
109 reg = ioread32(sbc610_regs);
110 return (reg >> 16) & 0xff;
113 /* Return the FPGA revision */
114 static unsigned int gef_sbc610_get_fpga_rev(void)
118 reg = ioread32(sbc610_regs);
119 return (reg >> 24) & 0xf;
122 static void gef_sbc610_show_cpuinfo(struct seq_file *m)
124 uint svid = mfspr(SPRN_SVR);
126 seq_printf(m, "Vendor\t\t: GE Intelligent Platforms\n");
128 seq_printf(m, "Revision\t: %u%c\n", gef_sbc610_get_pcb_rev(),
129 ('A' + gef_sbc610_get_board_rev() - 1));
130 seq_printf(m, "FPGA Revision\t: %u\n", gef_sbc610_get_fpga_rev());
132 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
135 static void gef_sbc610_nec_fixup(struct pci_dev *pdev)
139 /* Do not do the fixup on other platforms! */
140 if (!machine_is(gef_sbc610))
143 printk(KERN_INFO "Running NEC uPD720101 Fixup\n");
145 /* Ensure ports 1, 2, 3, 4 & 5 are enabled */
146 pci_read_config_dword(pdev, 0xe0, &val);
147 pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x5);
149 /* System clock is 48-MHz Oscillator and EHCI Enabled. */
150 pci_write_config_dword(pdev, 0xe4, 1 << 5);
152 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
153 gef_sbc610_nec_fixup);
155 machine_arch_initcall(gef_sbc610, mpc86xx_common_publish_devices);
157 define_machine(gef_sbc610) {
159 .compatible = "gef,sbc610",
160 .setup_arch = gef_sbc610_setup_arch,
161 .init_IRQ = gef_sbc610_init_irq,
162 .show_cpuinfo = gef_sbc610_show_cpuinfo,
163 .get_irq = mpic_get_irq,
164 .time_init = mpc86xx_time_init,
165 .progress = udbg_progress,
167 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,