1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Enter and leave deep sleep state on MPC83xx
5 * Copyright (c) 2006-2008 Freescale Semiconductor, Inc.
6 * Author: Scott Wood <scottwood@freescale.com>
10 #include <asm/ppc_asm.h>
12 #include <asm/asm-offsets.h>
14 #define SS_MEMSAVE 0x00 /* First 8 bytes of RAM */
15 #define SS_HID 0x08 /* 3 HIDs */
16 #define SS_IABR 0x14 /* 2 IABRs */
18 #define SS_DABR 0x20 /* 2 DABRs */
21 #define SS_SR 0x30 /* 16 segment registers */
26 #define SS_SPRG 0x80 /* 8 SPRGs */
27 #define SS_DBAT 0xa0 /* 8 DBATs */
28 #define SS_IBAT 0xe0 /* 8 IBATs */
31 #define SS_GPREG 0x12c /* r12-r31 */
32 #define STATE_SAVE_SIZE 0x17c
37 mpc83xx_sleep_save_area:
38 .space STATE_SAVE_SIZE
45 /* r3 = physical address of IMMR */
46 _GLOBAL(mpc83xx_enter_deep_sleep)
48 stw r3, immrbase@l(r4)
50 /* The first 2 words of memory are used to communicate with the
51 * bootloader, to tell it how to resume.
53 * The first word is the magic number 0xf5153ae5, and the second
54 * is the pointer to mpc83xx_deep_resume.
56 * The original content of these two words is saved in SS_MEMSAVE.
59 lis r3, mpc83xx_sleep_save_area@h
60 ori r3, r3, mpc83xx_sleep_save_area@l
66 stw r5, SS_MEMSAVE+0(r3)
67 stw r6, SS_MEMSAVE+4(r3)
100 stw r7, SS_SPRG+12(r3)
108 stw r4, SS_SPRG+16(r3)
109 stw r5, SS_SPRG+20(r3)
110 stw r6, SS_SPRG+24(r3)
111 stw r7, SS_SPRG+28(r3)
113 mfspr r4, SPRN_DBAT0U
114 mfspr r5, SPRN_DBAT0L
115 mfspr r6, SPRN_DBAT1U
116 mfspr r7, SPRN_DBAT1L
118 stw r4, SS_DBAT+0x00(r3)
119 stw r5, SS_DBAT+0x04(r3)
120 stw r6, SS_DBAT+0x08(r3)
121 stw r7, SS_DBAT+0x0c(r3)
123 mfspr r4, SPRN_DBAT2U
124 mfspr r5, SPRN_DBAT2L
125 mfspr r6, SPRN_DBAT3U
126 mfspr r7, SPRN_DBAT3L
128 stw r4, SS_DBAT+0x10(r3)
129 stw r5, SS_DBAT+0x14(r3)
130 stw r6, SS_DBAT+0x18(r3)
131 stw r7, SS_DBAT+0x1c(r3)
133 mfspr r4, SPRN_DBAT4U
134 mfspr r5, SPRN_DBAT4L
135 mfspr r6, SPRN_DBAT5U
136 mfspr r7, SPRN_DBAT5L
138 stw r4, SS_DBAT+0x20(r3)
139 stw r5, SS_DBAT+0x24(r3)
140 stw r6, SS_DBAT+0x28(r3)
141 stw r7, SS_DBAT+0x2c(r3)
143 mfspr r4, SPRN_DBAT6U
144 mfspr r5, SPRN_DBAT6L
145 mfspr r6, SPRN_DBAT7U
146 mfspr r7, SPRN_DBAT7L
148 stw r4, SS_DBAT+0x30(r3)
149 stw r5, SS_DBAT+0x34(r3)
150 stw r6, SS_DBAT+0x38(r3)
151 stw r7, SS_DBAT+0x3c(r3)
153 mfspr r4, SPRN_IBAT0U
154 mfspr r5, SPRN_IBAT0L
155 mfspr r6, SPRN_IBAT1U
156 mfspr r7, SPRN_IBAT1L
158 stw r4, SS_IBAT+0x00(r3)
159 stw r5, SS_IBAT+0x04(r3)
160 stw r6, SS_IBAT+0x08(r3)
161 stw r7, SS_IBAT+0x0c(r3)
163 mfspr r4, SPRN_IBAT2U
164 mfspr r5, SPRN_IBAT2L
165 mfspr r6, SPRN_IBAT3U
166 mfspr r7, SPRN_IBAT3L
168 stw r4, SS_IBAT+0x10(r3)
169 stw r5, SS_IBAT+0x14(r3)
170 stw r6, SS_IBAT+0x18(r3)
171 stw r7, SS_IBAT+0x1c(r3)
173 mfspr r4, SPRN_IBAT4U
174 mfspr r5, SPRN_IBAT4L
175 mfspr r6, SPRN_IBAT5U
176 mfspr r7, SPRN_IBAT5L
178 stw r4, SS_IBAT+0x20(r3)
179 stw r5, SS_IBAT+0x24(r3)
180 stw r6, SS_IBAT+0x28(r3)
181 stw r7, SS_IBAT+0x2c(r3)
183 mfspr r4, SPRN_IBAT6U
184 mfspr r5, SPRN_IBAT6L
185 mfspr r6, SPRN_IBAT7U
186 mfspr r7, SPRN_IBAT7L
188 stw r4, SS_IBAT+0x30(r3)
189 stw r5, SS_IBAT+0x34(r3)
190 stw r6, SS_IBAT+0x38(r3)
191 stw r7, SS_IBAT+0x3c(r3)
212 stmw r12, SS_GPREG(r3)
222 /* Disable machine checks and critical exceptions */
224 rlwinm r4, r4, 0, ~MSR_CE
225 rlwinm r4, r4, 0, ~MSR_ME
229 #define TMP_VIRT_IMMR 0xf0000000
230 #define DEFAULT_IMMR_VALUE 0xff400000
231 #define IMMRBAR_BASE 0x0000
234 lwz r4, immrbase@l(r4)
236 /* Use DBAT0 to address the current IMMR space */
239 mtspr SPRN_DBAT0L, r4
240 lis r8, TMP_VIRT_IMMR@h
241 ori r4, r8, 0x001e /* 1 MByte accessible from Kernel Space only */
242 mtspr SPRN_DBAT0U, r4
245 /* Use DBAT1 to address the original IMMR space */
247 lis r4, DEFAULT_IMMR_VALUE@h
249 mtspr SPRN_DBAT1L, r4
250 lis r9, (TMP_VIRT_IMMR + 0x01000000)@h
251 ori r4, r9, 0x001e /* 1 MByte accessible from Kernel Space only */
252 mtspr SPRN_DBAT1U, r4
255 /* Use DBAT2 to address the beginning of RAM. This isn't done
256 * using the normal virtual mapping, because with page debugging
257 * enabled it will be read-only.
261 mtspr SPRN_DBAT2L, r4
263 ori r4, r4, 0x001e /* 1 MByte accessible from Kernel Space only */
264 mtspr SPRN_DBAT2U, r4
267 /* Flush the cache with our BAT, as there will be TLB misses
268 * otherwise if page debugging is enabled, and these misses
269 * will disturb the PLRU algorithm.
272 bl __flush_disable_L1
274 /* Keep the i-cache enabled, so the hack below for low-boot
285 lis r7, mpc83xx_deep_resume@h
286 ori r7, r7, mpc83xx_deep_resume@l
303 /* Rev 1 of the 8313 has problems with wakeup events that are
304 * pending during the transition to deep sleep state (such as if
305 * the PCI host sets the state to D3 and then D0 in rapid
306 * succession). This check shrinks the race window somewhat.
308 * See erratum PCI23, though the problem is not limited
314 bne- mpc83xx_deep_resume
316 /* Move IMMR back to the default location, following the
317 * procedure specified in the MPC8313 manual.
319 lwz r4, IMMRBAR_BASE(r8)
321 lis r4, DEFAULT_IMMR_VALUE@h
322 stw r4, IMMRBAR_BASE(r8)
326 lwz r4, IMMRBAR_BASE(r9)
330 /* Check the Reset Configuration Word to see whether flash needs
331 * to be mapped at a low address or a high address.
335 andis. r4, r4, 0x0400
345 rlwinm r5, r5, 0, ~(HID0_DOZE | HID0_NAP)
346 oris r5, r5, HID0_SLEEP@h
351 oris r5, r5, MSR_POW@h
353 /* Enable the flash mapping at the appropriate address. This
354 * mapping will override the RAM mapping if booting low, so there's
355 * no need to disable the latter. This must be done inside the same
356 * cache line as setting MSR_POW, so that no instruction fetches
357 * from RAM happen after the flash mapping is turned on.
375 rlwinm r4, r4, 0, ~(MSR_IR | MSR_DR)
383 lis r3, mpc83xx_sleep_save_area@h
384 ori r3, r3, mpc83xx_sleep_save_area@l
387 lwz r5, SS_MEMSAVE+0(r3)
388 lwz r6, SS_MEMSAVE+4(r3)
401 lwz r4, SS_IABR+0(r3)
402 lwz r5, SS_IABR+4(r3)
404 lwz r7, SS_DABR+0(r3)
405 lwz r8, SS_DABR+4(r3)
423 lwz r4, SS_DBAT+0x00(r3)
424 lwz r5, SS_DBAT+0x04(r3)
425 lwz r6, SS_DBAT+0x08(r3)
426 lwz r7, SS_DBAT+0x0c(r3)
428 mtspr SPRN_DBAT0U, r4
429 mtspr SPRN_DBAT0L, r5
430 mtspr SPRN_DBAT1U, r6
431 mtspr SPRN_DBAT1L, r7
433 lwz r4, SS_DBAT+0x10(r3)
434 lwz r5, SS_DBAT+0x14(r3)
435 lwz r6, SS_DBAT+0x18(r3)
436 lwz r7, SS_DBAT+0x1c(r3)
438 mtspr SPRN_DBAT2U, r4
439 mtspr SPRN_DBAT2L, r5
440 mtspr SPRN_DBAT3U, r6
441 mtspr SPRN_DBAT3L, r7
443 lwz r4, SS_DBAT+0x20(r3)
444 lwz r5, SS_DBAT+0x24(r3)
445 lwz r6, SS_DBAT+0x28(r3)
446 lwz r7, SS_DBAT+0x2c(r3)
448 mtspr SPRN_DBAT4U, r4
449 mtspr SPRN_DBAT4L, r5
450 mtspr SPRN_DBAT5U, r6
451 mtspr SPRN_DBAT5L, r7
453 lwz r4, SS_DBAT+0x30(r3)
454 lwz r5, SS_DBAT+0x34(r3)
455 lwz r6, SS_DBAT+0x38(r3)
456 lwz r7, SS_DBAT+0x3c(r3)
458 mtspr SPRN_DBAT6U, r4
459 mtspr SPRN_DBAT6L, r5
460 mtspr SPRN_DBAT7U, r6
461 mtspr SPRN_DBAT7L, r7
463 lwz r4, SS_IBAT+0x00(r3)
464 lwz r5, SS_IBAT+0x04(r3)
465 lwz r6, SS_IBAT+0x08(r3)
466 lwz r7, SS_IBAT+0x0c(r3)
468 mtspr SPRN_IBAT0U, r4
469 mtspr SPRN_IBAT0L, r5
470 mtspr SPRN_IBAT1U, r6
471 mtspr SPRN_IBAT1L, r7
473 lwz r4, SS_IBAT+0x10(r3)
474 lwz r5, SS_IBAT+0x14(r3)
475 lwz r6, SS_IBAT+0x18(r3)
476 lwz r7, SS_IBAT+0x1c(r3)
478 mtspr SPRN_IBAT2U, r4
479 mtspr SPRN_IBAT2L, r5
480 mtspr SPRN_IBAT3U, r6
481 mtspr SPRN_IBAT3L, r7
483 lwz r4, SS_IBAT+0x20(r3)
484 lwz r5, SS_IBAT+0x24(r3)
485 lwz r6, SS_IBAT+0x28(r3)
486 lwz r7, SS_IBAT+0x2c(r3)
488 mtspr SPRN_IBAT4U, r4
489 mtspr SPRN_IBAT4L, r5
490 mtspr SPRN_IBAT5U, r6
491 mtspr SPRN_IBAT5L, r7
493 lwz r4, SS_IBAT+0x30(r3)
494 lwz r5, SS_IBAT+0x34(r3)
495 lwz r6, SS_IBAT+0x38(r3)
496 lwz r7, SS_IBAT+0x3c(r3)
498 mtspr SPRN_IBAT6U, r4
499 mtspr SPRN_IBAT6L, r5
500 mtspr SPRN_IBAT7U, r6
501 mtspr SPRN_IBAT7L, r7
503 lwz r4, SS_SPRG+16(r3)
504 lwz r5, SS_SPRG+20(r3)
505 lwz r6, SS_SPRG+24(r3)
506 lwz r7, SS_SPRG+28(r3)
513 lwz r4, SS_SPRG+0(r3)
514 lwz r5, SS_SPRG+4(r3)
515 lwz r6, SS_SPRG+8(r3)
516 lwz r7, SS_SPRG+12(r3)
544 lmw r12, SS_GPREG(r3)
546 /* Kick decrementer */
551 _ASM_NOKPROBE_SYMBOL(mpc83xx_deep_resume)