X-Git-Url: https://jxself.org/git/?p=open-ath9k-htc-firmware.git;a=blobdiff_plain;f=target_firmware%2Fwlan%2Fif_owl.c;h=35b037c471a85667be03779cd3f724a8bcad0e1e;hp=5a06c599f7f2046ad32c383b6bdc35ecb7c4be70;hb=24b5105e0730aaeffb8a7b0b6b0d93eec6190b86;hpb=c3639cf95a219f4ebbea6b813a137c945f16c22b

diff --git a/target_firmware/wlan/if_owl.c b/target_firmware/wlan/if_owl.c
index 5a06c59..35b037c 100755
--- a/target_firmware/wlan/if_owl.c
+++ b/target_firmware/wlan/if_owl.c
@@ -57,6 +57,7 @@
 #include "if_athrate.h"
 #include "if_athvar.h"
 #include "ah_desc.h"
+#include "ah_internal.h"
 
 #define ath_tgt_free_skb  adf_nbuf_free
 
@@ -147,6 +148,8 @@ static void ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
 int ath_tgt_tx_add_to_aggr(struct ath_softc_tgt *sc,
 			   struct ath_buf *bf,int datatype,
 			   ath_atx_tid_t *tid, int is_burst);
+int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid,
+			 ath_tx_bufhead *bf_q);
 
 struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb)
 {
@@ -237,6 +240,7 @@ static void ath_dma_unmap(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
 static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
 {
 	struct ath_tx_desc *ds0, *ds = bf->bf_desc;
+	struct ath_hal *ah = sc->sc_ah;
 	a_uint8_t i;
 
 	ds0 = ds;
@@ -252,7 +256,7 @@ static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
 		} else
 			ds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, i+1);
 
-		ath_hal_filltxdesc(sc->sc_ah, ds
+		ah->ah_fillTxDesc(ds
 				   , bf->bf_dmamap_info.dma_segs[i].len
 				   , i == 0
 				   , i == (bf->bf_dmamap_info.nsegs - 1)
@@ -276,7 +280,7 @@ static void ath_tx_tgt_setds(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
 		break;
 	}
 
-	ah->ah_set11nTxDesc(ah, ds
+	ah->ah_set11nTxDesc(ds
 			      , bf->bf_pktlen
 			      , bf->bf_atype
 			      , 60
@@ -371,7 +375,6 @@ static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
     HAL_11N_RATE_SERIES series[4];
     a_int32_t i, flags;
     a_uint8_t rix, cix, rtsctsrate;
-    a_uint32_t ctsduration = 0;
     a_int32_t prot_mode = AH_FALSE;
 
     rt = sc->sc_currates;
@@ -386,7 +389,7 @@ static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
 	    cix = rt->info[sc->sc_protrix].controlRate;
 	    prot_mode = AH_TRUE;
     } else {
-	    if (ath_hal_htsupported(ah) && (!bf->bf_ismcast))
+	    if (ath_hal_getcapability(ah, HAL_CAP_HT) && (!bf->bf_ismcast))
 		    flags = HAL_TXDESC_RTSENA;
 
 	    for (i = 4; i--;) {
@@ -443,8 +446,8 @@ static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
     rtsctsrate = rt->info[cix].rateCode |
 	    (bf->bf_shpream ? rt->info[cix].shortPreamble : 0);
 
-    ah->ah_set11nRateScenario(ah, ds, 1,
-				rtsctsrate, ctsduration,
+    ah->ah_set11nRateScenario(ds, 1,
+				rtsctsrate,
 				series, 4,
 				flags);
 }
@@ -556,6 +559,8 @@ void ath_tx_status_update(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
 	if (txs == NULL)
 		return;
 
+	txs->txstatus[txs->cnt].ts_flags = 0;
+
 	txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
 	txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
 
@@ -650,6 +655,7 @@ void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
 {
 	struct ath_tx_buf *bf;
 	struct ath_tx_desc *ds;
+	struct ath_hal *ah = sc->sc_ah;
 	HAL_STATUS status;
 
 	for (;;) {
@@ -662,7 +668,7 @@ void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
 		bf = asf_tailq_first(&txq->axq_q);
 
 		ds = bf->bf_lastds;
-		status = ath_hal_txprocdesc(sc->sc_ah, ds);
+		status = ah->ah_procTxDesc(ah, ds);
 
 		if (status == HAL_EINPROGRESS) {
 			if (txqstate == OWL_TXQ_ACTIVE)
@@ -885,7 +891,7 @@ static void ath_tgt_txq_add_ucast(struct ath_softc_tgt *sc, struct ath_tx_buf *b
 
 	txq = bf->bf_txq;
 
-	status = ath_hal_txprocdesc(sc->sc_ah, bf->bf_lastds);
+	status = ah->ah_procTxDesc(ah, bf->bf_lastds);
 
 	ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
 
@@ -894,7 +900,7 @@ static void ath_tgt_txq_add_ucast(struct ath_softc_tgt *sc, struct ath_tx_buf *b
 	} else {
 		*txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
 
-		txe_val = OS_REG_READ(ah, 0x840);
+		txe_val = ioread32_mac(0x0840);
 		if (!(txe_val & (1<< txq->axq_qnum)))
 			ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
 	}
@@ -983,11 +989,12 @@ ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
 {
 	a_int32_t i ;
 	struct ath_tx_desc *bfd = NULL;
+	struct ath_hal *ah = sc->sc_ah;
 
 	for (bfd = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; bfd++, i++) {
-		ath_hal_clr11n_aggr(sc->sc_ah, bfd);
-		ath_hal_set11n_burstduration(sc->sc_ah, bfd, 0);
-		ath_hal_set11n_virtualmorefrag(sc->sc_ah, bfd, 0);
+		ah->ah_clr11nAggr(bfd);
+		ah->ah_set11nBurstDuration(bfd, 0);
+		ah->ah_set11nVirtualMoreFrag(bfd, 0);
 	}
 
 	ath_dma_unmap(sc, bf);
@@ -1049,7 +1056,7 @@ ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
 	struct ath_vap_target *avp;
 	struct ath_hal *ah = sc->sc_ah;
 	a_uint8_t rix, txrate, ctsrate, cix = 0xff, *data;
-	a_uint32_t ivlen = 0, icvlen = 0, subtype, flags, ctsduration;
+	a_uint32_t subtype, flags, ctsduration;
 	a_int32_t i, iswep, ismcast, hdrlen, pktlen, try0, len;
 	struct ath_tx_desc *ds=NULL;
 	struct ath_txq *txq=NULL;
@@ -1198,20 +1205,16 @@ ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
 
 	flags |= HAL_TXDESC_INTREQ;
 
-	ath_hal_setuptxdesc(ah, ds
+	ah->ah_setupTxDesc(ds
 			    , pktlen
 			    , hdrlen
 			    , atype
 			    , 60
 			    , txrate, try0
 			    , keyix
-			    , 0
 			    , flags
 			    , ctsrate
-			    , ctsduration
-			    , icvlen
-			    , ivlen
-			    , ATH_COMP_PROC_NO_COMP_NO_CCS);
+			    , ctsduration);
 
 	bf->bf_flags = flags;
 
@@ -1220,8 +1223,8 @@ ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
 	 * in Auth frame 3 of Shared Authentication, owl needs this.
 	 */
 	if (iswep && (keyix != HAL_TXKEYIX_INVALID) &&
-	    (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH)
-		ath_hal_fillkeytxdesc(ah, ds, mh->keytype);
+			(wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH)
+		ah->ah_fillKeyTxDesc(ds, mh->keytype);
 
 	ath_filltxdesc(sc, bf);
 
@@ -1231,7 +1234,7 @@ ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
 		series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
 		series[i].RateFlags = 0;
 	}
-	ah->ah_set11nRateScenario(ah, ds, 0, ctsrate, ctsduration, series, 4, 0);
+	ah->ah_set11nRateScenario(ds, 0, ctsrate, series, 4, 0);
 	ath_tgt_txqaddbuf(sc, txq, bf, bf->bf_lastds);
 
 	return;
@@ -1410,7 +1413,7 @@ ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
 			bf->bf_next = NULL;
 
 			for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
-				ath_hal_clr11n_aggr(sc->sc_ah, ds);
+				ah->ah_clr11nAggr(ds);
 
 			ath_buf_set_rate(sc, bf);
 			bf->bf_txq_add(sc, bf);
@@ -1424,12 +1427,12 @@ ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
 
 		bf->bf_isaggr  = 1;
 		ath_buf_set_rate(sc, bf);
-		ah->ah_set11nAggrFirst(ah, bf->bf_desc, bf->bf_al,
+		ah->ah_set11nAggrFirst(bf->bf_desc, bf->bf_al,
 					  bf->bf_ndelim);
 		bf->bf_lastds = bf_last->bf_lastds;
 
 		for (i = 0; i < bf_last->bf_dmamap_info.nsegs; i++)
-			ath_hal_set11n_aggr_last(sc->sc_ah, &bf_last->bf_descarr[i]);
+			ah->ah_set11nAggrLast(&bf_last->bf_descarr[i]);
 
 		if (status == ATH_AGGR_8K_LIMITED) {
 			adf_os_assert(0);
@@ -1497,6 +1500,7 @@ int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid,
 	int nframes = 0, rl = 0;;
 	struct ath_tx_desc *ds = NULL;
 	struct ath_tx_buf *bf;
+	struct ath_hal *ah = sc->sc_ah;
 	u_int16_t aggr_limit =  (64*1024 -1), al = 0, bpad = 0, al_delta;
 	u_int16_t h_baw = tid->baw_size/2, prev_al = 0, prev_frames = 0;
 
@@ -1573,7 +1577,7 @@ int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid,
 		bf_prev = bf;
 
 		for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
-			ath_hal_set11n_aggr_middle(sc->sc_ah, ds, bf->bf_ndelim);
+			ah->ah_set11nAggrMiddle(ds, bf->bf_ndelim);
 
 	} while (!asf_tailq_empty(&tid->buf_q));
 
@@ -1802,14 +1806,15 @@ ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
 	struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
 	ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
 	struct ath_tx_desc *ds = NULL;
+	struct ath_hal *ah = sc->sc_ah;
 	int i = 0;
 
 	__stats(sc, txaggr_compretries);
 
 	for(ds = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; ds++, i++) {
-		ath_hal_clr11n_aggr(sc->sc_ah, ds);
-		ath_hal_set11n_burstduration(sc->sc_ah, ds, 0);
-		ath_hal_set11n_virtualmorefrag(sc->sc_ah, ds, 0);
+		ah->ah_clr11nAggr(ds);
+		ah->ah_set11nBurstDuration(ds, 0);
+		ah->ah_set11nVirtualMoreFrag(ds, 0);
 	}
 
 	if (bf->bf_retries >= OWLMAX_RETRIES) {
@@ -2124,7 +2129,7 @@ static void ath_bar_tx(struct ath_softc_tgt *sc,
 	adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
 
 	ds = bf->bf_desc;
-	ath_hal_setuptxdesc(sc->sc_ah, ds
+	ah->ah_setupTxDesc(ds
 			    , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
 			    , 0
 			    , HAL_PKT_TYPE_NORMAL
@@ -2132,18 +2137,16 @@ static void ath_bar_tx(struct ath_softc_tgt *sc,
 			    , min_rate
 			    , ATH_TXMAXTRY
 			    , bf->bf_keyix
-			    , 0
 			    , HAL_TXDESC_INTREQ
 			    | HAL_TXDESC_CLRDMASK
-			    , 0, 0, 0, 0
-			    , ATH_COMP_PROC_NO_COMP_NO_CCS);
+			    , 0, 0);
 
 	skbhead = bf->bf_skbhead;
 	bf->bf_isaggr = 0;
 	bf->bf_next = NULL;
 
 	for (ds0 = ds, i=0; i < bf->bf_dmamap_info.nsegs; ds0++, i++) {
-		ath_hal_clr11n_aggr(sc->sc_ah, ds0);
+		ah->ah_clr11nAggr(ds0);
 	}
 
 	ath_filltxdesc(sc, bf);
@@ -2154,6 +2157,6 @@ static void ath_bar_tx(struct ath_softc_tgt *sc,
 		series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
 	}
 
-	ah->ah_set11nRateScenario(ah, bf->bf_desc, 0, 0, 0, series, 4, 4);
+	ah->ah_set11nRateScenario(bf->bf_desc, 0, 0, series, 4, 4);
 	ath_tgt_txq_add_ucast(sc, bf);
 }