X-Git-Url: https://jxself.org/git/?p=open-ath9k-htc-firmware.git;a=blobdiff_plain;f=target_firmware%2Fwlan%2Fif_ath.c;h=896e72b56ff8506d7658e27937150d8f04cb38af;hp=9f1e1722084e724aa536e1798b43f0baadd65d45;hb=ffd97659858ed6e9bd252ed1baa2243d8a725dd6;hpb=840acf98145130f2d6ce939fe4724d49b390e69c

diff --git a/target_firmware/wlan/if_ath.c b/target_firmware/wlan/if_ath.c
index 9f1e172..896e72b 100755
--- a/target_firmware/wlan/if_ath.c
+++ b/target_firmware/wlan/if_ath.c
@@ -80,17 +80,6 @@ void owl_tgt_node_init(struct ath_node_target * an);
 void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf);
 void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host);
 
-/*************/
-/* Utilities */
-/*************/
-
-#undef adf_os_cpu_to_le16
-
-static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x)
-{
-	return ((((x) & 0xff00) >> 8) |   (((x) & 0x00ff) << 8));
-}
-
 /*
  * Extend a 32 bit TSF to 64 bit, taking wrapping into account.
  */
@@ -266,9 +255,7 @@ static a_int32_t ath_rxdesc_init(struct ath_softc_tgt *sc, struct ath_rx_desc *d
 	ds->ds_link = 0;
 	adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen);
 
-	ah->ah_setupRxDesc(ah, ds,
-			    adf_nbuf_tailroom(ds->ds_nbuf),
-			    0);
+	ah->ah_setupRxDesc(ds, adf_nbuf_tailroom(ds->ds_nbuf), 0);
 
 	if (sc->sc_rxlink == NULL) {
 		ah->ah_setRxDP(ah, ds->ds_daddr);
@@ -555,22 +542,18 @@ static void ath_beacon_setup(struct ath_softc_tgt *sc,
 	rt  = sc->sc_currates;
 	rate = rt->info[rix].rateCode;
 
-	ah->ah_setupTxDesc(ah, ds
+	ah->ah_setupTxDesc(ds
 			    , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
 			    , sizeof(struct ieee80211_frame)
 			    , HAL_PKT_TYPE_BEACON
 			    , MAX_RATE_POWER
 			    , rate, 1
 			    , HAL_TXKEYIX_INVALID
-			    , 0
 			    , flags
 			    , 0
-			    , 0
-			    , 0
-			    , 0
-			    , ATH_COMP_PROC_NO_COMP_NO_CCS);
+			    , 0);
 
-	ath_hal_filltxdesc(ah, ds
+	ah->ah_fillTxDesc(ds
 			   , asf_roundup(adf_nbuf_len(skb), 4)
 			   , AH_TRUE
 			   , AH_TRUE
@@ -580,7 +563,7 @@ static void ath_beacon_setup(struct ath_softc_tgt *sc,
 	series[0].Rate = rate;
 	series[0].ChSel = sc->sc_ic.ic_tx_chainmask;
 	series[0].RateFlags = 0;
-	ah->ah_set11nRateScenario(ah, ds, 0, 0, 0, series, 4, 0);
+	ah->ah_set11nRateScenario(ds, 0, 0, series, 4, 0);
 }
 
 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr,
@@ -1143,7 +1126,7 @@ static void ath_init_tgt(void *Context, A_UINT16 Command,
 
 	sc->sc_imask |= HAL_INT_GTT;
 
-	if (ath_hal_htsupported(ah))
+	if (ath_hal_getcapability(ah, HAL_CAP_HT))
 		sc->sc_imask |= HAL_INT_CST;
 
 	adf_os_setup_intr(sc->sc_dev, ath_intr);
@@ -1442,10 +1425,7 @@ static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command,
 		t = (struct registerWrite *)(data+i);
 
 		if( t->reg > 0xffff ) {
-			a_uint32_t *pReg = (a_uint32_t *)t->reg;
-
-			*pReg = t->val;
-
+			HAL_WORD_REG_WRITE(t->reg, t->val);
 #if defined(PROJECT_K2)
 			if( t->reg == 0x50040 ) {
 				static uint8_t flg=0;
@@ -1461,20 +1441,19 @@ static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command,
 #if defined(PROJECT_K2)
 			if( t->reg == 0x7014 ) {
 				static uint8_t resetPLL = 0;
-				a_uint32_t *pReg;
 
 				if( resetPLL == 0 ) {
-					t->reg = 0x50044;
-					pReg = (a_uint32_t *)t->reg;
-					*pReg = 0;
+					/* here we write to core register */
+					HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
+					/* and here to mac register */
 					ath_hal_reg_write_target(ah, 0x786c,
 						 ath_hal_reg_read_target(ah,0x786c) | 0x6000000);
 					ath_hal_reg_write_target(ah, 0x786c,
 						 ath_hal_reg_read_target(ah,0x786c) & (~0x6000000));
-					*pReg = 0x20;
+
+					HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
 					resetPLL = 1;
 				}
-				t->reg = 0x7014;
 			}
 #elif defined(PROJECT_MAGPIE) && !defined (FPGA)
 			if( t->reg == 0x7014 ){