2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2005 Atheros Communications, Inc.
6 * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/hal/main/ar5416/ar5416phy.h#1 $
8 #ifndef _DEV_ATH_AR5416PHY_H_
9 #define _DEV_ATH_AR5416PHY_H_
12 #define AR_PHY_BASE 0x9800 /* base address of phy regs */
13 #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
15 #define AR_PHY_TEST 0x9800 /* PHY test control */
16 #define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */
17 #define RFSILENT_BB 0x00002000 /* shush bb */
19 /* TX99_11N_CHANGE begin */
20 #define AR_PHY_TESTCTRL 0x9808 /* PHY Test Control/Status */
21 #define AR_PHY_TESTCTRL_TXHOLD 0x3800 /* Select Tx hold */
22 #define AR_PHY_TESTCTRL_TXSRC_ALT 0x00000080 /* Select input to tsdac along with bit 1 */
23 #define AR_PHY_TESTCTRL_TXSRC_ALT_S 7
24 #define AR_PHY_TESTCTRL_TXSRC_SRC 0x00000002 /* Used with bit 7 */
25 #define AR_PHY_TESTCTRL_TXSRC_SRC_S 1
26 /* TX99_11N_CHANGE end */
29 #define AR_PHY_TURBO 0x9804 /* frame control register */
30 #define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */
31 #define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */
32 #define AR_PHY_FC_DYN2040_EN 0x00000004 /* Enable dyn 20/40 mode */
33 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
34 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
35 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
36 #define AR_PHY_FC_HT_EN 0x00000040 /* ht enable */
37 #define AR_PHY_FC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
38 #define AR_PHY_FC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */
39 #define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
41 #define AR_PHY_TIMING2 0x9810 /* Timing Control 2 */
42 #define AR_PHY_TIMING2_USE_FORCE 0x00001000
43 #define AR_PHY_TIMING2_FORCE_VAL 0x00000fff
45 #define AR_PHY_TIMING3 0x9814 /* Timing control 3 */
46 #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
47 #define AR_PHY_TIMING3_DSC_MAN_S 17
48 #define AR_PHY_TIMING3_DSC_EXP 0x0001E000
49 #define AR_PHY_TIMING3_DSC_EXP_S 13
51 #define AR_PHY_CHIP_ID 0x9818 /* PHY chip revision ID */
52 #define AR_PHY_CHIP_ID_REV_0 0x80 /* 5416 Rev 0 (owl 1.0) BB */
53 #define AR_PHY_CHIP_ID_REV_1 0x81 /* 5416 Rev 1 (owl 2.0) BB */
54 #define AR_PHY_CHIP_ID_SOWL_REV_0 0xb0 /* 9160 Rev 0 (sowl 1.0) BB */
56 #define AR_PHY_ACTIVE 0x981C /* activation register */
57 #define AR_PHY_ACTIVE_EN 0x00000001 /* Activate PHY chips */
58 #define AR_PHY_ACTIVE_DIS 0x00000000 /* Deactivate PHY chips */
60 #define AR_PHY_RF_CTL2 0x9824
61 #define AR_PHY_TX_END_DATA_START 0x000000FF
62 #define AR_PHY_TX_END_DATA_START_S 0
63 #define AR_PHY_TX_END_PA_ON 0x0000FF00
64 #define AR_PHY_TX_END_PA_ON_S 8
67 #define AR_PHY_RF_CTL3 0x9828
68 #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
69 #define AR_PHY_TX_END_TO_A2_RX_ON_S 16
71 #define AR_PHY_ADC_CTL 0x982C
72 #define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
73 #define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
74 #define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
75 #define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000 /* BB Rev 4.2+ only */
76 #define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000 /* BB Rev 4.2+ only */
77 #define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
78 #define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
80 #define AR_PHY_ADC_SERIAL_CTL 0x9830
81 #define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
82 #define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
84 #define AR_PHY_RF_CTL4 0x9834
85 #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
86 #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
87 #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
88 #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
89 #define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
90 #define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
91 #define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
92 #define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
94 /* TX99_11N_CHANGE begin */
95 #define AR_PHY_BB_XP_PA_CTL 0x9838
96 #define AR_PHY_BB_XPAA_ACTIVE_HIGH 0x00000001
97 #define AR_PHY_BB_XPAB_ACTIVE_HIGH 0x00000002
98 #define AR_PHY_BB_XPAB_ACTIVE_HIGH_S 1
100 #define AR_PHY_TSTDAC_CONST 0x983C
101 #define AR_PHY_TSTDAC_CONST_Q 0x0003FE00
102 #define AR_PHY_TSTDAC_CONST_Q_S 9
103 #define AR_PHY_TSTDAC_CONST_I 0x000001FF
104 /* TX99_11N_CHANGE end */
106 #define AR_PHY_SETTLING 0x9844
107 #define AR_PHY_SETTLING_SWITCH 0x00003F80
108 #define AR_PHY_SETTLING_SWITCH_S 7
110 #define AR_PHY_RXGAIN 0x9848
111 #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
112 #define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
113 #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
114 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
116 #define AR_PHY_DESIRED_SZ 0x9850
117 #define AR_PHY_DESIRED_SZ_ADC 0x000000FF
118 #define AR_PHY_DESIRED_SZ_ADC_S 0
119 #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
120 #define AR_PHY_DESIRED_SZ_PGA_S 8
121 #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
122 #define AR_PHY_DESIRED_SZ_TOT_DES_S 20
124 #define AR_PHY_FIND_SIG 0x9858
125 #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
126 #define AR_PHY_FIND_SIG_FIRSTEP_S 12
127 #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
128 #define AR_PHY_FIND_SIG_FIRPWR_S 18
130 #define AR_PHY_AGC_CTL1 0x985C
131 #define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
132 #define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
133 #define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000
134 #define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
136 #define AR_PHY_AGC_CONTROL 0x9860 /* chip calibration and noise floor setting */
137 #define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */
138 #define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calculation */
140 #define AR_PHY_CCA 0x9864
141 #define AR_PHY_MINCCA_PWR 0x0FF80000
142 #define AR_PHY_MINCCA_PWR_S 19
143 #define AR_PHY_CCA_THRESH62 0x0007F000
144 #define AR_PHY_CCA_THRESH62_S 12
146 #define AR_PHY_SFCORR_LOW 0x986C
147 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
148 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
149 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
150 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
151 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
152 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
153 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
155 #define AR_PHY_SFCORR 0x9868
156 #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
157 #define AR_PHY_SFCORR_M2COUNT_THR_S 0
158 #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
159 #define AR_PHY_SFCORR_M1_THRESH_S 17
160 #define AR_PHY_SFCORR_M2_THRESH 0x7F000000
161 #define AR_PHY_SFCORR_M2_THRESH_S 24
163 #define AR_PHY_SLEEP_CTR_CONTROL 0x9870
164 #define AR_PHY_SLEEP_CTR_LIMIT 0x9874
165 #define AR_PHY_SLEEP_SCAL 0x9878
167 #define AR_PHY_PLL_CTL 0x987c /* PLL control register */
168 #define AR_PHY_PLL_CTL_40 0xaa /* 40 MHz */
169 #define AR_PHY_PLL_CTL_40_5413 0x04
170 #define AR_PHY_PLL_CTL_44 0xab /* 44 MHz for 11b, 11g */
171 #define AR_PHY_PLL_CTL_44_2133 0xeb /* 44 MHz for 11b, 11g */
172 #define AR_PHY_PLL_CTL_40_2133 0xea /* 40 MHz for 11a, turbos */
174 #define AR_PHY_RX_DELAY 0x9914 /* analog pow-on time (100ns) */
175 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */
177 #define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12)) /* timing control */
178 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F /* Mask for kcos_theta-1 for q correction */
179 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 /* shift for Q_COFF */
180 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 /* Mask for sin_theta for i correction */
181 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 /* Shift for sin_theta for i correction */
182 #define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 /* enable IQ correction */
183 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 /* Mask for max number of samples (logarithmic) */
184 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 /* Shift for max number of samples */
185 #define AR_PHY_TIMING_CTRL4_DO_IQCAL 0x10000 /* perform IQ calibration */
187 #define AR_PHY_TIMING5 0x9924
188 #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
189 #define AR_PHY_TIMING5_CYCPWR_THR1_S 1
191 #define AR_PHY_POWER_TX_RATE1 0x9934
192 #define AR_PHY_POWER_TX_RATE2 0x9938
193 #define AR_PHY_POWER_TX_RATE_MAX 0x993c
194 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
196 #define AR_PHY_FRAME_CTL 0x9944
197 #define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038
198 #define AR_PHY_FRAME_CTL_TX_CLIP_S 3
200 #define AR_PHY_TXPWRADJ 0x994C /* BB Rev 4.2+ only */
201 #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0
202 #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
203 #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000
204 #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
206 #define AR_PHY_RADAR_0 0x9954 /* radar detection settings */
207 #define AR_PHY_RADAR_0_ENA 0x00000001 /* Enable radar detection */
208 #define AR_PHY_RADAR_0_INBAND 0x0000003e /* Inband pulse threshold */
209 #define AR_PHY_RADAR_0_INBAND_S 1
210 #define AR_PHY_RADAR_0_PRSSI 0x00000FC0 /* Pulse rssi threshold */
211 #define AR_PHY_RADAR_0_PRSSI_S 6
212 #define AR_PHY_RADAR_0_HEIGHT 0x0003F000 /* Pulse height threshold */
213 #define AR_PHY_RADAR_0_HEIGHT_S 12
214 #define AR_PHY_RADAR_0_RRSSI 0x00FC0000 /* Radar rssi threshold */
215 #define AR_PHY_RADAR_0_RRSSI_S 18
216 #define AR_PHY_RADAR_0_FIRPWR 0x7F000000 /* Radar firpwr threshold */
217 #define AR_PHY_RADAR_0_FIRPWR_S 24
219 #define AR_PHY_RADAR_1 0x9958 /* AR5413+ radar settigns */
220 #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 /* enable to check radar relative power */
221 #define AR_PHY_RADAR_1_USE_FIR128 0x00400000 /* enable to use the average inband power
222 * measured over 128 cycles
224 #define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 /* relative pwr thresh */
225 #define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
226 #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 /* Enable to block radar check if weak
227 * OFDM sig or pkt is immediately after
228 * tx to rx transition
230 #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 /* Enable to use max rssi */
231 #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 /* Enable to use pulse relative step check */
232 #define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 /* Pulse relative step threshold */
233 #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
234 #define AR_PHY_RADAR_1_MAXLEN 0x000000FF /* Max length of radar pulse */
235 #define AR_PHY_RADAR_1_MAXLEN_S 0
237 #define AR_PHY_SWITCH_CHAIN_0 0x9960
238 #define AR_PHY_SWITCH_COM 0x9964
240 #define AR_PHY_SIGMA_DELTA 0x996C /* AR5312 only */
241 #define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
242 #define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
243 #define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8
244 #define AR_PHY_SIGMA_DELTA_FILT2_S 3
245 #define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00
246 #define AR_PHY_SIGMA_DELTA_FILT1_S 8
247 #define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000
248 #define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
250 #define AR_PHY_RESTART 0x9970 /* restart */
251 #define AR_PHY_RESTART_DIV_GC 0x001C0000 /* bb_ant_fast_div_gc_limit */
252 #define AR_PHY_RESTART_DIV_GC_S 18
254 #define AR_PHY_RFBUS_REQ 0x997C
255 #define AR_PHY_RFBUS_REQ_EN 0x00000001
257 #define AR_PHY_RX_CHAINMASK 0x99a4
259 #define AR_PHY_EXT_CCA 0x99bc
260 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000 // [22:16] not replicated
261 #define AR_PHY_EXT_CCA_THRESH62_S 16
262 #define AR_PHY_EXT_MINCCA_PWR 0xFF800000
263 #define AR_PHY_EXT_MINCCA_PWR_S 23
265 #define AR_PHY_HALFGI 0x99D0 /* Timing control 3 */
266 #define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
267 #define AR_PHY_HALFGI_DSC_MAN_S 4
268 #define AR_PHY_HALFGI_DSC_EXP 0x0000000F
269 #define AR_PHY_HALFGI_DSC_EXP_S 0
271 #define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
273 #define AR_PHY_M_SLEEP 0x99f0 /* sleep control registers */
274 #define AR_PHY_REFCLKDLY 0x99f4
275 #define AR_PHY_REFCLKPD 0x99f8
277 #define AR_PHY_CALMODE 0x99f0
278 /* PHY IQ calibration results */
279 #define AR_PHY_IQCAL_RES_PWR_MEAS_I(_i) (0x9c10 + ((_i) << 12)) /* power measurement for I */
280 #define AR_PHY_IQCAL_RES_PWR_MEAS_Q(_i) (0x9c14 + ((_i) << 12)) /* power measurement for Q */
281 #define AR_PHY_IQCAL_RES_IQ_CORR_MEAS(_i) (0x9c18 + ((_i) << 12)) /* IQ correlation measurement */
283 #define AR_PHY_CURRENT_RSSI 0x9c1c /* rssi of current frame rx'd */
285 #define AR_PHY_RFBUS_GRANT 0x9C20
286 #define AR_PHY_RFBUS_GRANT_EN 0x00000001
288 #define AR_PHY_MODE 0xA200 /* Mode register */
289 #define AR_PHY_MODE_AR2133 0x08 /* AR2133 */
290 #define AR_PHY_MODE_AR5111 0x00 /* AR5111/AR2111 */
291 #define AR_PHY_MODE_AR5112 0x08 /* AR5112*/
292 #define AR_PHY_MODE_DYNAMIC 0x04 /* dynamic CCK/OFDM mode */
293 #define AR_PHY_MODE_RF2GHZ 0x02 /* 2.4 GHz */
294 #define AR_PHY_MODE_RF5GHZ 0x00 /* 5 GHz */
295 #define AR_PHY_MODE_CCK 0x01 /* CCK */
296 #define AR_PHY_MODE_OFDM 0x00 /* OFDM */
298 #define AR_PHY_CCK_TX_CTRL 0xA204
299 #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
301 #define AR_PHY_CCK_DETECT 0xA208
302 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
303 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
304 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 // [12:6] settling time for antenna switch
305 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
306 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
308 #define AR_PHY_GAIN_2GHZ 0xA20C
309 #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
310 #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
311 #define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
312 #define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
313 #define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
314 #define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
316 #define AR_PHY_CCK_RXCTRL4 0xA21C
317 #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000
318 #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
320 #define AR_PHY_DAG_CTRLCCK 0xA228
321 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 /* BB Rev 4.2+ only */
322 #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00 /* BB Rev 4.2+ only */
323 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 /* BB Rev 4.2+ only */
325 #define AR_PHY_POWER_TX_RATE3 0xA234
326 #define AR_PHY_POWER_TX_RATE4 0xA238
328 #define AR_PHY_SCRM_SEQ_XR 0xA23C
329 #define AR_PHY_HEADER_DETECT_XR 0xA240
330 #define AR_PHY_CHIRP_DETECTED_XR 0xA244
331 #define AR_PHY_BLUETOOTH 0xA254
333 #define AR_PHY_TPCRG1 0xA258 /* ar2413 power control */
334 #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
335 #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
337 #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
338 #define AR_PHY_TPCRG1_PD_GAIN_1_S 16
339 #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
340 #define AR_PHY_TPCRG1_PD_GAIN_2_S 18
341 #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
342 #define AR_PHY_TPCRG1_PD_GAIN_3_S 20
345 #define AR_PHY_ANALOG_SWAP 0xa268
346 #define AR_PHY_SWAP_ALT_CHAIN 0x00000040
348 #define AR_PHY_TPCRG5 0xA26C /* ar2413 power control */
349 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
350 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
351 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
352 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
353 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
354 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
355 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
356 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
357 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
358 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
360 #define AR_PHY_POWER_TX_RATE5 0xA38C
361 #define AR_PHY_POWER_TX_RATE6 0xA390
363 #define AR_PHY_CAL_CHAINMASK 0xA39C
365 #define AR_PHY_POWER_TX_SUB 0xA3C8
366 #define AR_PHY_POWER_TX_RATE7 0xA3CC
367 #define AR_PHY_POWER_TX_RATE8 0xA3D0
368 #define AR_PHY_POWER_TX_RATE9 0xA3D4
370 #define AR_PHY_CH1_CCA 0xa864
371 #define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
372 #define AR_PHY_CH1_MINCCA_PWR_S 19
374 #define AR_PHY_CH2_CCA 0xb864
375 #define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
376 #define AR_PHY_CH2_MINCCA_PWR_S 19
378 #define AR_PHY_CH1_EXT_CCA 0xa9bc
379 #define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
380 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
382 #define AR_PHY_CH2_EXT_CCA 0xb9bc
383 #define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
384 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
389 #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
390 #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
391 #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
392 #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
394 #define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* Enable noise floor calibration to happen */
395 #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* Don't update noise floor automatically */
397 #define AR9280_PHY_MINCCA_PWR 0x1FF00000
398 #define AR9280_PHY_MINCCA_PWR_S 20
399 #define AR9280_PHY_CCA_THRESH62 0x000FF000
400 #define AR9280_PHY_CCA_THRESH62_S 12
402 #define AR_PHY_CCA_MAX_GOOD_VALUE -85
403 #define AR_PHY_CCA_MAX_HIGH_VALUE -62
404 #define AR_PHY_CCA_MIN_BAD_VALUE -121
406 #define AR_PHY_SYNTH_CONTROL 0x9874
407 #define AR9280_PHY_CURRENT_RSSI 0x9c3c
409 #define AR9280_PHY_CURRENT_RSSI 0x9c3c
411 #define AR_PHY_XPA_CFG 0xA3D8
412 #define AR_PHY_FORCE_XPA_CFG 0x000000001
413 #define AR_PHY_FORCE_XPA_CFG_S 0
415 #define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
416 #define AR9280_PHY_CH1_MINCCA_PWR_S 20
418 #define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
419 #define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
425 #endif /* _DEV_ATH_AR5416PHY_H_ */