carl9170fw/carlfw/include/dma.h

   1 /*
   2  * carl9170 firmware - used by the ar9170 wireless device
   3  *
   4  * This module contains DMA descriptor related definitions.
   5  *
   6  * Copyright (c) 2000-2005 ZyDAS Technology Corporation
   7  * Copyright (c) 2007-2009 Atheros Communications, Inc.
   8  * Copyright    2009    Johannes Berg <johannes@sipsolutions.net>
   9  * Copyright 2009-2011  Christian Lamparter <chunkeey@googlemail.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License along
  22  * with this program; if not, write to the Free Software Foundation, Inc.,
  23  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  24  */
  25
  26 #ifndef __CARL9170FW_DMA_H
  27 #define __CARL9170FW_DMA_H
  28
  29 #include "config.h"
  30 #include "types.h"
  31 #include "compiler.h"
  32 #include "hw.h"
  33 #include "ieee80211.h"
  34 #include "wlan.h"
  35
  36 struct dma_desc {
  37         volatile uint16_t status;       /* Descriptor status */
  38         volatile uint16_t ctrl;         /* Descriptor control */
  39         volatile uint16_t dataSize;     /* Data size */
  40         volatile uint16_t totalLen;     /* Total length */
  41         struct dma_desc *lastAddr;      /* Last address of this chain */
  42         union {
  43                 uint8_t *_dataAddr;     /* Data buffer address */
  44                 void *dataAddr;
  45         } __packed;
  46         struct dma_desc *nextAddr;      /* Next TD address */
  47 } __packed __aligned(4);
  48
  49 /* Up, Dn, 5x Tx, retry, Rx, [USB Int], (CAB), FW */
  50 #define AR9170_TERMINATOR_NUMBER_B      10
  51
  52 #define AR9170_TERMINATOR_NUMBER_INT    1
  53
  54 #define AR9170_TERMINATOR_NUMBER_CAB    CARL9170_INTF_NUM
  55
  56 #define AR9170_TERMINATOR_NUMBER (AR9170_TERMINATOR_NUMBER_B + \
  57                                   AR9170_TERMINATOR_NUMBER_INT + \
  58                                   AR9170_TERMINATOR_NUMBER_CAB)
  59
  60 #define AR9170_BLOCK_SIZE           (256 + 64)
  61
  62 #define AR9170_DESCRIPTOR_SIZE      (sizeof(struct dma_desc))
  63
  64 struct ar9170_tx_ba_frame {
  65         struct ar9170_tx_hwdesc hdr;
  66         struct ieee80211_ba ba;
  67 } __packed;
  68
  69 struct carl9170_tx_ba_superframe {
  70         struct carl9170_tx_superdesc s;
  71         struct ar9170_tx_ba_frame f;
  72 } __packed;
  73
  74 struct ar9170_tx_null_frame {
  75         struct ar9170_tx_hwdesc hdr;
  76         struct ieee80211_hdr null;
  77 } __packed;
  78
  79 struct carl9170_tx_null_superframe {
  80         struct carl9170_tx_superdesc s;
  81         struct ar9170_tx_null_frame f;
  82 } __packed;
  83
  84 #define CARL9170_BA_BUFFER_LEN  (__roundup(sizeof(struct carl9170_tx_ba_superframe), 16))
  85 #define CARL9170_RSP_BUFFER_LEN AR9170_BLOCK_SIZE
  86
  87 struct carl9170_sram_reserved {
  88         union {
  89                 uint32_t buf[CARL9170_BA_BUFFER_LEN / sizeof(uint32_t)];
  90                 struct carl9170_tx_ba_superframe ba;
  91         } ba;
  92
  93         union {
  94                 uint32_t buf[CARL9170_MAX_CMD_LEN / sizeof(uint32_t)];
  95                 struct carl9170_cmd cmd;
  96
  97 #ifdef CONFIG_CARL9170FW_WOL
  98                 struct carl9170_tx_null_superframe null;
  99 #endif /* CONFIG_CARL9170FW_WOL */
 100         } cmd;
 101
 102         union {
 103                 uint32_t buf[CARL9170_RSP_BUFFER_LEN / sizeof(uint32_t)];
 104                 struct carl9170_rsp rsp;
 105         } rsp;
 106
 107         union {
 108                 uint32_t buf[CARL9170_INTF_NUM][AR9170_MAC_BCN_LENGTH_MAX / sizeof(uint32_t)];
 109         } bcn;
 110 };
 111
 112 /*
 113  * Memory layout in RAM:
 114  *
 115  * 0x100000                     +--
 116  *                              | terminator descriptors (dma_desc)
 117  *                              |  - Up (to USB host)
 118  *                              |  - Down (from USB host)
 119  *                              |  - TX (5x, to wifi)
 120  *                              |  - AMPDU TX retry
 121  *                              |  - RX (from wifi)
 122  *                              |  - CAB Queue
 123  *                              |  - FW cmd & req descriptor
 124  *                              |  - BlockAck descriptor
 125  *                              | total: AR9170_TERMINATOR_NUMBER
 126  *                              +--
 127  *                              | block descriptors (dma_desc)
 128  *                              | (AR9170_BLOCK_NUMBER)
 129  * AR9170_BLOCK_BUFFER_BASE     +-- align to multiple of 64
 130  *                              | block buffers (AR9170_BLOCK_SIZE each)
 131  *                              | (AR9170_BLOCK_NUMBER)
 132  * approx. 0x117c00             +--
 133  *                              | BA buffer (128 bytes)
 134  *                              +--
 135  *                              | CMD buffer (128 bytes)
 136  *                              | - used as NULLFRAME buffer (128 bytes) for WOL
 137  *                              +--
 138  *                              | RSP buffer (320 bytes)
 139  *                              +--
 140  *                              | BEACON buffer (256 bytes)
 141  *                              +--
 142  *                              | unaccounted space / padding
 143  *                              +--
 144  * 0x18000
 145  */
 146
 147 #define CARL9170_SRAM_RESERVED          (sizeof(struct carl9170_sram_reserved))
 148
 149 #define AR9170_FRAME_MEMORY_SIZE        (AR9170_SRAM_SIZE - CARL9170_SRAM_RESERVED)
 150
 151 #define BLOCK_ALIGNMENT         64
 152
 153 #define NONBLOCK_DESCRIPTORS_SIZE       \
 154         (AR9170_DESCRIPTOR_SIZE * (AR9170_TERMINATOR_NUMBER))
 155
 156 #define NONBLOCK_DESCRIPTORS_SIZE_ALIGNED       \
 157         (ALIGN(NONBLOCK_DESCRIPTORS_SIZE, BLOCK_ALIGNMENT))
 158
 159 #define AR9170_BLOCK_NUMBER     ((AR9170_FRAME_MEMORY_SIZE - NONBLOCK_DESCRIPTORS_SIZE_ALIGNED) / \
 160                                  (AR9170_BLOCK_SIZE + AR9170_DESCRIPTOR_SIZE))
 161
 162 struct ar9170_data_block {
 163         uint8_t data[AR9170_BLOCK_SIZE];
 164 };
 165
 166 struct ar9170_dma_memory {
 167         struct dma_desc                 terminator[AR9170_TERMINATOR_NUMBER];
 168         struct dma_desc                 block[AR9170_BLOCK_NUMBER];
 169         struct ar9170_data_block        data[AR9170_BLOCK_NUMBER] __aligned(BLOCK_ALIGNMENT);
 170         struct carl9170_sram_reserved   reserved __aligned(BLOCK_ALIGNMENT);
 171 };
 172
 173 extern struct ar9170_dma_memory dma_mem;
 174
 175 #define AR9170_DOWN_BLOCK_RATIO 2
 176 #define AR9170_RX_BLOCK_RATIO   1
 177 /* Tx 16*2 = 32 packets => 32*(5*320) */
 178 #define AR9170_TX_BLOCK_NUMBER  (AR9170_BLOCK_NUMBER * AR9170_DOWN_BLOCK_RATIO / \
 179                                 (AR9170_RX_BLOCK_RATIO + AR9170_DOWN_BLOCK_RATIO))
 180 #define AR9170_RX_BLOCK_NUMBER  (AR9170_BLOCK_NUMBER - AR9170_TX_BLOCK_NUMBER)
 181
 182 /* Error code */
 183 #define AR9170_ERR_FS_BIT       1
 184 #define AR9170_ERR_LS_BIT       2
 185 #define AR9170_ERR_OWN_BITS     3
 186 #define AR9170_ERR_DATA_SIZE    4
 187 #define AR9170_ERR_TOTAL_LEN    5
 188 #define AR9170_ERR_DATA         6
 189 #define AR9170_ERR_SEQ          7
 190 #define AR9170_ERR_LEN          8
 191
 192 /* Status bits definitions */
 193 /* Own bits definitions */
 194 #define AR9170_OWN_BITS         0x3
 195 #define AR9170_OWN_BITS_S       0
 196 #define AR9170_OWN_BITS_SW      0x0
 197 #define AR9170_OWN_BITS_HW      0x1
 198 #define AR9170_OWN_BITS_SE      0x2
 199
 200 /* Control bits definitions */
 201 #define AR9170_CTRL_TXFAIL      1
 202 #define AR9170_CTRL_BAFAIL      2
 203 #define AR9170_CTRL_FAIL        (AR9170_CTRL_TXFAIL | AR9170_CTRL_BAFAIL)
 204
 205 /* First segament bit */
 206 #define AR9170_CTRL_LS_BIT      0x100
 207 /* Last segament bit */
 208 #define AR9170_CTRL_FS_BIT      0x200
 209
 210 struct dma_queue {
 211         struct dma_desc *head;
 212         struct dma_desc *terminator;
 213 };
 214
 215 #define DESC_PAYLOAD(a)                 ((void *)a->dataAddr)
 216 #define DESC_PAYLOAD_OFF(a, offset)     ((void *)((unsigned long)(a->_dataAddr) + offset))
 217
 218 struct dma_desc *dma_unlink_head(struct dma_queue *queue);
 219 void dma_init_descriptors(void);
 220 void dma_reclaim(struct dma_queue *q, struct dma_desc *desc);
 221 void dma_put(struct dma_queue *q, struct dma_desc *desc);
 222
 223 static inline __inline bool is_terminator(struct dma_queue *q, struct dma_desc *desc)
 224 {
 225         return q->terminator == desc;
 226 }
 227
 228 static inline __inline bool queue_empty(struct dma_queue *q)
 229 {
 230         return q->head == q->terminator;
 231 }
 232
 233 /*
 234  * Get a completed packet with # descriptors. Return the first
 235  * descriptor and pointer the head directly by lastAddr->nextAddr
 236  */
 237 static inline __inline struct dma_desc *dma_dequeue_bits(struct dma_queue *q,
 238                                                 uint16_t bits)
 239 {
 240         struct dma_desc *desc = NULL;
 241
 242         if ((q->head->status & AR9170_OWN_BITS) == bits)
 243                 desc = dma_unlink_head(q);
 244
 245         return desc;
 246 }
 247
 248 static inline __inline struct dma_desc *dma_dequeue_not_bits(struct dma_queue *q,
 249                                                     uint16_t bits)
 250 {
 251         struct dma_desc *desc = NULL;
 252
 253         /* AR9170_OWN_BITS_HW will be filtered out here too. */
 254         if ((q->head->status & AR9170_OWN_BITS) != bits)
 255                 desc = dma_unlink_head(q);
 256
 257         return desc;
 258 }
 259
 260 #define for_each_desc_bits(desc, queue, bits)                           \
 261         while ((desc = dma_dequeue_bits(queue, bits)))
 262
 263 #define for_each_desc_not_bits(desc, queue, bits)                       \
 264         while ((desc = dma_dequeue_not_bits(queue, bits)))
 265
 266 #define for_each_desc(desc, queue)                                      \
 267         while ((desc = dma_unlink_head(queue)))
 268
 269 #define __for_each_desc_bits(desc, queue, bits)                         \
 270         for (desc = (queue)->head;                                      \
 271              (desc != (queue)->terminator &&                            \
 272              (desc->status & AR9170_OWN_BITS) == bits);                 \
 273              desc = desc->lastAddr->nextAddr)
 274
 275 #define __while_desc_bits(desc, queue, bits)                            \
 276         for (desc = (queue)->head;                                      \
 277              (!queue_empty(queue) &&                                    \
 278              (desc->status & AR9170_OWN_BITS) == bits);                 \
 279              desc = (queue)->head)
 280
 281 #define __for_each_desc_continue(desc, queue)                           \
 282         for (; desc != (queue)->terminator;                             \
 283              desc = (desc)->lastAddr->nextAddr)
 284
 285 #define __for_each_desc(desc, queue)                                    \
 286         for (desc = (queue)->head;                                      \
 287              desc != (queue)->terminator;                               \
 288              desc = (desc)->lastAddr->nextAddr)
 289
 290 #define __for_each_desc_safe(desc, tmp, queue)                          \
 291         for (desc = (queue)->head, tmp = desc->lastAddr->nextAddr;      \
 292              desc != (queue)->terminator;                               \
 293              desc = tmp, tmp = tmp->lastAddr->nextAddr)
 294
 295 #define __while_subdesc(desc, queue)                                    \
 296         for (desc = (queue)->head;                                      \
 297              desc != (queue)->terminator;                               \
 298              desc = (desc)->nextAddr)
 299
 300 static inline __inline unsigned int queue_len(struct dma_queue *q)
 301 {
 302         struct dma_desc *desc;
 303         unsigned int i = 0;
 304
 305         __while_subdesc(desc, q)
 306                 i++;
 307
 308         return i;
 309 }
 310
 311 /*
 312  * rearm a completed packet, so it will be processed agian.
 313  */
 314 static inline __inline void dma_rearm(struct dma_desc *desc)
 315 {
 316         /* Set OWN bit to HW */
 317         desc->status = ((desc->status & (~AR9170_OWN_BITS)) |
 318                         AR9170_OWN_BITS_HW);
 319 }
 320
 321 static inline __inline void dma_fix_downqueue(struct dma_desc *desc)
 322 {
 323         desc->status = AR9170_OWN_BITS_HW;
 324         desc->ctrl = 0;
 325         desc->dataSize = 0;
 326         desc->totalLen = AR9170_BLOCK_SIZE;
 327         desc->lastAddr = desc;
 328 }
 329
 330 static inline void __check_desc(void)
 331 {
 332         struct ar9170_dma_memory mem;
 333         BUILD_BUG_ON(sizeof(struct ar9170_data_block) != AR9170_BLOCK_SIZE);
 334         BUILD_BUG_ON(sizeof(struct dma_desc) != 20);
 335
 336         BUILD_BUG_ON(sizeof(mem) > AR9170_SRAM_SIZE);
 337
 338         BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, ba.buf) & (BLOCK_ALIGNMENT - 1));
 339         BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, cmd.buf) & (BLOCK_ALIGNMENT - 1));
 340         BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, rsp.buf) & (BLOCK_ALIGNMENT - 1));
 341         BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, bcn.buf) & (BLOCK_ALIGNMENT - 1));
 342         BUILD_BUG_ON(sizeof(struct carl9170_tx_null_superframe) > CARL9170_MAX_CMD_LEN);
 343 }
 344
 345 #endif /* __CARL9170FW_DMA_H */