ath9k_htc/target_firmware/wlan/if_ath.c

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted (subject to the limitations in the
   7  * disclaimer below) provided that the following conditions are met:
   8  *
   9  *  * Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  *  * Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the
  15  *    distribution.
  16  *
  17  *  * Neither the name of Qualcomm Atheros nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  *
  21  * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
  22  * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
  23  * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  32  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  33  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 #include <adf_os_types.h>
  37 #include <adf_os_pci.h>
  38 #include <adf_os_dma.h>
  39 #include <adf_os_timer.h>
  40 #include <adf_os_lock.h>
  41 #include <adf_os_io.h>
  42 #include <adf_os_mem.h>
  43 #include <adf_os_util.h>
  44 #include <adf_os_stdtypes.h>
  45 #include <adf_os_defer.h>
  46 #include <adf_os_atomic.h>
  47 #include <adf_nbuf.h>
  48 #include <adf_net.h>
  49 #include <adf_net_wcmd.h>
  50 #include <adf_os_irq.h>
  51
  52 #include <if_ath_pci.h>
  53 #include "if_llc.h"
  54 #include "ieee80211_var.h"
  55 #include "if_athrate.h"
  56 #include "if_athvar.h"
  57 #include "ah_desc.h"
  58 #include "ah.h"
  59 #include "ratectrl.h"
  60 #include "ah_internal.h"
  61
  62 static a_int32_t ath_numrxbufs = -1;
  63 static a_int32_t ath_numrxdescs = -1;
  64
  65 #if defined(PROJECT_MAGPIE)
  66 uint32_t *init_htc_handle = 0;
  67 #endif
  68
  69 #define RX_ENDPOINT_ID 3
  70 #define ATH_CABQ_HANDLING_THRESHOLD 9000
  71 #define UAPSDQ_NUM   9
  72 #define CABQ_NUM     8
  73
  74 void owl_tgt_tx_tasklet(TQUEUE_ARG data);
  75 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc,adf_nbuf_t bc_hdr,adf_nbuf_t nbuf,HTC_ENDPOINT_ID EndPt);
  76 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
  77 static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
  78 extern struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh);
  79 extern void  ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t mgt_hdr, adf_nbuf_t skb,HTC_ENDPOINT_ID EndPt);
  80 extern HAL_BOOL ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val);
  81 extern void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,  owl_txq_state_t txqstate);
  82 void owl_tgt_node_init(struct ath_node_target * an);
  83 void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf);
  84 void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host);
  85
  86 /*
  87  * Extend a 32 bit TSF to nearest 64 bit TSF value.
  88  * When the adapter is a STATION, its local TSF is periodically modified by
  89  * the hardware to match the BSS TSF (as received in beacon packets), and
  90  * rstamp may appear to be from the future or from the past (with reference
  91  * to the current local TSF) because of jitter. This is mostly noticable in
  92  * highly congested channels. The code uses signed modulo arithmetic to
  93  * handle both past/future cases and signed-extension to avoid branches.
  94  * Test cases:
  95  * extend(0x0000001200000004, 0x00000006) == 0x0000001200000006
  96  * extend(0x0000001200000004, 0x00000002) == 0x0000001200000002
  97  * extend(0x0000001200000004, 0xfffffffe) == 0x00000011fffffffe  ! tsfhigh--
  98  * extend(0x000000127ffffffe, 0x80000002) == 0x0000001280000002
  99  * extend(0x0000001280000002, 0x7ffffffe) == 0x000000127ffffffe
 100  * extend(0x00000012fffffffc, 0xfffffffe) == 0x00000012fffffffe
 101  * extend(0x00000012fffffffc, 0xfffffffa) == 0x00000012fffffffa
 102  * extend(0x00000012fffffffc, 0x00000002) == 0x0000001300000002  ! tsfhigh++
 103  */
 104 static u_int64_t ath_extend_tsf(struct ath_softc_tgt *sc, u_int32_t rstamp)
 105 {
 106         struct ath_hal *ah = sc->sc_ah;
 107         u_int64_t tsf;
 108         u_int32_t tsf_low;
 109         a_int64_t tsf_delta;  /* signed int64 */
 110
 111         tsf = ah->ah_getTsf64(ah);
 112         tsf_low = tsf & 0xffffffffUL;
 113
 114         tsf_delta = (a_int32_t)((rstamp - tsf_low) & 0xffffffffUL);
 115
 116         return (tsf + (u_int64_t)tsf_delta);
 117 }
 118
 119 static a_int32_t ath_rate_setup(struct ath_softc_tgt *sc, a_uint32_t mode)
 120 {
 121         struct ath_hal *ah = sc->sc_ah;
 122         const HAL_RATE_TABLE *rt;
 123
 124         switch (mode) {
 125         case IEEE80211_MODE_11NA:
 126                 sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NA);
 127                 break;
 128         case IEEE80211_MODE_11NG:
 129                 sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NG);
 130                 break;
 131         default:
 132                 return 0;
 133         }
 134         rt = sc->sc_rates[mode];
 135         if (rt == NULL)
 136                 return 0;
 137
 138         return 1;
 139 }
 140
 141 static void ath_setcurmode(struct ath_softc_tgt *sc,
 142                            enum ieee80211_phymode mode)
 143 {
 144         const HAL_RATE_TABLE *rt;
 145         a_int32_t i;
 146
 147         adf_os_mem_set(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
 148
 149         rt = sc->sc_rates[mode];
 150         adf_os_assert(rt != NULL);
 151
 152         for (i = 0; i < rt->rateCount; i++) {
 153                 sc->sc_rixmap[rt->info[i].rateCode] = i;
 154         }
 155
 156         sc->sc_currates = rt;
 157         sc->sc_curmode = mode;
 158         sc->sc_protrix = ((mode == IEEE80211_MODE_11NG) ? 3 : 0);
 159
 160 }
 161
 162 void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id,
 163                void *buffer, a_int32_t Length)
 164 {
 165         adf_nbuf_t netbuf = ADF_NBUF_NULL;
 166         a_uint8_t *pData;
 167
 168         netbuf = WMI_AllocEvent(handle, WMI_EVT_CLASS_CMD_EVENT,
 169                                 sizeof(WMI_CMD_HDR) + Length);
 170
 171         if (netbuf == ADF_NBUF_NULL) {
 172                 adf_os_print("Buf null\n");
 173                 return;
 174         }
 175
 176         if (buffer != NULL && Length != 0 && Length < WMI_SVC_MAX_BUFFERED_EVENT_SIZE) {
 177                 pData = adf_nbuf_put_tail(netbuf, Length);
 178                 adf_os_mem_copy(pData, buffer, Length);
 179         }
 180
 181         WMI_SendEvent(handle, netbuf, evt_id, 0, Length);
 182 }
 183
 184 void wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo,
 185                  void *buffer, a_int32_t Length)
 186 {
 187         adf_nbuf_t netbuf = ADF_NBUF_NULL;
 188         A_UINT8 *pData;
 189
 190         netbuf = WMI_AllocEvent(pContext, WMI_EVT_CLASS_CMD_REPLY,
 191                                 sizeof(WMI_CMD_HDR) + Length);
 192
 193         if (netbuf == ADF_NBUF_NULL) {
 194                 adf_os_assert(0);
 195                 return;
 196         }
 197
 198         if (Length != 0 && buffer != NULL) {
 199                 pData = (A_UINT8 *)adf_nbuf_put_tail(netbuf, Length);
 200                 adf_os_mem_copy(pData, buffer, Length);
 201         }
 202
 203         WMI_SendEvent(pContext, netbuf, cmd_id, SeqNo, Length);
 204 }
 205
 206 static void ath_node_vdelete_tgt(struct ath_softc_tgt *sc, a_uint8_t vap_index)
 207 {
 208         a_int32_t i;
 209
 210         for (i = 0; i < TARGET_NODE_MAX; i++) {
 211                 if(sc->sc_sta[i].ni.ni_vapindex == vap_index)
 212                         sc->sc_sta[i].an_valid = 0;
 213         }
 214 }
 215
 216 a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp)
 217 {
 218         if (sc->sc_curmode == IEEE80211_MODE_11NG)
 219                 return avp->av_minrateidx[0];
 220         else if (sc->sc_curmode == IEEE80211_MODE_11NA)
 221                 return avp->av_minrateidx[1];
 222
 223         return 0;
 224 }
 225
 226 /******/
 227 /* RX */
 228 /******/
 229
 230 static adf_nbuf_t ath_alloc_skb_align(struct ath_softc_tgt *sc,
 231                                       a_uint32_t size, a_uint32_t align)
 232 {
 233         adf_nbuf_t skb;
 234
 235         skb = BUF_Pool_alloc_buf_align(sc->pool_handle, POOL_ID_WLAN_RX_BUF,
 236                                        RX_HEADER_SPACE, align);
 237         return skb;
 238 }
 239
 240 static a_int32_t ath_rxdesc_init(struct ath_softc_tgt *sc, struct ath_rx_desc *ds)
 241 {
 242         struct ath_hal *ah = sc->sc_ah;
 243         struct ath_rx_desc *ds_held;
 244         a_uint8_t *anbdata;
 245         a_uint32_t anblen;
 246
 247         if (!sc->sc_rxdesc_held) {
 248                 sc->sc_rxdesc_held = ds;
 249                 return 0;
 250         }
 251
 252         ds_held = sc->sc_rxdesc_held;
 253         sc->sc_rxdesc_held = ds;
 254         ds = ds_held;
 255
 256         if (ds->ds_nbuf == ADF_NBUF_NULL) {
 257                 ds->ds_nbuf = ath_alloc_skb_align(sc, sc->sc_rxbufsize, sc->sc_cachelsz);
 258                 if (ds->ds_nbuf == ADF_NBUF_NULL) {
 259                         sc->sc_rxdesc_held = ds;
 260                         sc->sc_rx_stats.ast_rx_nobuf++;
 261                         return ENOMEM;
 262                 }
 263                 adf_nbuf_map(sc->sc_dev, ds->ds_dmap, ds->ds_nbuf, ADF_OS_DMA_FROM_DEVICE);
 264                 adf_nbuf_dmamap_info(ds->ds_dmap, &ds->ds_dmap_info);
 265                 ds->ds_data = ds->ds_dmap_info.dma_segs[0].paddr;
 266         }
 267
 268         ds->ds_link = 0;
 269         adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen);
 270
 271         ah->ah_setupRxDesc(ds, adf_nbuf_tailroom(ds->ds_nbuf), 0);
 272
 273         if (sc->sc_rxlink == NULL) {
 274                 ah->ah_setRxDP(ah, ds->ds_daddr);
 275         }
 276         else {
 277                 *sc->sc_rxlink = ds->ds_daddr;
 278         }
 279         sc->sc_rxlink = &ds->ds_link;
 280         ah->ah_enableReceive(ah);
 281
 282         return 0;
 283 }
 284
 285 static void ath_rx_complete(struct ath_softc_tgt *sc, adf_nbuf_t buf)
 286 {
 287         struct ath_rx_desc *ds;
 288         adf_nbuf_t buf_tmp;
 289         adf_nbuf_queue_t nbuf_head;
 290
 291         adf_nbuf_split_to_frag(buf, &nbuf_head);
 292         ds = asf_tailq_first(&sc->sc_rxdesc_idle);
 293
 294         while (ds) {
 295                 struct ath_rx_desc *ds_tmp;
 296                 buf_tmp = adf_nbuf_queue_remove(&nbuf_head);
 297
 298                 if (buf_tmp == NULL) {
 299                         break;
 300                 }
 301
 302                 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, buf_tmp);
 303
 304                 ds_tmp = ds;
 305                 ds = asf_tailq_next(ds, ds_list);
 306
 307                 ath_rxdesc_init(sc, ds_tmp);
 308
 309                 asf_tailq_remove(&sc->sc_rxdesc_idle, ds_tmp, ds_list);
 310                 asf_tailq_insert_tail(&sc->sc_rxdesc, ds_tmp, ds_list);
 311         }
 312 }
 313
 314 static void tgt_HTCSendCompleteHandler(HTC_ENDPOINT_ID Endpt, adf_nbuf_t buf, void *ServiceCtx)
 315 {
 316         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 317
 318         if (Endpt == RX_ENDPOINT_ID) {
 319                 sc->sc_rx_stats.ast_rx_done++;
 320                 ath_rx_complete(sc, buf);
 321         }
 322 }
 323
 324 static void ath_uapsd_processtriggers(struct ath_softc_tgt *sc)
 325 {
 326         struct ath_hal *ah = sc->sc_ah;
 327         struct ath_rx_buf *bf = NULL;
 328         struct ath_rx_desc *ds, *ds_head, *ds_tail, *ds_tmp;
 329         a_int32_t retval;
 330         a_uint32_t cnt = 0;
 331         a_uint16_t frame_len = 0;
 332
 333 #define PA2DESC(_sc, _pa)                                               \
 334         ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc +         \
 335                              ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
 336
 337         bf = asf_tailq_first(&sc->sc_rxbuf);
 338
 339         ds = asf_tailq_first(&sc->sc_rxdesc);
 340         ds_head = ds;
 341
 342         while(ds) {
 343                 ++cnt;
 344
 345                 if (cnt == ath_numrxbufs - 1) {
 346                         adf_os_print("VERY LONG PACKET!!!!!\n");
 347                         ds_tail = ds;
 348                         ds_tmp = ds_head;
 349                         while (ds_tmp) {
 350                                 struct ath_rx_desc *ds_rmv;
 351                                 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
 352                                 ds_rmv = ds_tmp;
 353                                 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
 354
 355                                 if (ds_tmp == NULL) {
 356                                         adf_os_print("ds_tmp is NULL\n");
 357                                         adf_os_assert(0);
 358                                 }
 359
 360                                 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ds_rmv->ds_nbuf);
 361                                 ds_rmv->ds_nbuf = ADF_NBUF_NULL;
 362
 363                                 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
 364                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 365                                         asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
 366                                 }
 367                                 else {
 368                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 369                                         asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
 370                                 }
 371
 372                                 if (ds_rmv == ds_tail) {
 373                                         break;
 374                                 }
 375                         }
 376                         break;
 377                 }
 378
 379                 if (ds->ds_link == 0) {
 380                         break;
 381                 }
 382
 383                 if (bf->bf_status & ATH_BUFSTATUS_DONE) {
 384                         continue;
 385                 }
 386
 387                 retval = ah->ah_procRxDescFast(ah, ds, ds->ds_daddr,
 388                                                 PA2DESC(sc, ds->ds_link), &bf->bf_rx_status);
 389                 if (HAL_EINPROGRESS == retval) {
 390                         break;
 391                 }
 392
 393                 if (adf_nbuf_len(ds->ds_nbuf) == 0) {
 394                         adf_nbuf_put_tail(ds->ds_nbuf, bf->bf_rx_status.rs_datalen);
 395                 }
 396
 397                 frame_len += bf->bf_rx_status.rs_datalen;
 398
 399                 if (bf->bf_rx_status.rs_more == 0) {
 400                         adf_nbuf_queue_t nbuf_head;
 401                         adf_nbuf_queue_init(&nbuf_head);
 402
 403                         cnt = 0;
 404
 405                         ds_tail = ds;
 406                         ds = asf_tailq_next(ds, ds_list);
 407
 408                         ds_tmp = ds_head;
 409                         ds_head = asf_tailq_next(ds_tail, ds_list);
 410
 411                         while (ds_tmp) {
 412                                 struct ath_rx_desc *ds_rmv;
 413
 414                                 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
 415                                 adf_nbuf_queue_add(&nbuf_head, ds_tmp->ds_nbuf);
 416                                 ds_tmp->ds_nbuf = ADF_NBUF_NULL;
 417
 418                                 ds_rmv = ds_tmp;
 419                                 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
 420                                 if (ds_tmp == NULL) {
 421                                         adf_os_assert(0);
 422                                 }
 423
 424                                 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
 425                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 426                                         asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
 427                                 }  else {
 428                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 429                                         asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
 430                                 }
 431
 432                                 if (ds_rmv == ds_tail) {
 433                                         break;
 434                                 }
 435                         }
 436
 437
 438                         bf->bf_rx_status.rs_datalen = frame_len;
 439                         frame_len = 0;
 440
 441                         bf->bf_skb = adf_nbuf_create_frm_frag(&nbuf_head);
 442
 443                         bf->bf_status |= ATH_BUFSTATUS_DONE;
 444
 445                         bf = (struct ath_rx_buf *)asf_tailq_next(bf, bf_list);
 446                 }
 447                 else {
 448                         ds = asf_tailq_next(ds, ds_list);
 449                 }
 450         }
 451
 452 #undef PA2DESC
 453 }
 454
 455 static a_int32_t ath_startrecv(struct ath_softc_tgt *sc)
 456 {
 457         struct ath_hal *ah = sc->sc_ah;
 458         struct ath_rx_desc *ds;
 459
 460         sc->sc_rxbufsize = 1024+512+128;
 461         sc->sc_rxlink = NULL;
 462
 463         sc->sc_rxdesc_held = NULL;
 464
 465         asf_tailq_foreach(ds, &sc->sc_rxdesc, ds_list) {
 466                 a_int32_t error = ath_rxdesc_init(sc, ds);
 467                 if (error != 0) {
 468                         return error;
 469                 }
 470         }
 471
 472         ds = asf_tailq_first(&sc->sc_rxdesc);
 473         ah->ah_setRxDP(ah, ds->ds_daddr);
 474
 475         return 0;
 476 }
 477
 478 static void ath_tgt_rx_tasklet(TQUEUE_ARG data)
 479 {
 480         struct ath_softc_tgt *sc  = (struct ath_softc_tgt *)data;
 481         struct ath_rx_buf *bf = NULL;
 482         struct ath_hal *ah = sc->sc_ah;
 483         struct rx_frame_header *rxhdr;
 484         struct ath_rx_status *rxstats;
 485         adf_nbuf_t skb = ADF_NBUF_NULL;
 486
 487         do {
 488                 bf = asf_tailq_first(&sc->sc_rxbuf);
 489                 if (bf == NULL) {
 490                         break;
 491                 }
 492
 493                 if (!(bf->bf_status & ATH_BUFSTATUS_DONE)) {
 494                         break;
 495                 }
 496
 497                 skb = bf->bf_skb;
 498                 if (skb == NULL) {
 499                         continue;
 500                 }
 501
 502                 asf_tailq_remove(&sc->sc_rxbuf, bf, bf_list);
 503
 504                 bf->bf_skb = NULL;
 505
 506                 rxhdr = (struct rx_frame_header *)adf_nbuf_push_head(skb,
 507                                                      sizeof(struct rx_frame_header));
 508                 rxstats = (struct ath_rx_status *)(&rxhdr->rx_stats[0]);
 509                 adf_os_mem_copy(rxstats, &(bf->bf_rx_status),
 510                                 sizeof(struct ath_rx_status));
 511
 512                 rxstats->rs_tstamp = ath_extend_tsf(sc, (u_int32_t)rxstats->rs_tstamp);
 513
 514                 HTC_SendMsg(sc->tgt_htc_handle, RX_ENDPOINT_ID, skb);
 515                 sc->sc_rx_stats.ast_rx_send++;
 516
 517                 bf->bf_status &= ~ATH_BUFSTATUS_DONE;
 518                 asf_tailq_insert_tail(&sc->sc_rxbuf, bf, bf_list);
 519
 520         } while(1);
 521
 522         sc->sc_imask |= HAL_INT_RX;
 523         ah->ah_setInterrupts(ah, sc->sc_imask);
 524 }
 525
 526 /*******************/
 527 /* Beacon Handling */
 528 /*******************/
 529
 530 /*
 531  * Setup the beacon frame for transmit.
 532  * FIXME: Short Preamble.
 533  */
 534 static void ath_beacon_setup(struct ath_softc_tgt *sc,
 535                              struct ath_tx_buf *bf,
 536                              struct ath_vap_target *avp)
 537 {
 538         adf_nbuf_t skb = bf->bf_skb;
 539         struct ath_hal *ah = sc->sc_ah;
 540         struct ath_tx_desc *ds;
 541         a_int32_t flags;
 542         const HAL_RATE_TABLE *rt;
 543         a_uint8_t rix, rate;
 544         HAL_11N_RATE_SERIES series[4] = {{ 0 }};
 545
 546         flags = HAL_TXDESC_NOACK;
 547
 548         ds = bf->bf_desc;
 549         ds->ds_link = 0;
 550         ds->ds_data = bf->bf_dmamap_info.dma_segs[0].paddr;
 551
 552         rix = ath_get_minrateidx(sc, avp);
 553         rt  = sc->sc_currates;
 554         rate = rt->info[rix].rateCode;
 555
 556         ah->ah_setupTxDesc(ds
 557                             , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
 558                             , sizeof(struct ieee80211_frame)
 559                             , HAL_PKT_TYPE_BEACON
 560                             , MAX_RATE_POWER
 561                             , rate, 1
 562                             , HAL_TXKEYIX_INVALID
 563                             , flags
 564                             , 0
 565                             , 0);
 566
 567         ah->ah_fillTxDesc(ds
 568                            , asf_roundup(adf_nbuf_len(skb), 4)
 569                            , AH_TRUE
 570                            , AH_TRUE
 571                            , ds);
 572
 573         series[0].Tries = 1;
 574         series[0].Rate = rate;
 575         series[0].ChSel = sc->sc_ic.ic_tx_chainmask;
 576         series[0].RateFlags = 0;
 577         ah->ah_set11nRateScenario(ds, 0, 0, series, 4, 0);
 578 }
 579
 580 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr,
 581                                 adf_nbuf_t nbuf, HTC_ENDPOINT_ID EndPt)
 582 {
 583         struct ath_hal *ah = sc->sc_ah;
 584         struct ath_tx_buf *bf;
 585         a_uint8_t vap_index, *anbdata;
 586         ath_beacon_hdr_t *bhdr = NULL;
 587         a_uint32_t anblen;
 588
 589         if (!bc_hdr) {
 590                 adf_nbuf_peek_header(nbuf, &anbdata, &anblen);
 591                 bhdr = (ath_beacon_hdr_t *)anbdata;
 592         } else {
 593                 adf_os_print("found bc_hdr! 0x%x\n", bc_hdr);
 594                 adf_os_assert(0);
 595         }
 596
 597         vap_index = bhdr->vap_index;
 598         adf_os_assert(vap_index < TARGET_VAP_MAX);
 599
 600         adf_nbuf_pull_head(nbuf, sizeof(ath_beacon_hdr_t));
 601
 602         bf = sc->sc_vap[vap_index].av_bcbuf;
 603         adf_os_assert(bf);
 604         bf->bf_endpt = EndPt;
 605
 606         if (bf->bf_skb) {
 607                 adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
 608                 adf_nbuf_push_head(bf->bf_skb, sizeof(ath_beacon_hdr_t));
 609                 ath_free_tx_skb(sc->tgt_htc_handle, bf->bf_endpt, bf->bf_skb);
 610         }
 611
 612         bf->bf_skb = nbuf;
 613
 614         adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, nbuf, ADF_OS_DMA_TO_DEVICE);
 615         adf_nbuf_dmamap_info(bf->bf_dmamap,&bf->bf_dmamap_info);
 616
 617         ath_beacon_setup(sc, bf, &sc->sc_vap[vap_index]);
 618         ah->ah_stopTxDma(ah, sc->sc_bhalq);
 619         ah->ah_setTxDP(ah, sc->sc_bhalq, ATH_BUF_GET_DESC_PHY_ADDR(bf));
 620         ah->ah_startTxDma(ah, sc->sc_bhalq);
 621 }
 622
 623 /******/
 624 /* TX */
 625 /******/
 626
 627 static void ath_tx_stopdma(struct ath_softc_tgt *sc, struct ath_txq *txq)
 628 {
 629         struct ath_hal *ah = sc->sc_ah;
 630
 631         ah->ah_stopTxDma(ah, txq->axq_qnum);
 632 }
 633
 634 static void owltgt_txq_drain(struct ath_softc_tgt *sc, struct ath_txq *txq)
 635 {
 636         owltgt_tx_processq(sc, txq, OWL_TXQ_STOPPED);
 637 }
 638
 639 static void ath_tx_draintxq(struct ath_softc_tgt *sc, struct ath_txq *txq)
 640 {
 641         owltgt_txq_drain(sc, txq);
 642 }
 643
 644 static void ath_draintxq(struct ath_softc_tgt *sc, HAL_BOOL drain_softq)
 645 {
 646         struct ath_hal *ah = sc->sc_ah;
 647         a_uint16_t i;
 648         struct ath_txq *txq = NULL;
 649         struct ath_atx_tid *tid = NULL;
 650
 651         ath_tx_status_clear(sc);
 652         sc->sc_tx_draining = 1;
 653
 654         ah->ah_stopTxDma(ah, sc->sc_bhalq);
 655
 656         for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
 657                 if (ATH_TXQ_SETUP(sc, i))
 658                         ath_tx_stopdma(sc, ATH_TXQ(sc, i));
 659
 660         for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
 661                 if (ATH_TXQ_SETUP(sc, i)) {
 662                         owltgt_tx_processq(sc, ATH_TXQ(sc,i), OWL_TXQ_STOPPED);
 663
 664                         txq = ATH_TXQ(sc,i);
 665                         while (!asf_tailq_empty(&txq->axq_tidq)){
 666                                 TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem);
 667                                 if(tid == NULL)
 668                                         break;
 669                                 tid->sched = AH_FALSE;
 670                                 ath_tgt_tid_drain(sc,tid);
 671                         }
 672                 }
 673
 674         sc->sc_tx_draining = 0;
 675 }
 676
 677 static void ath_tgt_txq_setup(struct ath_softc_tgt *sc)
 678 {
 679         a_int32_t qnum;
 680         struct ath_txq *txq;
 681
 682         sc->sc_txqsetup=0;
 683
 684         for (qnum=0;qnum<HAL_NUM_TX_QUEUES;qnum++) {
 685                 txq= &sc->sc_txq[qnum];
 686                 txq->axq_qnum = qnum;
 687                 txq->axq_link = NULL;
 688                 asf_tailq_init(&txq->axq_q);
 689                 txq->axq_depth = 0;
 690                 txq->axq_linkbuf = NULL;
 691                 asf_tailq_init(&txq->axq_tidq);
 692                 sc->sc_txqsetup |= 1<<qnum;
 693         }
 694
 695         sc->sc_uapsdq  = &sc->sc_txq[UAPSDQ_NUM];
 696         sc->sc_cabq    = &sc->sc_txq[CABQ_NUM];
 697
 698         sc->sc_ac2q[WME_AC_BE]  = &sc->sc_txq[0];
 699         sc->sc_ac2q[WME_AC_BK]  = &sc->sc_txq[1];
 700         sc->sc_ac2q[WME_AC_VI]  = &sc->sc_txq[2];
 701         sc->sc_ac2q[WME_AC_VO]  = &sc->sc_txq[3];
 702
 703         return;
 704 #undef N
 705 }
 706
 707 static void tgt_HTCRecv_beaconhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 708                                       adf_nbuf_t buf, void *ServiceCtx)
 709 {
 710         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 711
 712         ath_tgt_send_beacon(sc, hdr_buf, buf, EndPt);
 713 }
 714
 715 static void tgt_HTCRecv_uapsdhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 716                                      adf_nbuf_t buf, void *ServiceCtx)
 717 {
 718 }
 719
 720 static void tgt_HTCRecv_mgmthandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 721                                     adf_nbuf_t buf, void *ServiceCtx)
 722 {
 723         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 724
 725         ath_tgt_send_mgt(sc,hdr_buf,buf,EndPt);
 726 }
 727
 728 static void tgt_HTCRecvMessageHandler(HTC_ENDPOINT_ID EndPt,
 729                                       adf_nbuf_t hdr_buf, adf_nbuf_t buf,
 730                                       void *ServiceCtx)
 731 {
 732         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 733         struct ath_tx_buf *bf;
 734         a_uint8_t *data;
 735         a_uint32_t len;
 736         ath_data_hdr_t *dh;
 737         struct ath_node_target *an;
 738         struct ath_atx_tid *tid;
 739
 740         if (!hdr_buf) {
 741                 adf_nbuf_peek_header(buf, &data, &len);
 742                 adf_nbuf_pull_head(buf, sizeof(ath_data_hdr_t));
 743         } else {
 744                 adf_nbuf_peek_header(hdr_buf, &data, &len);
 745         }
 746
 747         adf_os_assert(len >= sizeof(ath_data_hdr_t));
 748         dh = (ath_data_hdr_t *)data;
 749
 750         an = &sc->sc_sta[dh->ni_index];
 751         tid = ATH_AN_2_TID(an, dh->tidno);
 752
 753         sc->sc_tx_stats.tx_tgt++;
 754
 755         bf = ath_tgt_tx_prepare(sc, buf, dh);
 756         if (!bf) {
 757                 ath_free_tx_skb(sc->tgt_htc_handle,EndPt,buf);
 758                 return;
 759         }
 760
 761         bf->bf_endpt = EndPt;
 762         bf->bf_cookie = dh->cookie;
 763         bf->vap_index = dh->vap_index;
 764
 765         if (tid->flag & TID_AGGR_ENABLED)
 766                 ath_tgt_handle_aggr(sc, bf);
 767         else
 768                 ath_tgt_handle_normal(sc, bf);
 769 }
 770
 771 static void tgt_HTCRecv_cabhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 772                                    adf_nbuf_t buf, void *ServiceCtx)
 773 {
 774         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 775         struct ath_hal *ah = sc->sc_ah;
 776         a_uint64_t tsf;
 777         a_uint32_t tmp;
 778
 779 #ifdef ATH_ENABLE_CABQ
 780         tsf = ah->ah_getTsf64(ah);
 781         tmp = tsf - sc->sc_swba_tsf;
 782
 783         if ( tmp > ATH_CABQ_HANDLING_THRESHOLD ) {
 784                 HTC_ReturnBuffers(sc->tgt_htc_handle, EndPt, buf);
 785                 return;
 786         }
 787
 788         tgt_HTCRecvMessageHandler(EndPt, hdr_buf, buf, ServiceCtx);
 789 #endif
 790 }
 791
 792 /***********************/
 793 /* Descriptor Handling */
 794 /***********************/
 795
 796 static a_int32_t ath_descdma_setup(struct ath_softc_tgt *sc,
 797                                    struct ath_descdma *dd, ath_bufhead *head,
 798                                    const char *name, a_int32_t nbuf, a_int32_t ndesc,
 799                                    a_uint32_t bfSize, a_uint32_t descSize)
 800 {
 801 #define DS2PHYS(_dd, _ds)                                               \
 802         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
 803
 804         struct ath_desc *ds;
 805         struct ath_buf *bf;
 806         a_int32_t i, bsize, error;
 807         a_uint8_t *bf_addr;
 808         a_uint8_t *ds_addr;
 809
 810         dd->dd_name = name;
 811         dd->dd_desc_len = descSize * nbuf * ndesc;
 812
 813         dd->dd_desc = adf_os_dmamem_alloc(sc->sc_dev,
 814                                   dd->dd_desc_len, 1, &dd->dd_desc_dmamap);
 815         dd->dd_desc_paddr = adf_os_dmamem_map2addr(dd->dd_desc_dmamap);
 816         if (dd->dd_desc == NULL) {
 817                 error = -ENOMEM;
 818                 goto fail;
 819         }
 820         ds = dd->dd_desc;
 821
 822         bsize = bfSize * nbuf;
 823         bf = adf_os_mem_alloc(bsize);
 824         if (bf == NULL) {
 825                 error = -ENOMEM;
 826                 goto fail2;
 827         }
 828         adf_os_mem_set(bf, 0, bsize);
 829         dd->dd_bufptr = bf;
 830
 831         bf_addr = (a_uint8_t *)bf;
 832         ds_addr = (a_uint8_t *)ds;
 833
 834         asf_tailq_init(head);
 835
 836         for (i = 0; i < nbuf; i++) {
 837                 a_int32_t j;
 838
 839                 if (adf_nbuf_dmamap_create( sc->sc_dev, &bf->bf_dmamap) != A_STATUS_OK) {
 840                         goto fail2;
 841                 }
 842
 843                 bf->bf_desc = bf->bf_descarr = bf->bf_lastds = ds;
 844                 for (j = 0; j < ndesc; j++)
 845                         ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, j, (ds_addr + (j*descSize)));
 846
 847                 ATH_BUF_SET_DESC_PHY_ADDR(bf, ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, 0));
 848
 849                 adf_nbuf_queue_init(&bf->bf_skbhead);
 850                 asf_tailq_insert_tail(head, bf, bf_list);
 851
 852                 bf_addr += bfSize;
 853                 ds_addr += (ndesc * descSize);
 854                 bf = (struct ath_buf *)bf_addr;
 855                 ds = (struct ath_desc *)ds_addr;
 856         }
 857
 858         return 0;
 859 fail2:
 860         adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
 861                            1, dd->dd_desc, dd->dd_desc_dmamap);
 862 fail:
 863         adf_os_mem_set(dd, 0, sizeof(*dd));
 864         adf_os_assert(0);
 865         return error;
 866
 867 #undef DS2PHYS
 868 }
 869
 870 static void ath_descdma_cleanup(struct ath_softc_tgt *sc,
 871                                 struct ath_descdma *dd,
 872                                 ath_bufhead *head, a_int32_t dir)
 873 {
 874         struct ath_buf *bf;
 875
 876         asf_tailq_foreach(bf, head, bf_list) {
 877                 if (adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
 878                         adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, dir);
 879                         while(adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
 880                                 ath_free_rx_skb(sc,
 881                                         adf_nbuf_queue_remove(&bf->bf_skbhead));
 882                         }
 883                         bf->bf_skb = NULL;
 884                 } else if (bf->bf_skb != NULL) {
 885                         adf_nbuf_unmap(sc->sc_dev,bf->bf_dmamap, dir);
 886                         ath_free_rx_skb(sc, bf->bf_skb);
 887                         bf->bf_skb = NULL;
 888                 }
 889
 890                 adf_nbuf_dmamap_destroy(sc->sc_dev, bf->bf_dmamap);
 891
 892                 bf->bf_node = NULL;
 893         }
 894
 895         adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
 896                            1, dd->dd_desc, dd->dd_desc_dmamap);
 897
 898         asf_tailq_init(head);
 899         adf_os_mem_free(dd->dd_bufptr);
 900         adf_os_mem_set(dd, 0, sizeof(*dd));
 901 }
 902
 903 static a_int32_t ath_desc_alloc(struct ath_softc_tgt *sc)
 904 {
 905 #define DS2PHYS(_dd, _ds)                                               \
 906         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
 907
 908         a_int32_t error;
 909         struct ath_tx_buf *bf;
 910
 911         if(ath_numrxbufs == -1)
 912                 ath_numrxbufs = ATH_RXBUF;
 913
 914         if (ath_numrxdescs == -1)
 915                 ath_numrxdescs = ATH_RXDESC;
 916
 917         error = ath_descdma_setup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 918                                   "rx", ath_numrxdescs, 1,
 919                                   sizeof(struct ath_rx_buf),
 920                                   sizeof(struct ath_rx_desc));
 921         if (error != 0)
 922                 return error;
 923
 924         a_uint32_t i;
 925         struct ath_descdma *dd = &sc->sc_rxdma;
 926         struct ath_rx_desc *ds = (struct ath_rx_desc *)dd->dd_desc;
 927         struct ath_rx_desc *ds_prev = NULL;
 928
 929         asf_tailq_init(&sc->sc_rxdesc);
 930         asf_tailq_init(&sc->sc_rxdesc_idle);
 931
 932         for (i = 0; i < ath_numrxdescs; i++, ds++) {
 933
 934                 if (ds->ds_nbuf != ADF_NBUF_NULL) {
 935                         ds->ds_nbuf = ADF_NBUF_NULL;
 936                 }
 937
 938                 if (adf_nbuf_dmamap_create(sc->sc_dev, &ds->ds_dmap) != A_STATUS_OK) {
 939                         adf_os_assert(0);
 940                 }
 941
 942                 ds->ds_daddr = DS2PHYS(&sc->sc_rxdma, ds);
 943
 944                 if (ds_prev) {
 945                         ds_prev->ds_link = ds->ds_daddr;
 946                 }
 947
 948                 ds->ds_link = 0;
 949                 ds_prev = ds;
 950
 951                 asf_tailq_insert_tail(&sc->sc_rxdesc, ds, ds_list);
 952         }
 953
 954         error = ath_descdma_setup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
 955                                   "tx", ATH_TXBUF + 1, ATH_TXDESC,
 956                                   sizeof(struct ath_tx_buf),
 957                                   sizeof(struct ath_tx_desc));
 958         if (error != 0) {
 959                 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 960                                     ADF_OS_DMA_FROM_DEVICE);
 961                 return error;
 962         }
 963
 964         error = ath_descdma_setup(sc, &sc->sc_bdma, (ath_bufhead *)&sc->sc_bbuf,
 965                                   "beacon", ATH_BCBUF, 1,
 966                                   sizeof(struct ath_tx_buf),
 967                                   sizeof(struct ath_tx_desc));
 968         if (error != 0) {
 969                 ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
 970                                     ADF_OS_DMA_TO_DEVICE);
 971                 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 972                                     ADF_OS_DMA_FROM_DEVICE);
 973                 return error;
 974         }
 975
 976         bf = asf_tailq_first(&sc->sc_txbuf);
 977         bf->bf_isaggr = bf->bf_isretried = bf->bf_retries = 0;
 978         asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
 979
 980         sc->sc_txbuf_held = bf;
 981
 982         return 0;
 983
 984 #undef DS2PHYS
 985 }
 986
 987 static void ath_desc_free(struct ath_softc_tgt *sc)
 988 {
 989         asf_tailq_insert_tail(&sc->sc_txbuf, sc->sc_txbuf_held, bf_list);
 990
 991         sc->sc_txbuf_held = NULL;
 992
 993         if (sc->sc_txdma.dd_desc_len != 0)
 994                 ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
 995                                     ADF_OS_DMA_TO_DEVICE);
 996         if (sc->sc_rxdma.dd_desc_len != 0)
 997                 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 998                                     ADF_OS_DMA_FROM_DEVICE);
 999 }
1000
1001 /**********************/
1002 /* Interrupt Handling */
1003 /**********************/
1004
1005 adf_os_irq_resp_t ath_intr(adf_drv_handle_t hdl)
1006 {
1007         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)hdl;
1008         struct ath_hal *ah = sc->sc_ah;
1009         HAL_INT status;
1010
1011         if (sc->sc_invalid)
1012                 return ADF_OS_IRQ_NONE;
1013
1014         if (!ah->ah_isInterruptPending(ah))
1015                 return ADF_OS_IRQ_NONE;
1016
1017         ah->ah_getPendingInterrupts(ah, &status);
1018
1019         status &= sc->sc_imask;
1020
1021         if (status & HAL_INT_FATAL) {
1022                 ah->ah_setInterrupts(ah, 0);
1023                 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_fataltq);
1024         } else {
1025                 if (status & HAL_INT_SWBA) {
1026                         WMI_SWBA_EVENT swbaEvt;
1027                         struct ath_txq *txq = ATH_TXQ(sc, 8);
1028
1029                         swbaEvt.tsf = ah->ah_getTsf64(ah);
1030                         swbaEvt.beaconPendingCount = ah->ah_numTxPending(ah, sc->sc_bhalq);
1031                         sc->sc_swba_tsf = ah->ah_getTsf64(ah);
1032
1033                         wmi_event(sc->tgt_wmi_handle,
1034                                   WMI_SWBA_EVENTID,
1035                                   &swbaEvt,
1036                                   sizeof(WMI_SWBA_EVENT));
1037
1038                         ath_tx_draintxq(sc, txq);
1039                 }
1040
1041                 if (status & HAL_INT_RXORN)
1042                         sc->sc_int_stats.ast_rxorn++;
1043
1044                 if (status & HAL_INT_RXEOL)
1045                         sc->sc_int_stats.ast_rxeol++;
1046
1047                 if (status & (HAL_INT_RX | HAL_INT_RXEOL | HAL_INT_RXORN)) {
1048                         if (status & HAL_INT_RX)
1049                                 sc->sc_int_stats.ast_rx++;
1050
1051                         ath_uapsd_processtriggers(sc);
1052
1053                         sc->sc_imask &= ~HAL_INT_RX;
1054                         ah->ah_setInterrupts(ah, sc->sc_imask);
1055
1056                         ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_rxtq);
1057                 }
1058
1059                 if (status & HAL_INT_TXURN) {
1060                         sc->sc_int_stats.ast_txurn++;
1061                         ah->ah_updateTxTrigLevel(ah, AH_TRUE);
1062                 }
1063
1064                 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_txtq);
1065
1066                 if (status & HAL_INT_BMISS) {
1067                         ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_bmisstq);
1068                 }
1069
1070                 if (status & HAL_INT_GTT)
1071                         sc->sc_int_stats.ast_txto++;
1072
1073                 if (status & HAL_INT_CST)
1074                         sc->sc_int_stats.ast_cst++;
1075         }
1076
1077         return ADF_OS_IRQ_HANDLED;
1078 }
1079
1080 static void ath_fatal_tasklet(TQUEUE_ARG data )
1081 {
1082         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1083
1084         wmi_event(sc->tgt_wmi_handle, WMI_FATAL_EVENTID, NULL, 0);
1085 }
1086
1087 static void ath_bmiss_tasklet(TQUEUE_ARG data)
1088 {
1089         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1090
1091         wmi_event(sc->tgt_wmi_handle, WMI_BMISS_EVENTID, NULL, 0);
1092 }
1093
1094 /****************/
1095 /* WMI Commands */
1096 /****************/
1097
1098 static void ath_enable_intr_tgt(void *Context, A_UINT16 Command,
1099                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1100 {
1101         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1102         struct ath_hal *ah = sc->sc_ah;
1103         a_uint32_t intr = 0;
1104
1105         if (datalen == 4)
1106                 intr = (*(a_uint32_t *)data);
1107
1108         intr = adf_os_ntohl(intr);
1109
1110         if (intr & HAL_INT_SWBA) {
1111                 sc->sc_imask |= HAL_INT_SWBA;
1112         } else {
1113                 sc->sc_imask &= ~HAL_INT_SWBA;
1114         }
1115
1116         if (intr & HAL_INT_BMISS) {
1117                 sc->sc_imask |= HAL_INT_BMISS;
1118         }
1119
1120         ah->ah_setInterrupts(ah, sc->sc_imask);
1121         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1122 }
1123
1124 static void ath_init_tgt(void *Context, A_UINT16 Command,
1125                          A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1126 {
1127         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1128         struct ath_hal *ah = sc->sc_ah;
1129
1130         sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1131                 | HAL_INT_RXEOL | HAL_INT_RXORN
1132                 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1133
1134         sc->sc_imask |= HAL_INT_GTT;
1135
1136         if (ath_hal_getcapability(ah, HAL_CAP_HT))
1137                 sc->sc_imask |= HAL_INT_CST;
1138
1139         adf_os_setup_intr(sc->sc_dev, ath_intr);
1140         ah->ah_setInterrupts(ah, sc->sc_imask);
1141
1142         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1143 }
1144
1145 static void ath_int_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1146                               A_UINT8 *data, a_int32_t datalen)
1147 {
1148         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1149
1150         struct fusion_stats {
1151                 a_uint32_t ast_rx;
1152                 a_uint32_t ast_rxorn;
1153                 a_uint32_t ast_rxeol;
1154                 a_uint32_t ast_txurn;
1155                 a_uint32_t ast_txto;
1156                 a_uint32_t ast_cst;
1157         };
1158
1159         struct fusion_stats stats;
1160
1161         stats.ast_rx = sc->sc_int_stats.ast_rx;
1162         stats.ast_rxorn = sc->sc_int_stats.ast_rxorn;
1163         stats.ast_rxeol = sc->sc_int_stats.ast_rxeol;
1164         stats.ast_txurn = sc->sc_int_stats.ast_txurn;
1165         stats.ast_txto = sc->sc_int_stats.ast_txto;
1166         stats.ast_cst = sc->sc_int_stats.ast_cst;
1167
1168         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1169 }
1170
1171 static void ath_tx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1172                              A_UINT8 *data, a_int32_t datalen)
1173 {
1174         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1175
1176         struct fusion_stats {
1177                 a_uint32_t   ast_tx_xretries;
1178                 a_uint32_t   ast_tx_fifoerr;
1179                 a_uint32_t   ast_tx_filtered;
1180                 a_uint32_t   ast_tx_timer_exp;
1181                 a_uint32_t   ast_tx_shortretry;
1182                 a_uint32_t   ast_tx_longretry;
1183
1184                 a_uint32_t   tx_qnull;
1185                 a_uint32_t   tx_noskbs;
1186                 a_uint32_t   tx_nobufs;
1187         };
1188
1189         struct fusion_stats stats;
1190
1191         stats.ast_tx_xretries = sc->sc_tx_stats.ast_tx_xretries;
1192         stats.ast_tx_fifoerr = sc->sc_tx_stats.ast_tx_fifoerr;
1193         stats.ast_tx_filtered = sc->sc_tx_stats.ast_tx_filtered;
1194         stats.ast_tx_timer_exp = sc->sc_tx_stats.ast_tx_timer_exp;
1195         stats.ast_tx_shortretry = sc->sc_tx_stats.ast_tx_shortretry;
1196         stats.ast_tx_longretry = sc->sc_tx_stats.ast_tx_longretry;
1197         stats.tx_qnull = sc->sc_tx_stats.tx_qnull;
1198         stats.tx_noskbs = sc->sc_tx_stats.tx_noskbs;
1199         stats.tx_nobufs = sc->sc_tx_stats.tx_nobufs;
1200
1201         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1202 }
1203
1204 static void ath_rx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1205                              A_UINT8 *data, a_int32_t datalen)
1206 {
1207         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1208
1209         struct fusion_stats {
1210                 a_uint32_t   ast_rx_nobuf;
1211                 a_uint32_t   ast_rx_send;
1212                 a_uint32_t   ast_rx_done;
1213         };
1214
1215         struct fusion_stats stats;
1216
1217         stats.ast_rx_nobuf = sc->sc_rx_stats.ast_rx_nobuf;
1218         stats.ast_rx_send = sc->sc_rx_stats.ast_rx_send;
1219         stats.ast_rx_done = sc->sc_rx_stats.ast_rx_done;
1220
1221         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1222 }
1223
1224 static void ath_get_tgt_version(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1225                                 A_UINT8 *data, a_int32_t datalen)
1226 {
1227         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1228         struct wmi_fw_version ver;
1229
1230         ver.major = ATH_VERSION_MAJOR;
1231         ver.minor = ATH_VERSION_MINOR;
1232
1233         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &ver, sizeof(ver));
1234 }
1235
1236 static void ath_enable_aggr_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1237                                 A_UINT8 *data, a_int32_t datalen)
1238 {
1239         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1240         struct ath_aggr_info *aggr = (struct ath_aggr_info *)data;
1241         a_uint8_t nodeindex = aggr->nodeindex;
1242         a_uint8_t tidno = aggr->tidno;
1243         struct ath_node_target *an = NULL ;
1244         struct ath_atx_tid  *tid = NULL;
1245
1246         if (nodeindex >= TARGET_NODE_MAX) {
1247                 goto done;
1248         }
1249
1250         an = &sc->sc_sta[nodeindex];
1251         if (!an->an_valid) {
1252                 goto done;
1253         }
1254
1255         if (tidno >= WME_NUM_TID) {
1256                 adf_os_print("[%s] enable_aggr with invalid tid %d(node = %d)\n",
1257                              __FUNCTION__, tidno, nodeindex);
1258                 goto done;
1259         }
1260
1261         tid = ATH_AN_2_TID(an, tidno);
1262
1263         if (aggr->aggr_enable) {
1264                 tid->flag |= TID_AGGR_ENABLED;
1265         } else if ( tid->flag & TID_AGGR_ENABLED ) {
1266                 tid->flag &= ~TID_AGGR_ENABLED;
1267                 ath_tgt_tx_cleanup(sc, an, tid, 1);
1268         }
1269 done:
1270         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1271 }
1272
1273 static void ath_ic_update_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1274                               A_UINT8 *data, a_int32_t datalen)
1275 {
1276         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1277         struct ieee80211com_target *ic = (struct ieee80211com_target * )data;
1278         struct ieee80211com_target *ictgt = &sc->sc_ic ;
1279
1280         adf_os_mem_copy(ictgt, ic, sizeof(struct  ieee80211com_target));
1281
1282         ictgt->ic_ampdu_limit         = adf_os_ntohl(ic->ic_ampdu_limit);
1283
1284         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1285 }
1286
1287 static void ath_vap_create_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1288                                A_UINT8 *data, a_int32_t datalen)
1289 {
1290         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1291         struct ieee80211vap_target *vap;
1292         a_uint8_t vap_index;
1293
1294         vap = (struct ieee80211vap_target *)data;
1295
1296         vap->iv_rtsthreshold    = adf_os_ntohs(vap->iv_rtsthreshold);
1297         vap->iv_opmode          = adf_os_ntohl(vap->iv_opmode);
1298
1299         vap_index = vap->iv_vapindex;
1300
1301         adf_os_assert(sc->sc_vap[vap_index].av_valid == 0);
1302
1303         adf_os_mem_copy(&(sc->sc_vap[vap_index].av_vap), vap,
1304                         VAP_TARGET_SIZE);
1305
1306         sc->sc_vap[vap_index].av_bcbuf = asf_tailq_first(&(sc->sc_bbuf));
1307         sc->sc_vap[vap_index].av_valid = 1;
1308
1309         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1310 }
1311
1312 static void ath_node_create_tgt(void *Context, A_UINT16 Command,
1313                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1314 {
1315         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1316         struct ieee80211_node_target *node;
1317         a_uint8_t vap_index;
1318         a_uint8_t node_index;
1319
1320         node = (struct ieee80211_node_target *)data;
1321
1322         node_index = node->ni_nodeindex;
1323
1324         node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1325         node->ni_flags = adf_os_ntohs(node->ni_flags);
1326         node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1327
1328         adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1329                         NODE_TARGET_SIZE);
1330
1331         vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1332         sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1333         if(sc->sc_sta[node_index].ni.ni_is_vapnode == 1)
1334                 sc->sc_vap[vap_index].av_vap.iv_nodeindex = node_index;
1335
1336         sc->sc_sta[node_index].an_valid = 1;
1337         sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1338         sc->sc_sta[node_index].ni.ni_iv16 = 0;
1339         sc->sc_sta[node_index].ni.ni_iv32 = 0;
1340
1341         owl_tgt_node_init(&sc->sc_sta[node_index]);
1342
1343         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1344 }
1345
1346 static void ath_node_cleanup_tgt(void *Context, A_UINT16 Command,
1347                                  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1348 {
1349         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1350         a_uint8_t node_index;
1351         a_uint8_t *nodedata;
1352
1353         nodedata = (a_uint8_t *)data;
1354         node_index = *nodedata;
1355         sc->sc_sta[node_index].an_valid = 0;
1356
1357         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1358 }
1359
1360 static void ath_node_update_tgt(void *Context, A_UINT16 Command,
1361                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1362 {
1363         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1364         struct ieee80211_node_target *node;
1365         a_uint8_t vap_index;
1366         a_uint8_t node_index;
1367
1368         node = (struct ieee80211_node_target *)data;
1369
1370         node_index = node->ni_nodeindex;
1371
1372         node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1373         node->ni_flags = adf_os_ntohs(node->ni_flags);
1374         node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1375
1376         adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1377                         NODE_TARGET_SIZE);
1378
1379         vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1380         sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1381
1382         sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1383         sc->sc_sta[node_index].ni.ni_iv16 = 0;
1384         sc->sc_sta[node_index].ni.ni_iv32 = 0;
1385
1386         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1387 }
1388
1389 static a_int32_t ath_reg_read_filter(struct ath_hal *ah, a_int32_t addr)
1390 {
1391         if ((addr & 0xffffe000) == 0x2000) {
1392                 /* SEEPROM registers */
1393                 ioread32_mac(addr);
1394                 if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0))
1395                         adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
1396
1397                 return ioread32_mac(0x407c) & 0x0000ffff;
1398         } else if (addr > 0xffff)
1399                 /* SoC registers */
1400                 return ioread32(addr);
1401         else
1402                 /* MAC registers */
1403                 return ioread32_mac(addr);
1404 }
1405
1406 static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
1407                                  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1408 {
1409         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1410         struct ath_hal *ah = sc->sc_ah;
1411         a_uint32_t addr;
1412         a_uint32_t val[32];
1413         int i;
1414
1415         for (i = 0; i < datalen; i += sizeof(a_int32_t)) {
1416                 addr = *(a_uint32_t *)(data + i);
1417                 addr = adf_os_ntohl(addr);
1418
1419                 val[i/sizeof(a_int32_t)] =
1420                         adf_os_ntohl(ath_reg_read_filter(ah, addr));
1421         }
1422
1423         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &val[0], datalen);
1424 }
1425
1426 static void ath_pll_reset_ones(struct ath_hal *ah)
1427 {
1428         static uint8_t reset_pll = 0;
1429
1430         if(reset_pll == 0) {
1431 #if defined(PROJECT_K2)
1432                 /* here we write to core register */
1433                 iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
1434                 /* and here to mac register */
1435                 iowrite32_mac(0x786c,
1436                          ioread32_mac(0x786c) | 0x6000000);
1437                 iowrite32_mac(0x786c,
1438                          ioread32_mac(0x786c) & (~0x6000000));
1439
1440                 iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
1441
1442 #elif defined(PROJECT_MAGPIE) && !defined (FPGA)
1443                 iowrite32_mac(0x7890,
1444                          ioread32_mac(0x7890) | 0x1800000);
1445                 iowrite32_mac(0x7890,
1446                          ioread32_mac(0x7890) & (~0x1800000));
1447 #endif
1448                 reset_pll = 1;
1449         }
1450 }
1451
1452 static void ath_hal_reg_write_filter(struct ath_hal *ah,
1453                         a_uint32_t reg, a_uint32_t val)
1454 {
1455         if(reg > 0xffff) {
1456                 iowrite32(reg, val);
1457 #if defined(PROJECT_K2)
1458                 if(reg == 0x50040) {
1459                         static uint8_t flg=0;
1460
1461                         if(flg == 0) {
1462                                 /* reinit clock and uart.
1463                                  * TODO: Independent on what host will
1464                                  * here set. We do our own decision. Why? */
1465                                 A_CLOCK_INIT(117);
1466                                 A_UART_HWINIT(117*1000*1000, 19200);
1467                                 flg = 1;
1468                         }
1469                 }
1470 #endif
1471         } else {
1472                 if(reg == 0x7014)
1473                         ath_pll_reset_ones(ah);
1474
1475                 iowrite32_mac(reg, val);
1476         }
1477 }
1478
1479 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command,
1480                                   A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1481 {
1482         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1483         struct ath_hal *ah = sc->sc_ah;
1484         int i;
1485         struct registerWrite {
1486                 a_uint32_t reg;
1487                 a_uint32_t val;
1488         }*t;
1489
1490         for (i = 0; i < datalen; i += sizeof(struct registerWrite)) {
1491                 t = (struct registerWrite *)(data+i);
1492
1493                 ath_hal_reg_write_filter(ah, t->reg, t->val);
1494         }
1495
1496         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1497 }
1498
1499 static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command,
1500                                 A_UINT16 SeqNo, A_UINT8 *data,
1501                                 a_int32_t datalen)
1502 {
1503         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1504         struct ath_hal *ah = sc->sc_ah;
1505         struct register_rmw *buf = (struct register_rmw *)data;
1506         int i;
1507
1508         for (i = 0; i < datalen;
1509              i += sizeof(struct register_rmw)) {
1510                 a_uint32_t val;
1511                 buf = (struct register_rmw *)(data + i);
1512
1513                 val = ath_reg_read_filter(ah, buf->reg);
1514                 val &= ~buf->clr;
1515                 val |= buf->set;
1516                 ath_hal_reg_write_filter(ah, buf->reg, val);
1517         }
1518         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1519 }
1520
1521 static void ath_vap_delete_tgt(void *Context, A_UINT16 Command,
1522                                A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1523 {
1524         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1525         a_uint8_t vap_index;
1526
1527         vap_index = *(a_uint8_t *)data;
1528
1529         sc->sc_vap[vap_index].av_valid = 0;
1530         sc->sc_vap[vap_index].av_bcbuf = NULL;
1531         ath_node_vdelete_tgt(sc, vap_index);
1532         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1533 }
1534
1535 static void ath_disable_intr_tgt(void *Context, A_UINT16 Command,
1536                                  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1537 {
1538         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1539         struct ath_hal *ah = sc->sc_ah;
1540
1541         ah->ah_setInterrupts(ah, 0);
1542         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1543 }
1544
1545 static void ath_flushrecv_tgt(void *Context, A_UINT16 Command,
1546                               A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1547 {
1548         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1549         struct ath_rx_buf *bf;
1550
1551         asf_tailq_foreach(bf, &sc->sc_rxbuf, bf_list)
1552                 if (bf->bf_skb != NULL) {
1553                         adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap,
1554                                        ADF_OS_DMA_FROM_DEVICE);
1555                         ath_free_rx_skb(sc, adf_nbuf_queue_remove(&bf->bf_skbhead));
1556                         bf->bf_skb = NULL;
1557                 }
1558
1559         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1560 }
1561
1562 static void ath_tx_draintxq_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1563                                 A_UINT8 *data, a_int32_t datalen)
1564 {
1565         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1566         a_uint32_t q = *(a_uint32_t *)data;
1567         struct ath_txq *txq = NULL;
1568
1569         q = adf_os_ntohl(q);
1570         txq = ATH_TXQ(sc, q);
1571
1572         ath_tx_draintxq(sc, txq);
1573         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1574 }
1575
1576 static void ath_draintxq_tgt(void *Context, A_UINT16 Command,
1577                              A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1578 {
1579         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1580         HAL_BOOL b = (HAL_BOOL) *(a_int32_t *)data;
1581
1582         ath_draintxq(Context, b);
1583         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1584 }
1585
1586 static void ath_aborttx_dma_tgt(void *Context, A_UINT16 Command,
1587                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1588 {
1589         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1590         struct ath_hal *ah = sc->sc_ah;
1591
1592         ah->ah_abortTxDma(sc->sc_ah);
1593         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1594 }
1595
1596 static void ath_aborttxq_tgt(void *Context, A_UINT16 Command,
1597                              A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1598 {
1599
1600         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1601         a_uint16_t i;
1602
1603         for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
1604                 if (ATH_TXQ_SETUP(sc, i))
1605                         ath_tx_draintxq(sc, ATH_TXQ(sc,i));
1606         }
1607
1608         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1609 }
1610
1611 static void ath_stop_tx_dma_tgt(void *Context, A_UINT16 Command,
1612                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1613 {
1614         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1615         struct ath_hal *ah = sc->sc_ah;
1616         a_uint32_t q;
1617
1618         if (!datalen)
1619                 goto done;
1620
1621         q = *(a_uint32_t *)data;
1622
1623         q = adf_os_ntohl(q);
1624         ah->ah_stopTxDma(ah, q);
1625 done:
1626         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1627 }
1628
1629 static void ath_startrecv_tgt(void *Context, A_UINT16 Command,
1630                               A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1631 {
1632
1633         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1634
1635         ath_startrecv(sc);
1636         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1637 }
1638
1639 static void ath_stoprecv_tgt(void *Context, A_UINT16 Command,
1640                              A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1641 {
1642         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1643         struct ath_hal *ah = sc->sc_ah;
1644
1645         ah->ah_stopPcuReceive(ah);
1646         ah->ah_setRxFilter(ah, 0);
1647         ah->ah_stopDmaReceive(ah);
1648
1649         sc->sc_rxlink = NULL;
1650         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1651 }
1652
1653 static void ath_setcurmode_tgt(void *Context, A_UINT16 Command,
1654                                A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1655 {
1656         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1657         a_uint16_t mode;
1658
1659         mode= *((a_uint16_t *)data);
1660         mode = adf_os_ntohs(mode);
1661
1662         ath_setcurmode(sc, mode);
1663
1664         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1665 }
1666
1667 static void ath_detach_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1668                                  A_UINT8 *data, a_int32_t datalen)
1669 {
1670         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1671         struct ath_hal *ah = sc->sc_ah;
1672
1673         ath_desc_free(sc);
1674         ah->ah_detach(ah);
1675         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1676         adf_os_mem_free(sc);
1677 }
1678
1679 static void handle_echo_command(void *pContext, A_UINT16 Command,
1680                                 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1681 {
1682         wmi_cmd_rsp(pContext, WMI_ECHO_CMDID, SeqNo, buffer, Length);
1683 }
1684
1685 static void handle_rc_state_change_cmd(void *Context, A_UINT16 Command,
1686                                        A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1687
1688 {
1689         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1690         struct wmi_rc_state_change_cmd *wmi_data = (struct wmi_rc_state_change_cmd *)buffer;
1691
1692         a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1693
1694         ath_rate_newstate(sc, &sc->sc_vap[wmi_data->vap_index].av_vap,
1695                           wmi_data->vap_state,
1696                           capflag,
1697                           &wmi_data->rs);
1698
1699         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1700 }
1701
1702 static void handle_rc_rate_update_cmd(void *Context, A_UINT16 Command,
1703                                       A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1704 {
1705         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1706         struct wmi_rc_rate_update_cmd *wmi_data = (struct wmi_rc_rate_update_cmd *)buffer;
1707
1708         a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1709
1710         ath_rate_node_update(sc, &sc->sc_sta[wmi_data->node_index],
1711                              wmi_data->isNew,
1712                              capflag,
1713                              &wmi_data->rs);
1714
1715         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1716 }
1717
1718 static void dispatch_magpie_sys_cmds(void *pContext, A_UINT16 Command,
1719                                      A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1720 {
1721         adf_os_assert(0);
1722 }
1723
1724 static void ath_rc_mask_tgt(void *Context, A_UINT16 Command,
1725                             A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1726 {
1727         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1728         struct wmi_rc_rate_mask_cmd *wmi_data = (struct wmi_rc_rate_mask_cmd *)buffer;
1729         int idx, band, i;
1730
1731         idx = wmi_data->vap_index;
1732         band = wmi_data->band;
1733
1734         sc->sc_vap[idx].av_rate_mask[band] = adf_os_ntohl(wmi_data->mask);
1735
1736         if (sc->sc_vap[idx].av_rate_mask[band]) {
1737                 for (i = 0; i < RATE_TABLE_SIZE; i++) {
1738                         if ((1 << i) & sc->sc_vap[idx].av_rate_mask[band]) {
1739                                 sc->sc_vap[idx].av_minrateidx[band] = i;
1740                                 break;
1741                         }
1742                 }
1743         } else {
1744                 sc->sc_vap[idx].av_minrateidx[band] = 0;
1745         }
1746
1747         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1748 }
1749
1750 static WMI_DISPATCH_ENTRY Magpie_Sys_DispatchEntries[] =
1751 {
1752         {handle_echo_command,         WMI_ECHO_CMDID,               0},
1753         {dispatch_magpie_sys_cmds,    WMI_ACCESS_MEMORY_CMDID,      0},
1754         {ath_get_tgt_version,         WMI_GET_FW_VERSION,           0},
1755         {ath_disable_intr_tgt,        WMI_DISABLE_INTR_CMDID,       0},
1756         {ath_enable_intr_tgt,         WMI_ENABLE_INTR_CMDID,        0},
1757         {ath_init_tgt,                WMI_ATH_INIT_CMDID,           0},
1758         {ath_aborttxq_tgt,            WMI_ABORT_TXQ_CMDID,          0},
1759         {ath_stop_tx_dma_tgt,         WMI_STOP_TX_DMA_CMDID,        0},
1760         {ath_aborttx_dma_tgt,         WMI_ABORT_TX_DMA_CMDID,       0},
1761         {ath_tx_draintxq_tgt,         WMI_DRAIN_TXQ_CMDID,          0},
1762         {ath_draintxq_tgt,            WMI_DRAIN_TXQ_ALL_CMDID,      0},
1763         {ath_startrecv_tgt,           WMI_START_RECV_CMDID,         0},
1764         {ath_stoprecv_tgt,            WMI_STOP_RECV_CMDID,          0},
1765         {ath_flushrecv_tgt,           WMI_FLUSH_RECV_CMDID,         0},
1766         {ath_setcurmode_tgt,          WMI_SET_MODE_CMDID,           0},
1767         {ath_node_create_tgt,         WMI_NODE_CREATE_CMDID,        0},
1768         {ath_node_cleanup_tgt,        WMI_NODE_REMOVE_CMDID,        0},
1769         {ath_vap_delete_tgt,          WMI_VAP_REMOVE_CMDID,         0},
1770         {ath_vap_create_tgt,          WMI_VAP_CREATE_CMDID,         0},
1771         {ath_hal_reg_read_tgt,        WMI_REG_READ_CMDID,           0},
1772         {ath_hal_reg_write_tgt,       WMI_REG_WRITE_CMDID,          0},
1773         {handle_rc_state_change_cmd,  WMI_RC_STATE_CHANGE_CMDID,    0},
1774         {handle_rc_rate_update_cmd,   WMI_RC_RATE_UPDATE_CMDID,     0},
1775         {ath_ic_update_tgt,           WMI_TARGET_IC_UPDATE_CMDID,   0},
1776         {ath_enable_aggr_tgt,         WMI_TX_AGGR_ENABLE_CMDID,     0},
1777         {ath_detach_tgt,              WMI_TGT_DETACH_CMDID,         0},
1778         {ath_node_update_tgt,         WMI_NODE_UPDATE_CMDID,        0},
1779         {ath_int_stats_tgt,           WMI_INT_STATS_CMDID,          0},
1780         {ath_tx_stats_tgt,            WMI_TX_STATS_CMDID,           0},
1781         {ath_rx_stats_tgt,            WMI_RX_STATS_CMDID,           0},
1782         {ath_rc_mask_tgt,             WMI_BITRATE_MASK_CMDID,       0},
1783         {ath_hal_reg_rmw_tgt,         WMI_REG_RMW_CMDID,            0},
1784 };
1785
1786 /*****************/
1787 /* Init / Deinit */
1788 /*****************/
1789
1790 static void htc_setup_comp(void)
1791 {
1792 }
1793
1794 static A_UINT8 tgt_ServiceConnect(HTC_SERVICE *pService,
1795                                   HTC_ENDPOINT_ID eid,
1796                                   A_UINT8 *pDataIn,
1797                                   a_int32_t LengthIn,
1798                                   A_UINT8 *pDataOut,
1799                                   a_int32_t *pLengthOut)
1800 {
1801         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)pService->ServiceCtx;
1802
1803         switch(pService->ServiceID) {
1804         case WMI_CONTROL_SVC:
1805                 sc->wmi_command_ep= eid;
1806                 break;
1807         case WMI_BEACON_SVC:
1808                 sc->beacon_ep= eid;
1809                 break;
1810         case WMI_CAB_SVC:
1811                 sc->cab_ep= eid;
1812                 break;
1813         case WMI_UAPSD_SVC:
1814                 sc->uapsd_ep= eid;
1815                 break;
1816         case WMI_MGMT_SVC:
1817                 sc->mgmt_ep= eid;
1818                 break;
1819         case WMI_DATA_VO_SVC:
1820                 sc->data_VO_ep = eid;
1821                 break;
1822         case WMI_DATA_VI_SVC:
1823                 sc->data_VI_ep = eid;
1824                 break;
1825         case WMI_DATA_BE_SVC:
1826                 sc->data_BE_ep = eid;
1827                 break;
1828         case WMI_DATA_BK_SVC:
1829                 sc->data_BK_ep = eid;
1830                 break;
1831         default:
1832                 adf_os_assert(0);
1833         }
1834
1835         return HTC_SERVICE_SUCCESS;
1836 }
1837
1838 static void tgt_reg_service(struct ath_softc_tgt *sc, HTC_SERVICE *svc,
1839                             int svcId, HTC_SERVICE_ProcessRecvMsg recvMsg)
1840 {
1841         svc->ProcessRecvMsg = recvMsg;
1842         svc->ProcessSendBufferComplete = tgt_HTCSendCompleteHandler;
1843         svc->ProcessConnect = tgt_ServiceConnect;
1844         svc->MaxSvcMsgSize = 1600;
1845         svc->TrailerSpcCheckLimit = 0;
1846         svc->ServiceID = svcId;
1847         svc->ServiceCtx = sc;
1848         HTC_RegisterService(sc->tgt_htc_handle, svc);
1849 }
1850
1851 static void tgt_hif_htc_wmi_init(struct ath_softc_tgt *sc)
1852 {
1853         HTC_CONFIG htc_conf;
1854         WMI_SVC_CONFIG wmiConfig;
1855         WMI_DISPATCH_TABLE *Magpie_Sys_Commands_Tbl;
1856
1857         /* Init dynamic buf pool */
1858         sc->pool_handle = BUF_Pool_init(sc->sc_hdl);
1859
1860         /* Init target-side HIF */
1861         sc->tgt_hif_handle = HIF_init(0);
1862
1863         /* Init target-side HTC */
1864         htc_conf.HIFHandle = sc->tgt_hif_handle;
1865         htc_conf.CreditSize = 320;
1866         htc_conf.CreditNumber = ATH_TXBUF;
1867         htc_conf.OSHandle = sc->sc_hdl;
1868         htc_conf.PoolHandle = sc->pool_handle;
1869         sc->tgt_htc_handle = HTC_init(htc_setup_comp, &htc_conf);
1870 #if defined(PROJECT_MAGPIE)
1871         init_htc_handle = sc->tgt_htc_handle;
1872 #endif
1873
1874         tgt_reg_service(sc, &sc->htc_beacon_service, WMI_BEACON_SVC, tgt_HTCRecv_beaconhandler);
1875         tgt_reg_service(sc, &sc->htc_cab_service, WMI_CAB_SVC, tgt_HTCRecv_cabhandler);
1876         tgt_reg_service(sc, &sc->htc_uapsd_service, WMI_UAPSD_SVC, tgt_HTCRecv_uapsdhandler);
1877         tgt_reg_service(sc, &sc->htc_mgmt_service, WMI_MGMT_SVC, tgt_HTCRecv_mgmthandler);
1878         tgt_reg_service(sc, &sc->htc_data_BE_service, WMI_DATA_BE_SVC, tgt_HTCRecvMessageHandler);
1879         tgt_reg_service(sc, &sc->htc_data_BK_service, WMI_DATA_BK_SVC, tgt_HTCRecvMessageHandler);
1880         tgt_reg_service(sc, &sc->htc_data_VI_service, WMI_DATA_VI_SVC, tgt_HTCRecvMessageHandler);
1881         tgt_reg_service(sc, &sc->htc_data_VO_service, WMI_DATA_VO_SVC, tgt_HTCRecvMessageHandler);
1882
1883         /* Init target-side WMI */
1884         Magpie_Sys_Commands_Tbl = (WMI_DISPATCH_TABLE *)adf_os_mem_alloc(sizeof(WMI_DISPATCH_TABLE));
1885         adf_os_mem_zero(Magpie_Sys_Commands_Tbl, sizeof(WMI_DISPATCH_TABLE));
1886         Magpie_Sys_Commands_Tbl->NumberOfEntries = WMI_DISPATCH_ENTRY_COUNT(Magpie_Sys_DispatchEntries);
1887         Magpie_Sys_Commands_Tbl->pTable = Magpie_Sys_DispatchEntries;
1888
1889         adf_os_mem_zero(&wmiConfig, sizeof(WMI_SVC_CONFIG));
1890         wmiConfig.HtcHandle = sc->tgt_htc_handle;
1891         wmiConfig.PoolHandle = sc->pool_handle;
1892         wmiConfig.MaxCmdReplyEvts = ATH_WMI_MAX_CMD_REPLY;
1893         wmiConfig.MaxEventEvts = ATH_WMI_MAX_EVENTS;
1894
1895         sc->tgt_wmi_handle = WMI_Init(&wmiConfig);
1896         Magpie_Sys_Commands_Tbl->pContext = sc;
1897         WMI_RegisterDispatchTable(sc->tgt_wmi_handle, Magpie_Sys_Commands_Tbl);
1898
1899         HTC_NotifyTargetInserted(sc->tgt_htc_handle);
1900
1901         /* Start HTC messages exchange */
1902         HTC_Ready(sc->tgt_htc_handle);
1903 }
1904
1905 a_int32_t ath_tgt_attach(a_uint32_t devid, struct ath_softc_tgt *sc, adf_os_device_t osdev)
1906 {
1907         struct ath_hal *ah;
1908         HAL_STATUS status;
1909         a_int32_t error = 0, i, flags = 0;
1910         a_uint8_t csz;
1911
1912         adf_os_pci_config_read8(osdev, ATH_PCI_CACHE_LINE_SIZE, &csz);
1913
1914         if (csz == 0)
1915                 csz = 16;
1916         sc->sc_cachelsz = csz << 2;
1917
1918         sc->sc_dev = osdev;
1919         sc->sc_hdl = osdev;
1920
1921         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_rxtq, ath_tgt_rx_tasklet, sc);
1922         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_txtq, owl_tgt_tx_tasklet, sc);
1923         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_bmisstq, ath_bmiss_tasklet, sc);
1924         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_fataltq, ath_fatal_tasklet, sc);
1925
1926         flags |= AH_USE_EEPROM;
1927         ah = _ath_hal_attach_tgt(devid, sc, sc->sc_dev, flags, &status);
1928         if (ah == NULL) {
1929                 error = ENXIO;
1930                 goto bad;
1931         }
1932         sc->sc_ah = ah;
1933
1934         tgt_hif_htc_wmi_init(sc);
1935
1936         sc->sc_bhalq = HAL_NUM_TX_QUEUES - 1;
1937
1938         ath_rate_setup(sc, IEEE80211_MODE_11NA);
1939         ath_rate_setup(sc, IEEE80211_MODE_11NG);
1940
1941         sc->sc_rc = ath_rate_attach(sc);
1942         if (sc->sc_rc == NULL) {
1943                 error = EIO;
1944                 goto bad2;
1945         }
1946
1947         for (i=0; i < TARGET_NODE_MAX; i++) {
1948                 sc->sc_sta[i].an_rcnode = adf_os_mem_alloc(sc->sc_rc->arc_space);
1949         }
1950
1951         error = ath_desc_alloc(sc);
1952         if (error != 0) {
1953                 goto bad;
1954         }
1955
1956         BUF_Pool_create_pool(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ath_numrxdescs, 1664);
1957
1958         ath_tgt_txq_setup(sc);
1959         sc->sc_imask =0;
1960         ah->ah_setInterrupts(ah, 0);
1961
1962         return 0;
1963 bad:
1964 bad2:
1965         ath_desc_free(sc);
1966         if (ah)
1967                 ah->ah_detach(ah);
1968 }
1969
1970 static void tgt_hif_htc_wmi_shutdown(struct ath_softc_tgt *sc)
1971 {
1972         HTC_NotifyTargetDetached(sc->tgt_htc_handle);
1973
1974         WMI_Shutdown(sc->tgt_wmi_handle);
1975         HTC_Shutdown(sc->tgt_htc_handle);
1976         HIF_shutdown(sc->tgt_hif_handle);
1977         BUF_Pool_shutdown(sc->pool_handle);
1978 }
1979
1980 a_int32_t ath_detach(struct ath_softc_tgt *sc)
1981 {
1982         tgt_hif_htc_wmi_shutdown(sc);
1983 }