ath9k_htc/target_firmware/magpie_fw_dev/target/inc/k2/k2_mem.h

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted (subject to the limitations in the
   7  * disclaimer below) provided that the following conditions are met:
   8  *
   9  *  * Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  *  * Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the
  15  *    distribution.
  16  *
  17  *  * Neither the name of Qualcomm Atheros nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  *
  21  * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
  22  * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
  23  * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  32  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  33  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35 /*************************************************************************/
  36 /*  Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */
  37 /*                                                                       */
  38 /*  Module Name : mem_addrs.h                                            */
  39 /*                                                                       */
  40 /*  Abstract                                                             */
  41 /*      This file contains definition of the memory related information. */
  42 /*                                                                       */
  43 /*  NOTES                                                                */
  44 /*      None                                                             */
  45 /*                                                                       */
  46 /*************************************************************************/
  47
  48 #ifndef _MEM_ADDRS_H_
  49 #define _MEM_ADDRS_H_
  50
  51 #define SYS_ROM_BLOCK_SIZE              (24*1024)
  52 #define SYS_ROM_BLOCK_NUM               1
  53 #define SYS_ROM_SIZE                    (SYS_ROM_BLOCK_SIZE*SYS_ROM_BLOCK_NUM)
  54
  55 #define SYS_RAM_BLOCK_SIZE              (40*1024)
  56
  57 #define SYS_RAM_BLOCK_NUM               4
  58 #define SYS_RAM_SZIE                    (SYS_RAM_BLOCK_SIZE*SYS_RAM_BLOCK_NUM)
  59
  60 /* instruction port area */
  61 #define SYS_I_R0M_REGION_0_BASE         0x8e0000
  62
  63 #define SYS_I_RAM_REGION_0_BASE         0x900000
  64 #define SYS_I_RAM_REGION_1_BASE         (SYS_I_RAM_REGION_0_BASE+SYS_RAM_BLOCK_SIZE)
  65 #define SYS_I_RAM_REGION_2_BASE         (SYS_I_RAM_REGION_1_BASE+SYS_RAM_BLOCK_SIZE)
  66 #define SYS_I_RAM_REGION_3_BASE         (SYS_I_RAM_REGION_2_BASE+SYS_RAM_BLOCK_SIZE)
  67
  68 /* data port area */
  69 #define SYS_D_R0M_REGION_0_BASE         0x4e0000
  70
  71 #define SYS_D_RAM_REGION_0_BASE         0x500000
  72 #define SYS_D_RAM_REGION_1_BASE         (SYS_D_RAM_REGION_0_BASE+SYS_RAM_BLOCK_SIZE)
  73 #define SYS_D_RAM_REGION_2_BASE         (SYS_D_RAM_REGION_1_BASE+SYS_RAM_BLOCK_SIZE)
  74 #define SYS_D_RAM_REGION_3_BASE         (SYS_D_RAM_REGION_2_BASE+SYS_RAM_BLOCK_SIZE)
  75
  76 /* data and bss section */
  77
  78 #define SYS_D_RAM_DATA_BSS              SYS_D_RAM_REGION_0_BASE
  79 #define SYS_D_RAM_DATA_BSS_SZ           SYS_RAM_BLOCK_SIZE
  80 #define SYS_D_RAM_STACK_SIZE                (2*1024)
  81 #define SYS_D_RAM_USB_DESC_BUFFER       (SYS_D_RAM_DATA_BSS+SYS_RAM_BLOCK_SIZE)
  82
  83 #define SYS_D_RAM_PCIE_DESC_BUFFER      (SYS_D_RAM_REGION_3_BASE)
  84 #define SPI_FLASH_BASE  0x0F000000
  85 #define SPI_FLASH_MAX_ADDR      0x0FFFFFFF
  86 #define SPI_FLASH_MAX_SIZE      0x01000000
  87 /////////////////////////////////////////////////////////////////////////////////////
  88 #define EEPROM_CTRL_BASE                    0x10000000
  89 #define EEPROM_ADDR_BASE                    (EEPROM_CTRL_BASE+0x2000)
  90
  91 #define EEPROM_SIZE                         0x1000  // 4K addressing space, each has 2 bytes, (a half word)
  92 #define EEPROM_START_OFFSET                 0       // THIS SHOULD NOT MODIFY
  93 #define EEPROM_END_OFFSET                   (EEPROM_START_OFFSET+EEPROM_SIZE-1)   // end of the eeprom offset
  94
  95 /////////////////////////////////////////////////////////////////////////////////////
  96 #define EEPROM_USB_DESCRIPTOR_ADDR          ((uint32_t)&_bss_end)  // address at RAM to put descriptor data
  97 #define USB_DESC_START_ADDR                 0x4
  98 #define USB_DESCRIPTOR_ADDR                 USB_DESC_START_ADDR     // eeprom offset to sotre the descriptor data
  99
 100 #define USB_DESC_IN_EEPROM_SIZE             2                       // indicate eeprom is exist in eeprom
 101 #define USB_DEVICE_DESCRIPTOR_SIZE          16                      // Device Descriptor
 102 #define USB_STRING00_DESCRIPTOR_SIZE        6                       // 16 half word
 103 #define USB_STRING10_DESCRIPTOR_SIZE        12                      // Manufacture data
 104 #define USB_STRING20_DESCRIPTOR_SIZE        16                      // Product/Company data
 105 #define USB_STRING30_DESCRIPTOR_SIZE        8                       // Serial Number
 106
 107 #define USB_DEVICE_PID_SIZE                 1                       // PID SIZE, 1 halfword offset
 108 #define USB_DEVICE_VID_SIZE                 1                       // VID SIZE, 1 halfword offset
 109
 110 #define USB_DESC_IN_EEPROM_FLAG_OFFSET      USB_DESCRIPTOR_ADDR
 111 #define USB_DEVICE_DESCRIPTOR_OFFSET        (USB_DESC_IN_EEPROM_FLAG_OFFSET+USB_DESC_IN_EEPROM_SIZE)
 112 #define USB_STRING00_DESCRIPTOR_OFFSET      (USB_DEVICE_DESCRIPTOR_OFFSET+USB_DEVICE_DESCRIPTOR_SIZE)
 113 #define USB_STRING10_DESCRIPTOR_OFFSET      (USB_STRING00_DESCRIPTOR_OFFSET+USB_STRING00_DESCRIPTOR_SIZE)
 114 #define USB_STRING20_DESCRIPTOR_OFFSET      (USB_STRING10_DESCRIPTOR_OFFSET+USB_STRING10_DESCRIPTOR_SIZE)
 115 #define USB_STRING30_DESCRIPTOR_OFFSET      (USB_STRING20_DESCRIPTOR_OFFSET+USB_STRING20_DESCRIPTOR_SIZE)
 116
 117 #define USB_DEVICE_VID_OFFSET               (USB_DEVICE_DESCRIPTOR_OFFSET+4)
 118 #define USB_DEVICE_PID_OFFSET               (USB_DEVICE_VID_OFFSET+USB_DEVICE_VID_SIZE)
 119
 120 #define USB_DESC_IN_EEPROM_FLAG_ADDR        EEPROM_USB_DESCRIPTOR_ADDR
 121 #define USB_DEVICE_DESCRIPTOR_ADDR          (USB_DESC_IN_EEPROM_FLAG_ADDR+(USB_DESC_IN_EEPROM_SIZE*2))
 122 #define USB_STRING00_DESCRIPTOR_ADDR        (USB_DEVICE_DESCRIPTOR_ADDR+(USB_DEVICE_DESCRIPTOR_SIZE*2))
 123 #define USB_STRING10_DESCRIPTOR_ADDR        (USB_STRING00_DESCRIPTOR_ADDR+(USB_STRING00_DESCRIPTOR_SIZE*2))
 124 #define USB_STRING20_DESCRIPTOR_ADDR        (USB_STRING10_DESCRIPTOR_ADDR+(USB_STRING10_DESCRIPTOR_SIZE*2))
 125 #define USB_STRING30_DESCRIPTOR_ADDR        (USB_STRING20_DESCRIPTOR_ADDR+(USB_STRING20_DESCRIPTOR_SIZE*2))
 126
 127 #define USB_DEVICE_VID_ADDR                 (USB_DEVICE_DESCRIPTOR_ADDR+4)
 128 #define USB_DEVICE_PID_ADDR                 (USB_DEVICE_VID_ADDR+USB_DEVICE_VID_SIZE)
 129
 130 #define USB_DESC_IN_EEP_PATTERN             0x41544852  //ATHR
 131
 132 /****************************** patch in eeprom *****************************************/
 133 #define ROM_PATCH_EEPROM_SIZE                   2                       // 4 bytes
 134
 135 #define ROM_PATCH_EEPROM_OFFSET         0x3E
 136 #define ROM_PATCH_BUF_ADDR              SYS_D_RAM_REGION_3_BASE
 137
 138 #endif /* _MEM_ADDRS_H_ */