ath9k_htc/target_firmware/magpie_fw_dev/target/inc/OTUS/OTUS_soc.h

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted (subject to the limitations in the
   7  * disclaimer below) provided that the following conditions are met:
   8  *
   9  *  * Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  *  * Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the
  15  *    distribution.
  16  *
  17  *  * Neither the name of Qualcomm Atheros nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  *
  21  * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
  22  * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
  23  * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  32  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  33  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35 #ifndef __AR6K_SOC_H__
  36 #define __AR6K_SOC_H__
  37
  38 //#include "hw/apb_map.h"
  39 //#include "hw/rtc_reg.h"
  40 //#include "hw/mbox_reg.h"
  41
  42 /*
  43  * Basic types, appropriate for both
  44  *      the 32-bit MIPS core on AR6000 and
  45  *      the 32-bit XTensa core on AR6002
  46  */
  47 typedef signed char         A_CHAR;
  48 typedef signed char         A_INT8;
  49 typedef unsigned char       A_UINT8;
  50 typedef unsigned char       A_UCHAR;
  51 typedef short               A_INT16;
  52 typedef unsigned short      A_UINT16;
  53 typedef int                 A_INT32;
  54 typedef unsigned int        A_UINT32;
  55 typedef long long           A_INT64;
  56 typedef unsigned long long  A_UINT64;
  57 typedef int                 A_BOOL;
  58 typedef unsigned int        ULONG;
  59 typedef ULONG               A_ULONG;
  60 typedef A_ULONG             A_ADDR;
  61
  62 #if 0
  63 //#include "targaddrs.h"
  64
  65 /*
  66  * Some platform-specific macros and constants that may needed
  67  * outside of the BSP.
  68  */
  69
  70 /*
  71  * AR6001/MIPS uses a cache line size of 16 Bytes.
  72  * AR6002/Xtensa has no caches; but existing code assumes
  73  * that this constant is non-zero.  To avoid code complexity
  74  * and possibly subtle bugs we define a bogus cache
  75  * line size for Xtensa that matches MIPs'.
  76  */
  77 #define A_CACHE_LINE_SIZE         16
  78
  79 #if defined(AR6001)
  80 #define A_MIPS_KSEG_UNCACHED      0xa0000000
  81 #define A_MIPS_KSEG_CACHED        0x80000000
  82 #define A_MIPS_KSEG_MASK          0xe0000000
  83
  84 /*
  85  * Convert a cached virtual address or a CPU physical address into
  86  * an uncached virtual address.
  87  */
  88 #define A_UNCACHED_ADDR(addr)     \
  89     ((void *)(((A_UINT32)(addr)) | A_MIPS_KSEG_UNCACHED))
  90
  91 /*
  92  * Convert an uncached or CPU physical address into
  93  * a cached virtual address.
  94  */
  95 #define A_CACHED_ADDR(addr)       \
  96     ((void *)((((A_UINT32)(addr)) & ~A_MIPS_KSEG_MASK) | A_MIPS_KSEG_CACHED))
  97
  98 /* Read/Write a 32-bit AR6000 SOC register, specified by its physical address */
  99 #define A_SOC_ADDR_READ(addr) (*((volatile A_UINT32 *)A_UNCACHED_ADDR(addr)))
 100
 101 #define A_SOC_ADDR_WRITE(addr, val)                                           \
 102     do {                                                                      \
 103         (*((volatile A_UINT32 *)A_UNCACHED_ADDR(addr))) = (A_UINT32)(val);    \
 104     } while (0)
 105
 106 #define A_RTC_REG_READ(addr)    A_SOC_ADDR_READ(addr)
 107 #define A_MC_REG_READ(addr)     A_SOC_ADDR_READ(addr)
 108 #define A_UART_REG_READ(addr)   A_SOC_ADDR_READ(addr)
 109 #define A_SI_REG_READ(addr)     A_SOC_ADDR_READ(addr)
 110 #define A_GPIO_REG_READ(addr)   A_SOC_ADDR_READ(addr)
 111 #define A_MBOX_REG_READ(addr)   A_SOC_ADDR_READ(addr)
 112 #define A_WMAC_REG_READ(addr)   A_SOC_ADDR_READ(addr)
 113 #define A_ANALOG_REG_READ(addr) A_SOC_ADDR_READ(addr)
 114
 115 #define A_RTC_REG_WRITE(addr, val)     A_SOC_ADDR_WRITE((addr), (val))
 116 #define A_MC_REG_WRITE(addr, val)      A_SOC_ADDR_WRITE((addr), (val))
 117 #define A_UART_REG_WRITE(addr, val)    A_SOC_ADDR_WRITE((addr), (val))
 118 #define A_SI_REG_WRITE(addr, val)      A_SOC_ADDR_WRITE((addr), (val))
 119 #define A_GPIO_REG_WRITE(addr, val)    A_SOC_ADDR_WRITE((addr), (val))
 120 #define A_MBOX_REG_WRITE(addr, val)    A_SOC_ADDR_WRITE((addr), (val))
 121 #define A_WMAC_REG_WRITE(addr, val)    A_SOC_ADDR_WRITE((addr), (val))
 122 #define A_ANALOG_REG_WRITE(addr, val)  A_SOC_ADDR_WRITE((addr), (val))
 123 #endif
 124
 125 #if defined(AR6002)
 126 #define A_UNCACHED_ADDR(addr)     (addr)
 127 #define A_CACHED_ADDR(addr)       (addr)
 128
 129 #define A_SOC_ADDR_READ(addr) (*((volatile A_UINT32 *)(addr)))
 130
 131 #define A_SOC_ADDR_WRITE(addr, val)                                           \
 132     do {                                                                      \
 133         (*((volatile A_UINT32 *)(addr))) = (A_UINT32)(val);                   \
 134     } while (0)
 135
 136 #define A_RTC_REG_READ(addr)    A_SOC_ADDR_READ(RTC_BASE_ADDRESS|(A_UINT32)(addr))
 137 #define A_MC_REG_READ(addr)     A_SOC_ADDR_READ(VMC_BASE_ADDRESS|(A_UINT32)(addr))
 138 #define A_UART_REG_READ(addr)   A_SOC_ADDR_READ(UART_BASE_ADDRESS|(A_UINT32)(addr))
 139 #define A_SI_REG_READ(addr)     A_SOC_ADDR_READ(SI_BASE_ADDRESS|(A_UINT32)(addr))
 140 #define A_GPIO_REG_READ(addr)   A_SOC_ADDR_READ(GPIO_BASE_ADDRESS|(A_UINT32)(addr))
 141 #define A_MBOX_REG_READ(addr)   A_SOC_ADDR_READ(MBOX_BASE_ADDRESS|(A_UINT32)(addr))
 142 #define A_WMAC_REG_READ(addr)   A_SOC_ADDR_READ(MAC_BASE_ADDRESS|(A_UINT32)(addr))
 143 #define A_ANALOG_REG_READ(addr) A_SOC_ADDR_READ(ANALOG_INTF_BASE_ADDRESS|(A_UINT32)(addr))
 144
 145 #define A_RTC_REG_WRITE(addr, val)     A_SOC_ADDR_WRITE(RTC_BASE_ADDRESS|(A_UINT32)(addr), (val))
 146 #define A_MC_REG_WRITE(addr, val)      A_SOC_ADDR_WRITE(VMC_BASE_ADDRESS|(A_UINT32)(addr), (val))
 147 #define A_UART_REG_WRITE(addr, val)    A_SOC_ADDR_WRITE(UART_BASE_ADDRESS|(A_UINT32)(addr), (val))
 148 #define A_SI_REG_WRITE(addr, val)      A_SOC_ADDR_WRITE(SI_BASE_ADDRESS|(A_UINT32)(addr), (val))
 149 #define A_GPIO_REG_WRITE(addr, val)    A_SOC_ADDR_WRITE(GPIO_BASE_ADDRESS|(A_UINT32)(addr), (val))
 150 #define A_MBOX_REG_WRITE(addr, val)    A_SOC_ADDR_WRITE(MBOX_BASE_ADDRESS|(A_UINT32)(addr), (val))
 151 #define A_WMAC_REG_WRITE(addr, val)    A_SOC_ADDR_WRITE(MAC_BASE_ADDRESS|(A_UINT32)(addr), (val))
 152 #define A_ANALOG_REG_WRITE(addr, val)  A_SOC_ADDR_WRITE(ANALOG_INTF_BASE_ADDRESS|(A_UINT32)(addr), (val))
 153
 154 #endif /* AR6002 */
 155
 156 /*
 157  * Sleep/stay awake control.
 158  * It is the caller's responsibility to guarantee atomicity.
 159  */
 160
 161 typedef A_UINT32 A_old_sleep_t;
 162
 163 #define A_SYSTEM_SLEEP_DISABLE(pOldSystemSleep)                        \
 164 do {                                                                   \
 165     *(pOldSystemSleep) = A_RTC_REG_READ(SYSTEM_SLEEP_ADDRESS);         \
 166     A_RTC_REG_WRITE(SYSTEM_SLEEP_ADDRESS,                              \
 167                     *(pOldSystemSleep) | SYSTEM_SLEEP_DISABLE_MASK);   \
 168     (void)A_RTC_REG_READ(SYSTEM_SLEEP_ADDRESS); /* flush */            \
 169 } while (0)
 170
 171 #define A_SYSTEM_SLEEP_RESTORE(OldSystemSleep)                         \
 172 do {                                                                   \
 173     A_RTC_REG_WRITE(SYSTEM_SLEEP_ADDRESS, (OldSystemSleep));           \
 174     (void)A_RTC_REG_READ(SYSTEM_SLEEP_ADDRESS); /* flush */            \
 175 } while (0)
 176
 177
 178 /*
 179  * AR6K-specific High Frequency Timestamp support.
 180  * This is intended for use as a performance tool, and
 181  * is not to be used in normal operation.
 182  */
 183 typedef struct {
 184     A_UINT32 highfreq; /* ~40MHz resolution */
 185     A_UINT32 lowfreq;  /* ~32KHz resolution */
 186 } A_timestamp_t;
 187
 188 /*
 189  * Enable HighFrequency timer.
 190  * Normally, we keep this OFF in order to save power.
 191  */
 192 #define HF_TIMER_CONTROL_START_MASK HF_TIMER_CONTROL_ON_MASK
 193 #define A_TIMESTAMP_ENABLE()                                             \
 194 do {                                                                     \
 195     A_RTC_REG_WRITE(HF_TIMER_ADDRESS, (40000000/32768)<<12);             \
 196     A_RTC_REG_WRITE(HF_TIMER_CONTROL_ADDRESS,                            \
 197                   HF_TIMER_CONTROL_START_MASK |                          \
 198                   HF_TIMER_CONTROL_AUTO_RESTART_MASK |                   \
 199                   HF_TIMER_CONTROL_RESET_MASK);                          \
 200 } while (0)
 201
 202 /*
 203  * Turn it OFF when you're done:
 204  */
 205 #define A_TIMESTAMP_DISABLE() A_RTC_REG_WRITE(HF_TIMER_CONTROL_ADDRESS, 0)
 206
 207 /*
 208  * Get a timestamp.  It's the caller's responsibility to
 209  * guarantee atomicity of the two reads, if needed.
 210  */
 211 #define A_TIMESTAMP(pTimestamp)                                          \
 212     do {                                                                 \
 213         (pTimestamp)->highfreq = A_RTC_REG_READ(HF_TIMER_COUNT_ADDRESS); \
 214         (pTimestamp)->lowfreq = A_RTC_REG_READ(HF_LF_COUNT_ADDRESS);     \
 215     } while (0)
 216
 217 /*
 218  * Supported reference clock speeds.
 219  *
 220  * Note: MAC HAL code has multiple tables indexed by these values,
 221  * so do not rearrange them.  Add any new refclk values at the end.
 222  */
 223 typedef enum {
 224     AR6K_REFCLK_UNKNOWN   = -1, /* Unsupported ref clock -- use PLL Bypass */
 225     AR6K_REFCLK_19_2_MHZ  = 0,
 226     AR6K_REFCLK_26_MHZ    = 1,
 227     AR6K_REFCLK_40_MHZ    = 2,
 228     AR6K_REFCLK_52_MHZ    = 3,
 229     AR6K_REFCLK_38_4_MHZ  = 4,
 230     AR6K_REFCLK_24_MHZ    = 5,
 231 } A_refclk_speed_t;
 232
 233 #define A_REFCLK_UNKNOWN    AR6K_REFCLK_UNKNOWN
 234 #define A_REFCLK_19_2_MHZ   AR6K_REFCLK_19_2_MHZ
 235 #define A_REFCLK_26_MHZ     AR6K_REFCLK_26_MHZ
 236 #define A_REFCLK_40_MHZ     AR6K_REFCLK_40_MHZ
 237 #define A_REFCLK_52_MHZ     AR6K_REFCLK_52_MHZ
 238 #define A_REFCLK_38_4_MHZ   AR6K_REFCLK_38_4_MHZ
 239 #define A_REFCLK_24_MHZ     AR6K_REFCLK_24_MHZ
 240
 241 /* System defaults to 2.4GHz settings */
 242 #define A_BAND_DEFAULT        A_BAND_24GHZ
 243
 244 #if defined(AR6001)
 245 #define FLASH_ADDR(n) AR6000_FLASH_ADDR(n)
 246 #endif
 247
 248 #if defined(AR6002)
 249 #define HOST_INTEREST ((struct host_interest_s *)AR6002_HOST_INTEREST_ADDRESS)
 250 #else
 251 #define HOST_INTEREST ((struct host_interest_s *)AR6001_HOST_INTEREST_ADDRESS)
 252 #endif
 253
 254 #define AR6K_OPTION_TEST(option) \
 255             (A_MBOX_REG_READ(LOCAL_SCRATCH_ADDRESS) & (option))
 256
 257 #endif
 258
 259 #endif /* __AR6K_SOC_H__ */