ath9k_htc/sboot/magpie_1_1/sboot/hif/usb/src/usb_defs.h

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted (subject to the limitations in the
   7  * disclaimer below) provided that the following conditions are met:
   8  *
   9  *  * Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  *  * Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the
  15  *    distribution.
  16  *
  17  *  * Neither the name of Qualcomm Atheros nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  *
  21  * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
  22  * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
  23  * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  32  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  33  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35 #ifndef USB_DEFS_H
  36 #define USB_DEFS_H
  37
  38 #include "usb_table.h"
  39 #include "dt_defs.h"
  40 #include "reg_defs.h"
  41
  42 #define CHECK_SWITCH_BY_BOOTCODE         1   //to be verified for ZD1215, OK for ZD1211
  43 #define VERIFY_CHECKSUM_BY_BOOTCODE      1
  44
  45 /***********************************************************************/
  46 /*  for SEEPROM  Boot                                                  */
  47 /***********************************************************************/
  48 #define WLAN_BOOT_SIGNATURE         (0x19710303)
  49
  50 #define WLAN_SIGNATURE_ADDR         (0x102000)
  51
  52 #define cMAX_ADDR                       0x10000
  53
  54 #define cEEPROM_SIZE                    0x800       // 2k word (4k byte)
  55
  56 #define cRESERVE_LOAD_SPACE             0
  57
  58 // start addr. of boot code
  59 #define cBOOT_CODE_ADDR                 (cMAX_ADDR - cEEPROM_SIZE)  // 0xF800
  60
  61 /************************** Register Addr Process *********************/
  62 #define mpADDR(addr)                                            ((volatile uint16_t*) (addr))
  63 #define mADDR(addr)                                             (*mpADDR(addr))
  64 #define muADDR(addr)                                            ((uint16_t) (&(addr)))
  65
  66 #define USB_BYTE_REG_WRITE(addr, val)           HAL_BYTE_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3), (val))
  67 #define USB_BYTE_REG_READ(addr)                 HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3))
  68 //#define USB_BYTE_REG_READ(addr)               HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr))
  69
  70 #define USB_HALF_WORD_REG_WRITE(addr, val)      HAL_HALF_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr), (val))
  71 #define USB_HALF_WORD_REG_READ(addr)            HAL_HALF_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr))
  72
  73 #define USB_WORD_REG_WRITE(addr, val)           HAL_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr), (val))
  74 #define USB_WORD_REG_READ(addr)                 HAL_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr))
  75
  76
  77 /************************** Register Deinition ***************************/
  78 //#define USB_BASE_ADDR_SOC                0x8000
  79
  80 //#define SOC_Reg                          mpADDR(USB_BASE_ADDR_SOC)
  81
  82 #define cSOC_USB_OFST                    (0x100)
  83
  84 #define ZM_CBUS_FIFO_SIZE_OFFSET    (cSOC_USB_OFST)     //OFFSET 0
  85
  86 #define cSOC_CBUS_CTL_OFFSET             0xF0
  87
  88 #define ZM_FUSB_BASE                     USB_CTRL_BASE_ADDRESS
  89
  90 #define ZM_MAIN_CTRL_OFFSET              0x00
  91 #define ZM_DEVICE_ADDRESS_OFFSET         0x01
  92 #define ZM_TEST_OFFSET                   0x02
  93 #define ZM_PHY_TEST_SELECT_OFFSET        0x08
  94 #define ZM_VDR_SPECIFIC_MODE_OFFSET       0x0A
  95 #define ZM_CX_CONFIG_STATUS_OFFSET       0x0B
  96 #define ZM_EP0_DATA1_OFFSET              0x0C
  97 #define ZM_EP0_DATA2_OFFSET              0x0D
  98 #define ZM_EP0_DATA_OFFSET               0x0C
  99
 100 #define ZM_INTR_MASK_BYTE_0_OFFSET       0x11
 101 #define ZM_INTR_MASK_BYTE_1_OFFSET       0x12
 102 #define ZM_INTR_MASK_BYTE_2_OFFSET       0x13
 103 #define ZM_INTR_MASK_BYTE_3_OFFSET       0x14
 104 #define ZM_INTR_MASK_BYTE_4_OFFSET       0x15
 105 #define ZM_INTR_MASK_BYTE_5_OFFSET       0x16
 106 #define ZM_INTR_MASK_BYTE_6_OFFSET       0x17
 107 #define ZM_INTR_MASK_BYTE_7_OFFSET       0x18
 108
 109 #define ZM_INTR_GROUP_OFFSET             0x20
 110 #define ZM_INTR_SOURCE_0_OFFSET          0x21
 111 #define ZM_INTR_SOURCE_1_OFFSET          0x22
 112 #define ZM_INTR_SOURCE_2_OFFSET          0x23
 113 #define ZM_INTR_SOURCE_3_OFFSET          0x24
 114 #define ZM_INTR_SOURCE_4_OFFSET          0x25
 115 #define ZM_INTR_SOURCE_5_OFFSET          0x26
 116 #define ZM_INTR_SOURCE_6_OFFSET          0x27
 117 #define ZM_INTR_SOURCE_7_OFFSET          0x28
 118
 119 #define ZM_EP_IN_MAX_SIZE_HIGH_OFFSET    0x3F
 120 #define ZM_EP_IN_MAX_SIZE_LOW_OFFSET     0x3E
 121
 122 #define ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET   0x5F
 123 #define ZM_EP_OUT_MAX_SIZE_LOW_OFFSET    0x5E
 124
 125 #define ZM_EP3_BYTE_COUNT_HIGH_OFFSET    0xAE
 126 #define ZM_EP3_BYTE_COUNT_LOW_OFFSET     0xBE
 127 #define ZM_EP4_BYTE_COUNT_HIGH_OFFSET    0xAF
 128 #define ZM_EP4_BYTE_COUNT_LOW_OFFSET     0xBF
 129
 130 #define ZM_EP3_DATA_OFFSET               0xF8
 131 #define ZM_EP4_DATA_OFFSET               0xFC
 132
 133 #define ZM_SOC_USB_MODE_CTRL_OFFSET      0x108
 134 #define ZM_SOC_USB_MAX_AGGREGATE_OFFSET  0x110
 135 #define ZM_SOC_USB_TIME_CTRL_OFFSET      0x114
 136
 137 #define ZM_ADDR_CONV                     0x0
 138
 139 #define ZM_CBUS_FIFO_SIZE_REG                   (ZM_CBUS_FIFO_SIZE_OFFSET^ZM_ADDR_CONV)
 140
 141 #define ZM_CBUS_CTRL_REG                                (cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET^ZM_ADDR_CONV)
 142
 143 #define ZM_MAIN_CTRL_REG                                (ZM_MAIN_CTRL_OFFSET^ZM_ADDR_CONV)
 144
 145 #define ZM_DEVICE_ADDRESS_REG                   (ZM_DEVICE_ADDRESS_OFFSET^ZM_ADDR_CONV)
 146
 147 #define ZM_TEST_REG                                             (ZM_TEST_OFFSET^ZM_ADDR_CONV)
 148
 149 #define ZM_PHY_TEST_SELECT_REG                  (ZM_PHY_TEST_SELECT_OFFSET^ZM_ADDR_CONV)))
 150
 151 #define ZM_CX_CONFIG_STATUS_REG                 (ZM_CX_CONFIG_STATUS_OFFSET^ZM_ADDR_CONV)
 152
 153 #define ZM_EP0_DATA1_REG                                (ZM_EP0_DATA1_OFFSET^ZM_ADDR_CONV)))
 154
 155 #define ZM_EP0_DATA2_REG                                (ZM_EP0_DATA2_OFFSET^ZM_ADDR_CONV)
 156
 157 #define ZM_EP0_DATA_REG                                 (ZM_EP0_DATA_OFFSET^ZM_ADDR_CONV)
 158
 159 #define ZM_INTR_MASK_BYTE_0_REG                 (ZM_INTR_MASK_BYTE_0_OFFSET^ZM_ADDR_CONV)
 160
 161 #define ZM_INTR_MASK_BYTE_1_REG                 (ZM_INTR_MASK_BYTE_1_OFFSET^ZM_ADDR_CONV)
 162
 163 #define ZM_INTR_MASK_BYTE_2_REG                 (ZM_INTR_MASK_BYTE_2_OFFSET^ZM_ADDR_CONV)
 164
 165 #define ZM_INTR_MASK_BYTE_3_REG                 (ZM_INTR_MASK_BYTE_3_OFFSET^ZM_ADDR_CONV)
 166
 167 #define ZM_INTR_MASK_BYTE_4_REG                 (ZM_INTR_MASK_BYTE_4_OFFSET^ZM_ADDR_CONV)
 168
 169 #define ZM_INTR_MASK_BYTE_5_REG                 (ZM_INTR_MASK_BYTE_5_OFFSET^ZM_ADDR_CONV)
 170
 171 #define ZM_INTR_MASK_BYTE_6_REG                 (ZM_INTR_MASK_BYTE_6_OFFSET^ZM_ADDR_CONV)
 172
 173 #define ZM_INTR_MASK_BYTE_7_REG                 (ZM_INTR_MASK_BYTE_7_OFFSET^ZM_ADDR_CONV)
 174
 175 #define ZM_INTR_SOURCE_0_REG                    (ZM_INTR_SOURCE_0_OFFSET^ZM_ADDR_CONV)
 176
 177 #define ZM_INTR_SOURCE_1_REG                    (ZM_INTR_SOURCE_1_OFFSET^ZM_ADDR_CONV)
 178
 179 #define ZM_INTR_SOURCE_2_REG                    (ZM_INTR_SOURCE_2_OFFSET^ZM_ADDR_CONV)
 180
 181 #define ZM_INTR_SOURCE_3_REG                    (ZM_INTR_SOURCE_3_OFFSET^ZM_ADDR_CONV)
 182
 183 #define ZM_INTR_SOURCE_4_REG                    (ZM_INTR_SOURCE_4_OFFSET^ZM_ADDR_CONV)
 184
 185 #define ZM_INTR_SOURCE_5_REG                    (ZM_INTR_SOURCE_5_OFFSET^ZM_ADDR_CONV)
 186
 187 #define ZM_INTR_SOURCE_6_REG                    (ZM_INTR_SOURCE_6_OFFSET^ZM_ADDR_CONV)
 188
 189 #define ZM_INTR_SOURCE_7_REG                    (ZM_INTR_SOURCE_7_OFFSET^ZM_ADDR_CONV)
 190
 191 #define ZM_INTR_GROUP_REG                               (ZM_INTR_GROUP_OFFSET^ZM_ADDR_CONV)))
 192
 193 #define ZM_EP3_BYTE_COUNT_HIGH_REG              (ZM_EP3_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV)
 194
 195 #define ZM_EP3_BYTE_COUNT_LOW_REG               (ZM_EP3_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV)
 196
 197 #define ZM_EP4_BYTE_COUNT_HIGH_REG              (ZM_EP4_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV)
 198
 199 #define ZM_EP4_BYTE_COUNT_LOW_REG               (ZM_EP4_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV)
 200
 201 #define ZM_EP3_DATA_REG                                 (ZM_EP3_DATA_OFFSET)
 202
 203 #define ZM_EP4_DATA_REG                                 (ZM_EP4_DATA_OFFSET)
 204
 205 #define ZM_SOC_USB_MODE_CTRL_REG                (ZM_SOC_USB_MODE_CTRL_OFFSET)
 206
 207 #define ZM_SOC_USB_MAX_AGGREGATE_REG    (ZM_SOC_USB_MAX_AGGREGATE_OFFSET)
 208
 209 #define ZM_SOC_USB_TIME_CTRL_REG                (ZM_SOC_USB_TIME_CTRL_OFFSET)
 210
 211 #define bmHIGH_SPEED                    BIT6
 212 #define bmCWR_BUF_END                   BIT1
 213
 214 #define mUsbEP0DataRd1()                (USB_BYTE_REG_READ(ZM_EP0_DATA1_OFFSET))
 215 //#define mUsbEP0DataRd2()              ZM_EP0_DATA2_REG
 216 //#define mUsbEP0DataRd3()              ZM_EP0_DATA3_REG
 217 //#define mUsbEP0DataRd4()              ZM_EP0_DATA4_REG
 218 #define mUsbEP0DataWr1(data)            (USB_BYTE_REG_WRITE(ZM_EP0_DATA1_OFFSET, data))
 219 #define mUsbEP0DataWr2(data)            (USB_BYTE_REG_WRITE(ZM_EP0_DATA2_OFFSET, data))
 220
 221 #define mGetByte0(data)                 ( data & 0xff )
 222 #define mGetByte1(data)                 ( (data >> 8) & 0xff )
 223 #define mGetByte2(data)                 ( (data >> 16) & 0xff )
 224 #define mGetByte3(data)                 ( (data >> 24) & 0xff )
 225
 226 //#define mUsbHighSpeedST()             (ZM_MAIN_CTRL_REG & BIT6)
 227 //#define mUsbCfgST()                   (ZM_DEVICE_ADDRESS_REG & BIT7)
 228 //#define mUsbApWrEnd()                 (ZM_CBUS_CTRL_REG = bmCWR_BUF_END)
 229 //#define mUsbApRdEnd()                 (ZM_CBUS_CTRL_REG = bmCWR_BUF_END)
 230
 231 #define mUsbHighSpeedST()               (USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET) & BIT6)
 232 #define mUsbCfgST()                     (USB_BYTE_REG_READ(ZM_DEVICE_ADDRESS_OFFSET) & BIT7)
 233 #define mUsbApWrEnd()                   (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END)
 234 #define mUsbApRdEnd()                   (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END)
 235
 236 #define mUsbRmWkupST()                  USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
 237                                                                                         USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&BIT0)
 238 #define mUsbRmWkupClr()                 USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
 239                                                                                         USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&~BIT0)
 240 #define mUsbRmWkupSet()                 USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
 241                                                                                         USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT0)
 242
 243 #define mUsbGlobIntEnable()             USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
 244                                                                                         USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT2)
 245
 246 #define mUSB_REG_OUT_INT_ENABLE()       USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
 247                                                                                         USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0x3f)
 248 #define mUSB_REG_OUT_INT_DISABLE()      USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
 249                                                                                         USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)|0xc0)
 250 #define mUSB_STATUS_IN_INT_ENABLE()     USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
 251                                                                                         USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)&0xbf)
 252 #define mUSB_STATUS_IN_INT_DISABLE()    USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
 253                                                                                         USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0xc0)
 254 //                                                                                      USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0x40)
 255
 256 #define mUSB_EP3_XFER_DONE()            USB_BYTE_REG_WRITE(ZM_EP3_BYTE_COUNT_HIGH_OFFSET, \
 257                                                                                         USB_BYTE_REG_READ(ZM_EP3_BYTE_COUNT_HIGH_OFFSET)|0x08)
 258
 259
 260
 261 #define HS_C1_I0_A0_EP1_MAX_PACKET              MX_PA_SZ_512
 262 #define HS_C1_I0_A0_EP1_bInterval       00
 263
 264 #define HS_C1_I0_A0_EP_NUMBER           0x06
 265 #define HS_C1_I0_A0_EP_LENGTH           (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER)
 266 #define HS_C1_I0_ALT_LENGTH             (HS_C1_I0_A0_EP_LENGTH)
 267 #define HS_C1_INTERFACE_LENGTH          (HS_C1_I0_ALT_LENGTH)
 268
 269 #define HS_C1_CONFIG_TOTAL_LENGTH       (CONFIG_LENGTH + INTERFACE_LENGTH +  HS_C1_INTERFACE_LENGTH)
 270 #define FS_C1_CONFIG_TOTAL_LENGTH       (CONFIG_LENGTH + INTERFACE_LENGTH +  FS_C1_INTERFACE_LENGTH)
 271
 272 #define FS_C1_I0_A0_EP1_MAX_PACKET      MX_PA_SZ_64
 273 //#define FS_C1_I0_A0_EP1_bInterval       HS_C1_I0_A0_EP1_bInterval
 274
 275 #define HS_CONFIGURATION_NUMBER         1
 276 #define FS_CONFIGURATION_NUMBER         1
 277
 278 #define fDOUBLE_BUF                     1
 279 #define fDOUBLE_BUF_IN                  1
 280
 281 #define fFLASH_DISK                     0
 282 #define fENABLE_ISO                     0
 283
 284 #if (HS_CONFIGURATION_NUMBER >= 1)
 285     // Configuration 0X01
 286     #define HS_C1_INTERFACE_NUMBER      0x01
 287     #define HS_C1                       0x01
 288     #define HS_C1_iConfiguration        0x00
 289     #define HS_C1_bmAttribute           0x80
 290     #if !(fFLASH_DISK && !fFLASH_BOOT)
 291     #define HS_C1_iMaxPower             0xFA
 292     #else
 293     #define HS_C1_iMaxPower             0x32
 294     #endif
 295
 296     #if (HS_C1_INTERFACE_NUMBER >= 1)
 297         // Interface 0
 298         #define HS_C1_I0_ALT_NUMBER     0X01
 299         #if (HS_C1_I0_ALT_NUMBER >= 1)
 300             // AlternateSetting 0X00
 301             #define HS_C1_I0_A0_bInterfaceNumber   0X00
 302             #define HS_C1_I0_A0_bAlternateSetting  0X00
 303         //JWEI 2003/07/14
 304             //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT)
 305             #define HS_C1_I0_A0_EP_NUMBER          0x06
 306             //#else
 307             //#define HS_C1_I0_A0_EP_NUMBER          0X03
 308             //#endif
 309             #if !(fFLASH_DISK && !fFLASH_BOOT)
 310             #define HS_C1_I0_A0_bInterfaceClass    0XFF
 311             #define HS_C1_I0_A0_bInterfaceSubClass 0X00
 312             #define HS_C1_I0_A0_bInterfaceProtocol 0X00
 313             #else
 314             #define HS_C1_I0_A0_bInterfaceClass    0X08
 315             #define HS_C1_I0_A0_bInterfaceSubClass 0X06
 316             #define HS_C1_I0_A0_bInterfaceProtocol 0X50
 317             #endif
 318             #define HS_C1_I0_A0_iInterface         0X00
 319
 320             #if (HS_C1_I0_A0_EP_NUMBER >= 1)
 321                 //EP0X01
 322                 #define HS_C1_I0_A0_EP1_BLKSIZE    BLK512BYTE
 323             //JWEI 2003/05/19
 324                 #if fDOUBLE_BUF
 325                 #define HS_C1_I0_A0_EP1_BLKNO      DOUBLE_BLK
 326                 #else
 327                 #define HS_C1_I0_A0_EP1_BLKNO      SINGLE_BLK
 328                 #endif
 329                 #define HS_C1_I0_A0_EP1_DIRECTION  DIRECTION_OUT
 330                 #define HS_C1_I0_A0_EP1_TYPE       TF_TYPE_BULK
 331             //JWEI 2003/05/07
 332                 #define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512
 333                 #define HS_C1_I0_A0_EP1_bInterval  00
 334             #endif
 335             #if (HS_C1_I0_A0_EP_NUMBER >= 2)
 336                 //EP0X02
 337                 #define HS_C1_I0_A0_EP2_BLKSIZE    BLK512BYTE
 338             //JWEI 2003/08/20
 339                 #if fDOUBLE_BUF_IN
 340                 #define HS_C1_I0_A0_EP2_BLKNO      DOUBLE_BLK
 341                 #else
 342                 #define HS_C1_I0_A0_EP2_BLKNO      SINGLE_BLK
 343                 #endif
 344                 #define HS_C1_I0_A0_EP2_DIRECTION  DIRECTION_IN
 345                 #define HS_C1_I0_A0_EP2_TYPE       TF_TYPE_BULK
 346                 #define HS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_512
 347                 #define HS_C1_I0_A0_EP2_bInterval  00
 348             #endif
 349             #if (HS_C1_I0_A0_EP_NUMBER >= 3)
 350                 //EP0X03
 351                 #define HS_C1_I0_A0_EP3_BLKSIZE    BLK64BYTE
 352                 #define HS_C1_I0_A0_EP3_BLKNO      SINGLE_BLK
 353                 #define HS_C1_I0_A0_EP3_DIRECTION  DIRECTION_IN
 354                 #define HS_C1_I0_A0_EP3_TYPE       TF_TYPE_INTERRUPT
 355                 #define HS_C1_I0_A0_EP3_MAX_PACKET 0x0040
 356                 #define HS_C1_I0_A0_EP3_bInterval  01
 357             #endif
 358         // Note: HS Bulk type require max pkt size = 512
 359         //       ==> must use Interrupt type for max pkt size = 64
 360             #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
 361                 //EP0X04
 362                 #define HS_C1_I0_A0_EP4_BLKSIZE    BLK64BYTE
 363                 #define HS_C1_I0_A0_EP4_BLKNO      SINGLE_BLK
 364                 #define HS_C1_I0_A0_EP4_DIRECTION  DIRECTION_OUT
 365                 #define HS_C1_I0_A0_EP4_TYPE       TF_TYPE_INTERRUPT
 366                 #define HS_C1_I0_A0_EP4_MAX_PACKET 0x0040
 367                 #define HS_C1_I0_A0_EP4_bInterval  01
 368             #endif
 369             #if (HS_C1_I0_A0_EP_NUMBER >= 5)
 370                 //EP0X04
 371                 #define HS_C1_I0_A0_EP5_BLKSIZE    BLK512BYTE
 372                 #if fDOUBLE_BUF
 373                 #define HS_C1_I0_A0_EP5_BLKNO      DOUBLE_BLK
 374                 #else
 375                 #define HS_C1_I0_A0_EP5_BLKNO      SINGLE_BLK
 376                 #endif
 377                 #define HS_C1_I0_A0_EP5_DIRECTION  DIRECTION_OUT
 378                 #define HS_C1_I0_A0_EP5_TYPE       TF_TYPE_BULK
 379                 #define HS_C1_I0_A0_EP5_MAX_PACKET MX_PA_SZ_512
 380                 #define HS_C1_I0_A0_EP5_bInterval  00
 381             #endif
 382             #if (HS_C1_I0_A0_EP_NUMBER >= 6)
 383                 //EP0X04
 384                 #define HS_C1_I0_A0_EP6_BLKSIZE    BLK512BYTE
 385                 #if fDOUBLE_BUF
 386                 #define HS_C1_I0_A0_EP6_BLKNO      DOUBLE_BLK
 387                 #else
 388                 #define HS_C1_I0_A0_EP6_BLKNO      SINGLE_BLK
 389                 #endif
 390                 #define HS_C1_I0_A0_EP6_DIRECTION  DIRECTION_OUT
 391                 #define HS_C1_I0_A0_EP6_TYPE       TF_TYPE_BULK
 392                 #define HS_C1_I0_A0_EP6_MAX_PACKET MX_PA_SZ_512
 393                 #define HS_C1_I0_A0_EP6_bInterval  00
 394             #endif
 395         #endif
 396     #endif
 397 #endif
 398
 399 #if (HS_CONFIGURATION_NUMBER >= 1)
 400     // Configuration 1
 401     #if (HS_C1_INTERFACE_NUMBER >= 1)
 402         // Interface 0
 403         #if (HS_C1_I0_ALT_NUMBER >= 1)
 404             // AlternateSetting 0
 405             #define HS_C1_I0_A0_EP_LENGTH           (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER)
 406             #if (HS_C1_I0_A0_EP_NUMBER >= 1)
 407                 // EP1
 408                 #define HS_C1_I0_A0_EP1_FIFO_START  FIFO0
 409                 #define HS_C1_I0_A0_EP1_FIFO_NO     (HS_C1_I0_A0_EP1_BLKNO * HS_C1_I0_A0_EP1_BLKSIZE)
 410                 #define HS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP1_BLKNO - 1) << 2) | HS_C1_I0_A0_EP1_TYPE)
 411                 #define HS_C1_I0_A0_EP1_FIFO_MAP    (((1 - HS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1)
 412                 #define HS_C1_I0_A0_EP1_MAP         (HS_C1_I0_A0_EP1_FIFO_START |   (HS_C1_I0_A0_EP1_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I0_A0_EP1_DIRECTION)))
 413             #endif
 414             #if (HS_C1_I0_A0_EP_NUMBER >= 2)
 415                 // EP2
 416                 #if fDOUBLE_BUF
 417                 #define HS_C1_I0_A0_EP2_FIFO_START  (HS_C1_I0_A0_EP1_FIFO_START + HS_C1_I0_A0_EP1_FIFO_NO)
 418                 #else
 419                 #define HS_C1_I0_A0_EP2_FIFO_START  FIFO2
 420                 #endif
 421                 #define HS_C1_I0_A0_EP2_FIFO_NO     (HS_C1_I0_A0_EP2_BLKNO * HS_C1_I0_A0_EP2_BLKSIZE)
 422                 #define HS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP2_BLKNO - 1) << 2) | HS_C1_I0_A0_EP2_TYPE)
 423                 #define HS_C1_I0_A0_EP2_FIFO_MAP    (((1 - HS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2)
 424                 #define HS_C1_I0_A0_EP2_MAP         (HS_C1_I0_A0_EP2_FIFO_START |   (HS_C1_I0_A0_EP2_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I0_A0_EP2_DIRECTION)))
 425             #endif
 426             #if (HS_C1_I0_A0_EP_NUMBER >= 3)
 427                 // EP3
 428             //JWEI 2003/07/15
 429             //    #define HS_C1_I0_A0_EP3_FIFO_START  (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO)
 430                 #define HS_C1_I0_A0_EP3_FIFO_START  FIFO14
 431                 #define HS_C1_I0_A0_EP3_FIFO_NO     (HS_C1_I0_A0_EP3_BLKNO * HS_C1_I0_A0_EP3_BLKSIZE)
 432                 #define HS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP3_BLKNO - 1) << 2) | HS_C1_I0_A0_EP3_TYPE)
 433                 #define HS_C1_I0_A0_EP3_FIFO_MAP    (((1 - HS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3)
 434                 #define HS_C1_I0_A0_EP3_MAP         (HS_C1_I0_A0_EP3_FIFO_START |   (HS_C1_I0_A0_EP3_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I0_A0_EP3_DIRECTION)))
 435             #endif
 436             #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
 437                 // EP4
 438                 #define HS_C1_I0_A0_EP4_FIFO_START  (HS_C1_I0_A0_EP3_FIFO_START + HS_C1_I0_A0_EP3_FIFO_NO)
 439                 #define HS_C1_I0_A0_EP4_FIFO_NO     (HS_C1_I0_A0_EP4_BLKNO * HS_C1_I0_A0_EP4_BLKSIZE)
 440                 #define HS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP4_BLKNO - 1) << 2) | HS_C1_I0_A0_EP4_TYPE)
 441                 #define HS_C1_I0_A0_EP4_FIFO_MAP    (((1 - HS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4)
 442                 #define HS_C1_I0_A0_EP4_MAP         (HS_C1_I0_A0_EP4_FIFO_START |   (HS_C1_I0_A0_EP4_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I0_A0_EP4_DIRECTION)))
 443             #endif
 444             #if (HS_C1_I0_A0_EP_NUMBER >= 5)
 445                 // EP5
 446                 #define HS_C1_I0_A0_EP5_FIFO_START  (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO)
 447                 #define HS_C1_I0_A0_EP5_FIFO_NO     (HS_C1_I0_A0_EP5_BLKNO * HS_C1_I0_A0_EP5_BLKSIZE)
 448                 #define HS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP5_BLKNO - 1) << 2) | HS_C1_I0_A0_EP5_TYPE)
 449                 #define HS_C1_I0_A0_EP5_FIFO_MAP    (((1 - HS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5)
 450                 #define HS_C1_I0_A0_EP5_MAP         (HS_C1_I0_A0_EP5_FIFO_START |   (HS_C1_I0_A0_EP5_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I0_A0_EP5_DIRECTION)))
 451             #endif
 452             #if (HS_C1_I0_A0_EP_NUMBER >= 6)
 453                 // EP5
 454                 #define HS_C1_I0_A0_EP6_FIFO_START  (HS_C1_I0_A0_EP5_FIFO_START + HS_C1_I0_A0_EP5_FIFO_NO)
 455                 #define HS_C1_I0_A0_EP6_FIFO_NO     (HS_C1_I0_A0_EP6_BLKNO * HS_C1_I0_A0_EP6_BLKSIZE)
 456                 #define HS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP6_BLKNO - 1) << 2) | HS_C1_I0_A0_EP6_TYPE)
 457                 #define HS_C1_I0_A0_EP6_FIFO_MAP    (((1 - HS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6)
 458                 #define HS_C1_I0_A0_EP6_MAP         (HS_C1_I0_A0_EP6_FIFO_START |   (HS_C1_I0_A0_EP6_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I0_A0_EP6_DIRECTION)))
 459             #endif
 460         #endif
 461
 462         #if (HS_C1_I0_ALT_NUMBER >= 2)
 463             // AlternateSetting 1
 464             #define HS_C1_I0_A1_EP_LENGTH           (EP_LENGTH * HS_C1_I0_A1_EP_NUMBER)
 465             #if (HS_C1_I0_A1_EP_NUMBER >= 1)
 466                 // EP1
 467                 #define HS_C1_I0_A1_EP1_FIFO_START  FIFO0
 468                 #define HS_C1_I0_A1_EP1_FIFO_NO     (HS_C1_I0_A1_EP1_BLKNO * HS_C1_I0_A1_EP1_BLKSIZE)
 469                 #define HS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP1_BLKNO - 1) << 2) | HS_C1_I0_A1_EP1_TYPE)
 470                 #define HS_C1_I0_A1_EP1_FIFO_MAP    (((1 - HS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1)
 471                 #define HS_C1_I0_A1_EP1_MAP         (HS_C1_I0_A1_EP1_FIFO_START |   (HS_C1_I0_A1_EP1_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I0_A1_EP1_DIRECTION)))
 472             #endif
 473             #if (HS_C1_I0_A1_EP_NUMBER >= 2)
 474                 // EP2
 475                 #define HS_C1_I0_A1_EP2_FIFO_START  (HS_C1_I0_A1_EP1_FIFO_START + HS_C1_I0_A1_EP1_FIFO_NO)
 476                 #define HS_C1_I0_A1_EP2_FIFO_NO     (HS_C1_I0_A1_EP2_BLKNO * HS_C1_I0_A1_EP2_BLKSIZE)
 477                 #define HS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP2_BLKNO - 1) << 2) | HS_C1_I0_A1_EP2_TYPE)
 478                 #define HS_C1_I0_A1_EP2_FIFO_MAP    (((1 - HS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2)
 479                 #define HS_C1_I0_A1_EP2_MAP         (HS_C1_I0_A1_EP2_FIFO_START |   (HS_C1_I0_A1_EP2_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I0_A1_EP2_DIRECTION)))
 480             #endif
 481             #if (HS_C1_I0_A1_EP_NUMBER >= 3)
 482                 // EP3
 483                 #define HS_C1_I0_A1_EP3_FIFO_START  (HS_C1_I0_A1_EP2_FIFO_START + HS_C1_I0_A1_EP2_FIFO_NO)
 484                 #define HS_C1_I0_A1_EP3_FIFO_NO     (HS_C1_I0_A1_EP3_BLKNO * HS_C1_I0_A1_EP3_BLKSIZE)
 485                 #define HS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP3_BLKNO - 1) << 2) | HS_C1_I0_A1_EP3_TYPE)
 486                 #define HS_C1_I0_A1_EP3_FIFO_MAP    (((1 - HS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3)
 487                 #define HS_C1_I0_A1_EP3_MAP         (HS_C1_I0_A1_EP3_FIFO_START |   (HS_C1_I0_A1_EP3_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I0_A1_EP3_DIRECTION)))
 488             #endif
 489         #endif
 490
 491         #if (HS_C1_I0_ALT_NUMBER == 1)
 492             #define HS_C1_I0_ALT_LENGTH             (HS_C1_I0_A0_EP_LENGTH)
 493         #elif (HS_C1_I0_ALT_NUMBER == 2)
 494             #define HS_C1_I0_ALT_LENGTH             (HS_C1_I0_A0_EP_LENGTH + HS_C1_I0_A1_EP_LENGTH)
 495         #endif
 496     #endif
 497
 498     #if (HS_C1_INTERFACE_NUMBER >= 2)
 499         // Interface 1
 500         #if (HS_C1_I1_ALT_NUMBER >= 1)
 501             // AlternateSetting 0
 502             #define HS_C1_I1_A0_EP_LENGTH           (EP_LENGTH * HS_C1_I1_A0_EP_NUMBER)
 503             #if (HS_C1_I1_A0_EP_NUMBER >= 1)
 504                 // EP1
 505                 #define HS_C1_I1_A0_EP1_FIFO_START  FIFO0
 506                 #define HS_C1_I1_A0_EP1_FIFO_NO     (HS_C1_I1_A0_EP1_BLKNO * HS_C1_I1_A0_EP1_BLKSIZE)
 507                 #define HS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP1_BLKNO - 1) << 2) | HS_C1_I1_A0_EP1_TYPE)
 508                 #define HS_C1_I1_A0_EP1_FIFO_MAP    (((1 - HS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1)
 509                 #define HS_C1_I1_A0_EP1_MAP         (HS_C1_I1_A0_EP1_FIFO_START |   (HS_C1_I1_A0_EP1_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I1_A0_EP1_DIRECTION)))
 510             #endif
 511             #if (HS_C1_I1_A0_EP_NUMBER >= 2)
 512                 // EP2
 513                 #define HS_C1_I1_A0_EP2_FIFO_START  (HS_C1_I1_A0_EP1_FIFO_START + HS_C1_I1_A0_EP1_FIFO_NO)
 514                 #define HS_C1_I1_A0_EP2_FIFO_NO     (HS_C1_I1_A0_EP2_BLKNO * HS_C1_I1_A0_EP2_BLKSIZE)
 515                 #define HS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP2_BLKNO - 1) << 2) | HS_C1_I1_A0_EP2_TYPE)
 516                 #define HS_C1_I1_A0_EP2_FIFO_MAP    (((1 - HS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2)
 517                 #define HS_C1_I1_A0_EP2_MAP         (HS_C1_I1_A0_EP2_FIFO_START |   (HS_C1_I1_A0_EP2_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I1_A0_EP2_DIRECTION)))
 518             #endif
 519             #if (HS_C1_I1_A0_EP_NUMBER >= 3)
 520                 // EP3
 521                 #define HS_C1_I1_A0_EP3_FIFO_START  (HS_C1_I1_A0_EP2_FIFO_START + HS_C1_I1_A0_EP2_FIFO_NO)
 522                 #define HS_C1_I1_A0_EP3_FIFO_NO     (HS_C1_I1_A0_EP3_BLKNO * HS_C1_I1_A0_EP3_BLKSIZE)
 523                 #define HS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP3_BLKNO - 1) << 2) | HS_C1_I1_A0_EP3_TYPE)
 524                 #define HS_C1_I1_A0_EP3_FIFO_MAP    (((1 - HS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3)
 525                 #define HS_C1_I1_A0_EP3_MAP         (HS_C1_I1_A0_EP3_FIFO_START |   (HS_C1_I1_A0_EP3_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I1_A0_EP3_DIRECTION)))
 526             #endif
 527         #endif
 528
 529         #if (HS_C1_I1_ALT_NUMBER >= 2)
 530             // AlternateSetting 1
 531             #define HS_C1_I1_A1_EP_LENGTH           (EP_LENGTH * HS_C1_I1_A1_EP_NUMBER)
 532             #if (HS_C1_I1_A1_EP_NUMBER >= 1)
 533                 // EP1
 534                 #define HS_C1_I1_A1_EP1_FIFO_START  FIFO0
 535                 #define HS_C1_I1_A1_EP1_FIFO_NO     (HS_C1_I1_A1_EP1_BLKNO * HS_C1_I1_A1_EP1_BLKSIZE)
 536                 #define HS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP1_BLKNO - 1) << 2) | HS_C1_I1_A1_EP1_TYPE)
 537                 #define HS_C1_I1_A1_EP1_FIFO_MAP    (((1 - HS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1)
 538                 #define HS_C1_I1_A1_EP1_MAP         (HS_C1_I1_A1_EP1_FIFO_START |   (HS_C1_I1_A1_EP1_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I1_A1_EP1_DIRECTION)))
 539             #endif
 540             #if (HS_C1_I1_A1_EP_NUMBER >= 2)
 541                 // EP2
 542                 #define HS_C1_I1_A1_EP2_FIFO_START  (HS_C1_I1_A1_EP1_FIFO_START + HS_C1_I1_A1_EP1_FIFO_NO)
 543                 #define HS_C1_I1_A1_EP2_FIFO_NO     (HS_C1_I1_A1_EP2_BLKNO * HS_C1_I1_A1_EP2_BLKSIZE)
 544                 #define HS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP2_BLKNO - 1) << 2) | HS_C1_I1_A1_EP2_TYPE)
 545                 #define HS_C1_I1_A1_EP2_FIFO_MAP    (((1 - HS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2)
 546                 #define HS_C1_I1_A1_EP2_MAP         (HS_C1_I1_A1_EP2_FIFO_START |   (HS_C1_I1_A1_EP2_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I1_A1_EP2_DIRECTION)))
 547             #endif
 548             #if (HS_C1_I1_A1_EP_NUMBER >= 3)
 549                 // EP3
 550                 #define HS_C1_I1_A1_EP3_FIFO_START  (HS_C1_I1_A1_EP2_FIFO_START + HS_C1_I1_A1_EP2_FIFO_NO)
 551                 #define HS_C1_I1_A1_EP3_FIFO_NO     (HS_C1_I1_A1_EP3_BLKNO * HS_C1_I1_A1_EP3_BLKSIZE)
 552                 #define HS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP3_BLKNO - 1) << 2) | HS_C1_I1_A1_EP3_TYPE)
 553                 #define HS_C1_I1_A1_EP3_FIFO_MAP    (((1 - HS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3)
 554                 #define HS_C1_I1_A1_EP3_MAP         (HS_C1_I1_A1_EP3_FIFO_START |   (HS_C1_I1_A1_EP3_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I1_A1_EP3_DIRECTION)))
 555             #endif
 556         #endif
 557
 558         #if (HS_C1_I1_ALT_NUMBER == 1)
 559             #define HS_C1_I1_ALT_LENGTH             (HS_C1_I1_A0_EP_LENGTH)
 560         #elif (HS_C1_I1_ALT_NUMBER == 2)
 561             #define HS_C1_I1_ALT_LENGTH             (HS_C1_I1_A0_EP_LENGTH + HS_C1_I1_A1_EP_LENGTH)
 562         #endif
 563     #endif
 564
 565     #if (HS_C1_INTERFACE_NUMBER == 1)
 566         #define HS_C1_INTERFACE_LENGTH              (HS_C1_I0_ALT_LENGTH)
 567     #elif (HS_C1_INTERFACE_NUMBER == 2)
 568         #define HS_C1_INTERFACE_LENGTH              (HS_C1_I0_ALT_LENGTH + HS_C1_I1_ALT_LENGTH)
 569     #endif
 570 #endif
 571
 572 #if (FS_CONFIGURATION_NUMBER >= 1)
 573     // Configuration 0X01
 574     #define FS_C1_INTERFACE_NUMBER  0X01
 575     #define FS_C1                   0X01
 576     #define FS_C1_iConfiguration    0X00
 577     #define FS_C1_bmAttribute       0X80
 578     #define FS_C1_iMaxPower         0XFA
 579
 580     #if (FS_C1_INTERFACE_NUMBER >= 1)
 581         // Interface 0
 582         #define FS_C1_I0_ALT_NUMBER    0X01
 583         #if (FS_C1_I0_ALT_NUMBER >= 1)
 584             // AlternateSetting 0X00
 585             #define FS_C1_I0_A0_bInterfaceNumber   0X00
 586             #define FS_C1_I0_A0_bAlternateSetting  0X00
 587         //JWEI 2003/07/14
 588             //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT)
 589             #define FS_C1_I0_A0_EP_NUMBER          0x05
 590             //#else
 591             //#define FS_C1_I0_A0_EP_NUMBER          0X03
 592             //#endif
 593             #if !(fFLASH_DISK && !fFLASH_BOOT)
 594             #define FS_C1_I0_A0_bInterfaceClass    0XFF
 595             #define FS_C1_I0_A0_bInterfaceSubClass 0X00
 596             #define FS_C1_I0_A0_bInterfaceProtocol 0X00
 597             #else
 598             #define FS_C1_I0_A0_bInterfaceClass    0X08
 599             #define FS_C1_I0_A0_bInterfaceSubClass 0X06
 600             #define FS_C1_I0_A0_bInterfaceProtocol 0X50
 601             #endif
 602             #define FS_C1_I0_A0_iInterface         0X00
 603
 604             #if (FS_C1_I0_A0_EP_NUMBER >= 1)
 605                 //EP0X01
 606                 #define FS_C1_I0_A0_EP1_BLKSIZE    BLK512BYTE
 607             //JWEI 2003/05/19
 608                 #if fDOUBLE_BUF
 609                 #define FS_C1_I0_A0_EP1_BLKNO      DOUBLE_BLK
 610                 #else
 611                 #define FS_C1_I0_A0_EP1_BLKNO      SINGLE_BLK
 612                 #endif
 613                 #define FS_C1_I0_A0_EP1_DIRECTION  DIRECTION_OUT
 614                 #define FS_C1_I0_A0_EP1_TYPE       TF_TYPE_BULK
 615             //JWEI 2003/05/07
 616                 #define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64
 617                 #define FS_C1_I0_A0_EP1_bInterval  00
 618             #endif
 619             #if (FS_C1_I0_A0_EP_NUMBER >= 2)
 620                 //EP0X02
 621                 #define FS_C1_I0_A0_EP2_BLKSIZE    BLK512BYTE
 622             //JWEI 2003/08/20
 623                 #if fDOUBLE_BUF_IN
 624                 #define FS_C1_I0_A0_EP2_BLKNO      DOUBLE_BLK
 625                 #else
 626                 #define FS_C1_I0_A0_EP2_BLKNO      SINGLE_BLK
 627                 #endif
 628                 #define FS_C1_I0_A0_EP2_DIRECTION  DIRECTION_IN
 629                 #define FS_C1_I0_A0_EP2_TYPE       TF_TYPE_BULK
 630                 #define FS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_64
 631                 #define FS_C1_I0_A0_EP2_bInterval  00
 632             #endif
 633             #if (FS_C1_I0_A0_EP_NUMBER >= 3)
 634                 //EP0X03
 635                 #define FS_C1_I0_A0_EP3_BLKSIZE    BLK64BYTE
 636                 #define FS_C1_I0_A0_EP3_BLKNO      SINGLE_BLK
 637                 #define FS_C1_I0_A0_EP3_DIRECTION  DIRECTION_IN
 638                 #define FS_C1_I0_A0_EP3_TYPE       TF_TYPE_INTERRUPT
 639                 #define FS_C1_I0_A0_EP3_MAX_PACKET 0x0040
 640                 #define FS_C1_I0_A0_EP3_bInterval  01
 641             #endif
 642             #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
 643                 //EP0X04
 644                 #define FS_C1_I0_A0_EP4_BLKSIZE    BLK64BYTE
 645                 #define FS_C1_I0_A0_EP4_BLKNO      SINGLE_BLK
 646                 #define FS_C1_I0_A0_EP4_DIRECTION  DIRECTION_OUT
 647                 #define FS_C1_I0_A0_EP4_TYPE       TF_TYPE_BULK
 648                 #define FS_C1_I0_A0_EP4_MAX_PACKET 0x0040
 649                 #define FS_C1_I0_A0_EP4_bInterval  00
 650             #endif
 651             #if (FS_C1_I0_A0_EP_NUMBER >= 5)
 652                 //EP0X04
 653                 #define FS_C1_I0_A0_EP5_BLKSIZE    BLK512BYTE
 654                 #if fDOUBLE_BUF_IN
 655                 #define FS_C1_I0_A0_EP5_BLKNO      DOUBLE_BLK
 656                 #else
 657                 #define FS_C1_I0_A0_EP5_BLKNO      SINGLE_BLK
 658                 #endif
 659                 #define FS_C1_I0_A0_EP5_DIRECTION  DIRECTION_OUT
 660                 #define FS_C1_I0_A0_EP5_TYPE       TF_TYPE_BULK
 661                 #define FS_C1_I0_A0_EP5_MAX_PACKET 0x0040
 662                 #define FS_C1_I0_A0_EP5_bInterval  00
 663             #endif
 664             #if (FS_C1_I0_A0_EP_NUMBER >= 6)
 665                 //EP0X04
 666                 #define FS_C1_I0_A0_EP6_BLKSIZE    BLK512BYTE
 667                 #if fDOUBLE_BUF_IN
 668                 #define FS_C1_I0_A0_EP6_BLKNO      DOUBLE_BLK
 669                 #else
 670                 #define FS_C1_I0_A0_EP6_BLKNO      SINGLE_BLK
 671                 #endif
 672                 #define FS_C1_I0_A0_EP6_DIRECTION  DIRECTION_OUT
 673                 #define FS_C1_I0_A0_EP6_TYPE       TF_TYPE_BULK
 674                 #define FS_C1_I0_A0_EP6_MAX_PACKET 0x0040
 675                 #define FS_C1_I0_A0_EP6_bInterval  00
 676             #endif
 677         #endif
 678     #endif
 679 #endif
 680
 681 #if (FS_CONFIGURATION_NUMBER >= 1)
 682     // Configuration 1
 683     #if (FS_C1_INTERFACE_NUMBER >= 1)
 684         // Interface 0
 685         #if (FS_C1_I0_ALT_NUMBER >= 1)
 686             // AlternateSetting 0
 687             #define FS_C1_I0_A0_EP_LENGTH           (EP_LENGTH * FS_C1_I0_A0_EP_NUMBER)
 688             #if (FS_C1_I0_A0_EP_NUMBER >= 1)
 689                 // EP1
 690                 #define FS_C1_I0_A0_EP1_FIFO_START  FIFO0
 691                 #define FS_C1_I0_A0_EP1_FIFO_NO     (FS_C1_I0_A0_EP1_BLKNO * FS_C1_I0_A0_EP1_BLKSIZE)
 692                 #define FS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP1_BLKNO - 1) << 2) | FS_C1_I0_A0_EP1_TYPE)
 693                 #define FS_C1_I0_A0_EP1_FIFO_MAP    (((1 - FS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1)
 694                 #define FS_C1_I0_A0_EP1_MAP         (FS_C1_I0_A0_EP1_FIFO_START |   (FS_C1_I0_A0_EP1_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I0_A0_EP1_DIRECTION)))
 695             #endif
 696             #if (FS_C1_I0_A0_EP_NUMBER >= 2)
 697                 // EP2
 698                 #define FS_C1_I0_A0_EP2_FIFO_START  (FS_C1_I0_A0_EP1_FIFO_START + FS_C1_I0_A0_EP1_FIFO_NO)
 699                 #define FS_C1_I0_A0_EP2_FIFO_NO     (FS_C1_I0_A0_EP2_BLKNO * FS_C1_I0_A0_EP2_BLKSIZE)
 700                 #define FS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP2_BLKNO - 1) << 2) | FS_C1_I0_A0_EP2_TYPE)
 701                 #define FS_C1_I0_A0_EP2_FIFO_MAP    (((1 - FS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2)
 702                 #define FS_C1_I0_A0_EP2_MAP         (FS_C1_I0_A0_EP2_FIFO_START |   (FS_C1_I0_A0_EP2_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I0_A0_EP2_DIRECTION)))
 703             #endif
 704             #if (FS_C1_I0_A0_EP_NUMBER >= 3)
 705                 // EP3
 706             //JWEI 2003/07/15
 707             //    #define FS_C1_I0_A0_EP3_FIFO_START  (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO)
 708                 #define FS_C1_I0_A0_EP3_FIFO_START  FIFO14
 709                 #define FS_C1_I0_A0_EP3_FIFO_NO     (FS_C1_I0_A0_EP3_BLKNO * FS_C1_I0_A0_EP3_BLKSIZE)
 710                 #define FS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP3_BLKNO - 1) << 2) | FS_C1_I0_A0_EP3_TYPE)
 711                 #define FS_C1_I0_A0_EP3_FIFO_MAP    (((1 - FS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3)
 712                 #define FS_C1_I0_A0_EP3_MAP         (FS_C1_I0_A0_EP3_FIFO_START |   (FS_C1_I0_A0_EP3_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I0_A0_EP3_DIRECTION)))
 713             #endif
 714             #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
 715                 // EP4
 716                 #define FS_C1_I0_A0_EP4_FIFO_START  (FS_C1_I0_A0_EP3_FIFO_START + FS_C1_I0_A0_EP3_FIFO_NO)
 717                 #define FS_C1_I0_A0_EP4_FIFO_NO     (FS_C1_I0_A0_EP4_BLKNO * FS_C1_I0_A0_EP4_BLKSIZE)
 718                 #define FS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP4_BLKNO - 1) << 2) | FS_C1_I0_A0_EP4_TYPE)
 719                 #define FS_C1_I0_A0_EP4_FIFO_MAP    (((1 - FS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4)
 720                 #define FS_C1_I0_A0_EP4_MAP         (FS_C1_I0_A0_EP4_FIFO_START |   (FS_C1_I0_A0_EP4_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I0_A0_EP4_DIRECTION)))
 721             #endif
 722             #if (FS_C1_I0_A0_EP_NUMBER >= 5)
 723                 // EP5
 724                 #define FS_C1_I0_A0_EP5_FIFO_START  (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO)
 725                 #define FS_C1_I0_A0_EP5_FIFO_NO     (FS_C1_I0_A0_EP5_BLKNO * FS_C1_I0_A0_EP5_BLKSIZE)
 726                 #define FS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP5_BLKNO - 1) << 2) | FS_C1_I0_A0_EP5_TYPE)
 727                 #define FS_C1_I0_A0_EP5_FIFO_MAP    (((1 - FS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5)
 728                 #define FS_C1_I0_A0_EP5_MAP         (FS_C1_I0_A0_EP5_FIFO_START |   (FS_C1_I0_A0_EP5_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I0_A0_EP5_DIRECTION)))
 729             #endif
 730             #if (FS_C1_I0_A0_EP_NUMBER >= 6)
 731                 // EP5
 732                 #define FS_C1_I0_A0_EP6_FIFO_START  (FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO)
 733                 #define FS_C1_I0_A0_EP6_FIFO_NO     (FS_C1_I0_A0_EP6_BLKNO * FS_C1_I0_A0_EP6_BLKSIZE)
 734                 #define FS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP6_BLKNO - 1) << 2) | FS_C1_I0_A0_EP6_TYPE)
 735                 #define FS_C1_I0_A0_EP6_FIFO_MAP    (((1 - FS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6)
 736                 #define FS_C1_I0_A0_EP6_MAP         (FS_C1_I0_A0_EP6_FIFO_START |   (FS_C1_I0_A0_EP6_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I0_A0_EP6_DIRECTION)))
 737             #endif
 738         #endif
 739
 740         #if (FS_C1_I0_ALT_NUMBER >= 2)
 741             // AlternateSetting 1
 742             #define FS_C1_I0_A1_EP_LENGTH           (EP_LENGTH * FS_C1_I0_A1_EP_NUMBER)
 743             #if (FS_C1_I0_A1_EP_NUMBER >= 1)
 744                 // EP1
 745                 #define FS_C1_I0_A1_EP1_FIFO_START  FIFO0
 746                 #define FS_C1_I0_A1_EP1_FIFO_NO     (FS_C1_I0_A1_EP1_BLKNO * FS_C1_I0_A1_EP1_BLKSIZE)
 747                 #define FS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP1_BLKNO - 1) << 2) | FS_C1_I0_A1_EP1_TYPE)
 748                 #define FS_C1_I0_A1_EP1_FIFO_MAP    (((1 - FS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1)
 749                 #define FS_C1_I0_A1_EP1_MAP         (FS_C1_I0_A1_EP1_FIFO_START |   (FS_C1_I0_A1_EP1_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I0_A1_EP1_DIRECTION)))
 750             #endif
 751             #if (FS_C1_I0_A1_EP_NUMBER >= 2)
 752                 // EP2
 753                 #define FS_C1_I0_A1_EP2_FIFO_START  (FS_C1_I0_A1_EP1_FIFO_START + FS_C1_I0_A1_EP1_FIFO_NO)
 754                 #define FS_C1_I0_A1_EP2_FIFO_NO     (FS_C1_I0_A1_EP2_BLKNO * FS_C1_I0_A1_EP2_BLKSIZE)
 755                 #define FS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP2_BLKNO - 1) << 2) | FS_C1_I0_A1_EP2_TYPE)
 756                 #define FS_C1_I0_A1_EP2_FIFO_MAP    (((1 - FS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2)
 757                 #define FS_C1_I0_A1_EP2_MAP         (FS_C1_I0_A1_EP2_FIFO_START |   (FS_C1_I0_A1_EP2_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I0_A1_EP2_DIRECTION)))
 758             #endif
 759             #if (FS_C1_I0_A1_EP_NUMBER >= 3)
 760                 // EP3
 761                 #define FS_C1_I0_A1_EP3_FIFO_START  (FS_C1_I0_A1_EP2_FIFO_START + FS_C1_I0_A1_EP2_FIFO_NO)
 762                 #define FS_C1_I0_A1_EP3_FIFO_NO     (FS_C1_I0_A1_EP3_BLKNO * FS_C1_I0_A1_EP3_BLKSIZE)
 763                 #define FS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP3_BLKNO - 1) << 2) | FS_C1_I0_A1_EP3_TYPE)
 764                 #define FS_C1_I0_A1_EP3_FIFO_MAP    (((1 - FS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3)
 765                 #define FS_C1_I0_A1_EP3_MAP         (FS_C1_I0_A1_EP3_FIFO_START |   (FS_C1_I0_A1_EP3_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I0_A1_EP3_DIRECTION)))
 766             #endif
 767         #endif
 768
 769         #if (FS_C1_I0_ALT_NUMBER == 1)
 770             #define FS_C1_I0_ALT_LENGTH             (FS_C1_I0_A0_EP_LENGTH)
 771         #elif (FS_C1_I0_ALT_NUMBER == 2)
 772             #define FS_C1_I0_ALT_LENGTH             (FS_C1_I0_A0_EP_LENGTH + FS_C1_I0_A1_EP_LENGTH)
 773         #endif
 774     #endif
 775
 776     #if (FS_C1_INTERFACE_NUMBER >= 2)
 777         // Interface 1
 778         #if (FS_C1_I1_ALT_NUMBER >= 1)
 779             // AlternateSetting 0
 780             #define FS_C1_I1_A0_EP_LENGTH           (EP_LENGTH * FS_C1_I1_A0_EP_NUMBER)
 781             #if (FS_C1_I1_A0_EP_NUMBER >= 1)
 782                 // EP1
 783                 #define FS_C1_I1_A0_EP1_FIFO_START  FIFO0
 784                 #define FS_C1_I1_A0_EP1_FIFO_NO     (FS_C1_I1_A0_EP1_BLKNO * FS_C1_I1_A0_EP1_BLKSIZE)
 785                 #define FS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP1_BLKNO - 1) << 2) | FS_C1_I1_A0_EP1_TYPE)
 786                 #define FS_C1_I1_A0_EP1_FIFO_MAP    (((1 - FS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1)
 787                 #define FS_C1_I1_A0_EP1_MAP         (FS_C1_I1_A0_EP1_FIFO_START |   (FS_C1_I1_A0_EP1_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I1_A0_EP1_DIRECTION)))
 788             #endif
 789             #if (FS_C1_I1_A0_EP_NUMBER >= 2)
 790                 // EP2
 791                 #define FS_C1_I1_A0_EP2_FIFO_START  (FS_C1_I1_A0_EP1_FIFO_START + FS_C1_I1_A0_EP1_FIFO_NO)
 792                 #define FS_C1_I1_A0_EP2_FIFO_NO     (FS_C1_I1_A0_EP2_BLKNO * FS_C1_I1_A0_EP2_BLKSIZE)
 793                 #define FS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP2_BLKNO - 1) << 2) | FS_C1_I1_A0_EP2_TYPE)
 794                 #define FS_C1_I1_A0_EP2_FIFO_MAP    (((1 - FS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2)
 795                 #define FS_C1_I1_A0_EP2_MAP         (FS_C1_I1_A0_EP2_FIFO_START |   (FS_C1_I1_A0_EP2_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I1_A0_EP2_DIRECTION)))
 796             #endif
 797             #if (FS_C1_I1_A0_EP_NUMBER >= 3)
 798                 // EP3
 799                 #define FS_C1_I1_A0_EP3_FIFO_START  (FS_C1_I1_A0_EP2_FIFO_START + FS_C1_I1_A0_EP2_FIFO_NO)
 800                 #define FS_C1_I1_A0_EP3_FIFO_NO     (FS_C1_I1_A0_EP3_BLKNO * FS_C1_I1_A0_EP3_BLKSIZE)
 801                 #define FS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP3_BLKNO - 1) << 2) | FS_C1_I1_A0_EP3_TYPE)
 802                 #define FS_C1_I1_A0_EP3_FIFO_MAP    (((1 - FS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3)
 803                 #define FS_C1_I1_A0_EP3_MAP         (FS_C1_I1_A0_EP3_FIFO_START |   (FS_C1_I1_A0_EP3_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I1_A0_EP3_DIRECTION)))
 804             #endif
 805         #endif
 806
 807         #if (FS_C1_I1_ALT_NUMBER >= 2)
 808             // AlternateSetting 1
 809             #define FS_C1_I1_A1_EP_LENGTH           (EP_LENGTH * FS_C1_I1_A1_EP_NUMBER)
 810             #if (FS_C1_I1_A1_EP_NUMBER >= 1)
 811                 // EP1
 812                 #define FS_C1_I1_A1_EP1_FIFO_START  FIFO0
 813                 #define FS_C1_I1_A1_EP1_FIFO_NO     (FS_C1_I1_A1_EP1_BLKNO * FS_C1_I1_A1_EP1_BLKSIZE)
 814                 #define FS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP1_BLKNO - 1) << 2) | FS_C1_I1_A1_EP1_TYPE)
 815                 #define FS_C1_I1_A1_EP1_FIFO_MAP    (((1 - FS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1)
 816                 #define FS_C1_I1_A1_EP1_MAP         (FS_C1_I1_A1_EP1_FIFO_START |   (FS_C1_I1_A1_EP1_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I1_A1_EP1_DIRECTION)))
 817             #endif
 818             #if (FS_C1_I1_A1_EP_NUMBER >= 2)
 819                 // EP2
 820                 #define FS_C1_I1_A1_EP2_FIFO_START  (FS_C1_I1_A1_EP1_FIFO_START + FS_C1_I1_A1_EP1_FIFO_NO)
 821                 #define FS_C1_I1_A1_EP2_FIFO_NO     (FS_C1_I1_A1_EP2_BLKNO * FS_C1_I1_A1_EP2_BLKSIZE)
 822                 #define FS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP2_BLKNO - 1) << 2) | FS_C1_I1_A1_EP2_TYPE)
 823                 #define FS_C1_I1_A1_EP2_FIFO_MAP    (((1 - FS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2)
 824                 #define FS_C1_I1_A1_EP2_MAP         (FS_C1_I1_A1_EP2_FIFO_START |   (FS_C1_I1_A1_EP2_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I1_A1_EP2_DIRECTION)))
 825             #endif
 826             #if (FS_C1_I1_A1_EP_NUMBER >= 3)
 827                 // EP3
 828                 #define FS_C1_I1_A1_EP3_FIFO_START  (FS_C1_I1_A1_EP2_FIFO_START + FS_C1_I1_A1_EP2_FIFO_NO)
 829                 #define FS_C1_I1_A1_EP3_FIFO_NO     (FS_C1_I1_A1_EP3_BLKNO * FS_C1_I1_A1_EP3_BLKSIZE)
 830                 #define FS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP3_BLKNO - 1) << 2) | FS_C1_I1_A1_EP3_TYPE)
 831                 #define FS_C1_I1_A1_EP3_FIFO_MAP    (((1 - FS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3)
 832                 #define FS_C1_I1_A1_EP3_MAP         (FS_C1_I1_A1_EP3_FIFO_START |   (FS_C1_I1_A1_EP3_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I1_A1_EP3_DIRECTION)))
 833             #endif
 834         #endif
 835
 836         #if (FS_C1_I1_ALT_NUMBER == 1)
 837             #define FS_C1_I1_ALT_LENGTH             (FS_C1_I1_A0_EP_LENGTH)
 838         #elif (FS_C1_I1_ALT_NUMBER == 2)
 839             #define FS_C1_I1_ALT_LENGTH             (FS_C1_I1_A0_EP_LENGTH + FS_C1_I1_A1_EP_LENGTH)
 840         #endif
 841     #endif
 842
 843     #if (FS_C1_INTERFACE_NUMBER == 1)
 844         #define FS_C1_INTERFACE_LENGTH              (FS_C1_I0_ALT_LENGTH)
 845     #elif (FS_C1_INTERFACE_NUMBER == 2)
 846         #define FS_C1_INTERFACE_LENGTH              (FS_C1_I0_ALT_LENGTH + HS_FS_C1_I1_ALT_LENGTH)
 847     #endif
 848 #endif
 849
 850 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 851 #define USB_ENABLE_UP_DMA()  USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,    \
 852                                                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT0)) // upstream DMA enable
 853
 854 #define USB_DISABLE_UP_DMA()  USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,    \
 855                                                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))) // upstream DMA disable
 856
 857 #define USB_UP_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
 858                                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT3)))   // upQ stream mode
 859
 860 #define USB_UP_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
 861                                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT3))          // upQ packet mode
 862
 863 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 864 #define USB_ENABLE_LP_DN_DMA()  USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,    \
 865                                                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT1))    // lp downstream DMA enable
 866
 867 #define USB_DISABLE_LP_DN_DMA()  USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,    \
 868                                                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT1)))   // lp downstream DMA disable
 869
 870 #define USB_LP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
 871                                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT6)))   // lpQ packet mode
 872
 873 #define USB_LP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
 874                                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT6))          // lpQ stream mode
 875
 876 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 877 #define USB_ENABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,  \
 878                                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8))    // hp downstream DMA enable
 879
 880 #define USB_DISABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,  \
 881                                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT8)))  // hp downstream DMA disable
 882
 883 #define USB_HP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
 884                                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT7)))   // hpQ packet mode
 885
 886 #define USB_HP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
 887                                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT7))          // hpQ stream mode
 888
 889 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 890 #define USB_ENABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9))    // mp downstream DMA enable
 891
 892 #define USB_DISABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT9)))    // mp downstream DMA disable
 893
 894 #define USB_MP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT10)))   // hpQ packet mode
 895
 896 #define USB_MP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT10))          // hpQ stream mode
 897
 898 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 899
 900 #define USB_ENABLE_UP_PACKET_MODE()     USB_DISABLE_UP_DMA();    \
 901                                             USB_UP_PACKET_MODE();   \
 902                                             USB_ENABLE_UP_DMA();
 903
 904 #define USB_ENABLE_LP_DN_PACKET_MODE()  USB_DISABLE_LP_DN_DMA();    \
 905                                             USB_LP_DN_PACKET_MODE();   \
 906                                             USB_ENABLE_LP_DN_DMA()
 907
 908 #define USB_ENABLE_MP_DN_PACKET_MODE()   USB_DISABLE_MP_DN_DMA();    \
 909                                             USB_MP_DN_PACKET_MODE();   \
 910                                             USB_ENABLE_MP_DN_DMA();
 911
 912 #define USB_ENABLE_HP_DN_PACKET_MODE()    USB_DISABLE_HP_DN_DMA();    \
 913                                             USB_HP_DN_PACKET_MODE();   \
 914                                             USB_ENABLE_HP_DN_DMA();
 915
 916 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 917 #define USB_ENABLE_UP_STREAM_MODE()    USB_DISABLE_UP_DMA();    \
 918                                         USB_UP_STREAM_MODE();   \
 919                                         USB_ENABLE_UP_DMA();
 920
 921 #define USB_ENABLE_LP_DN_STREAM_MODE()    USB_DISABLE_LP_DN_DMA();    \
 922                                             USB_LP_DN_STREAM_MODE();   \
 923                                             USB_ENABLE_LP_DN_DMA()
 924
 925 #define USB_ENABLE_MP_DN_STREAM_MODE()    USB_DISABLE_MP_DN_DMA();    \
 926                                             USB_MP_DN_STREAM_MODE();   \
 927                                             USB_ENABLE_MP_DN_DMA();
 928
 929 #define USB_ENABLE_HP_DN_STREAM_MODE()    USB_DISABLE_HP_DN_DMA();    \
 930                                             USB_HP_DN_STREAM_MODE();   \
 931                                             USB_ENABLE_HP_DN_DMA();
 932
 933 #define USB_STREAM_HOST_BUF_SIZE(size)  USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
 934                                                                             (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(size)));
 935 #define USB_STREAM_TIMEOUT(time_cnt)    USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, time_cnt);  // set stream mode timeout critirea
 936 #define USB_STREAM_AGG_PKT_CNT(cnt)     USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, cnt); // set stream mode packet buffer critirea
 937
 938 #endif