ath9k_htc/sboot/magpie_1_1/sboot/hif/usb/src/usb_api.c

   1 #include "usb_defs.h"
   2 #include "usb_type.h"
   3 #include "usb_pre.h"
   4 #include "usb_extr.h"
   5 #include "usb_std.h"
   6 #include "reg_defs.h"
   7 #include "athos_api.h"
   8 #include "usbfifo_api.h"
   9
  10 #include "sys_cfg.h"
  11
  12 #if SYSTEM_MODULE_USB
  13
  14 #define CMD_GET_CUSTOM_DATA     4
  15 LOCAL void flash_read(uint16_t len, uint16_t ofset);
  16
  17 SetupPacket ControlCmd;
  18 USB_FIFO_CONFIG usbFifoConf;
  19 uint32_t fwCheckSum = 0;
  20
  21 #define fBUS_POWER                 1
  22 uint16_t   UsbStatus[3];
  23
  24 /* Variable for USB EP0 pipe (USB.c) */
  25 uint16_t       *pu8DescriptorEX;
  26 uint16_t       u16TxRxCounter;
  27 uint16_t       *u8ConfigDescriptorEX;
  28 //extern BOOLEAN     bUsbEP0HaltSt;
  29 Action      eUsbCxFinishAction;
  30 CommandType eUsbCxCommand;
  31 BOOLEAN     UsbChirpFinish;
  32
  33 uint16_t       u8UsbConfigValue;
  34 uint16_t       u8UsbInterfaceValue;
  35 uint16_t       u8UsbInterfaceAlternateSetting;
  36 uint16_t       u16FirmwareComplete;
  37
  38 extern uint16_t *UsbDeviceDescriptor;
  39 extern uint16_t *String00Descriptor;
  40 extern uint16_t *String10Descriptor;
  41 extern uint16_t *String20Descriptor;
  42 extern uint16_t *String30Descriptor;
  43
  44 /////////////////////////////////////////////////
  45 // should be declared as extern array not pointer
  46 extern uint16_t u8DeviceQualifierDescriptorEX[];
  47 extern uint16_t u8OtherSpeedConfigDescriptorEX[];
  48
  49 uint16_t *u8UsbDeviceDescriptor;
  50 uint16_t *u8String00Descriptor;
  51 uint16_t *u8String10Descriptor;
  52 uint16_t *u8String20Descriptor;
  53 uint16_t *u8String30Descriptor;
  54
  55
  56 #if 0   // use macro instead of function
  57 void mUsbEPinRsTgSet(uint8_t u8ep)
  58 {
  59     //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
  60     //*reg |= BIT4;
  61     USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
  62         (USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT4));
  63
  64 }
  65
  66 void mUsbEPinRsTgClr(uint8_t u8ep)
  67 {
  68     //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
  69     //*reg &= ~BIT4;
  70     USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
  71         (USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&(~BIT4)));
  72 }
  73
  74 void mUsbEPoutRsTgSet(uint8_t u8ep)
  75 {
  76     //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
  77     //*reg |= BIT4;
  78     USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
  79         (USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT4));
  80 }
  81
  82 void mUsbEPoutRsTgClr(uint8_t u8ep)
  83 {
  84     //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
  85     //*reg &= ~BIT4;
  86     USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
  87         (USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&(~BIT4)));
  88 }
  89
  90 void mUsbEPinStallSet(uint8_t u8ep)
  91 {
  92     //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
  93     //*reg |= BIT3;
  94     USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
  95         USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT3);
  96 }
  97
  98 void mUsbEPinStallClr(uint8_t u8ep)
  99 {
 100     //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
 101     //*reg &= ~BIT3;
 102
 103     USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
 104         (USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&(~BIT3)));
 105 }
 106
 107 void mUsbEPoutStallSet(uint8_t u8ep)
 108 {
 109     //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
 110     //*reg |= BIT3;
 111     USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
 112         (USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT3));
 113 }
 114
 115 void mUsbEPoutStallClr(uint8_t u8ep)
 116 {
 117     //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
 118     //*reg &= ~BIT3;
 119     USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
 120         (USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&(~BIT3)));
 121 }
 122
 123 uint8_t mUsbEPinStallST(uint8_t u8ep)
 124 {
 125     //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
 126     //return ((*reg & BIT3) >> 3);
 127     return ((USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))& BIT3) >> 3);
 128 }
 129
 130 uint8_t mUsbEPoutStallST(uint8_t u8ep)
 131 {
 132     //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
 133     //return ((*reg & BIT3) >> 3);
 134     return ((USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))& BIT3) >> 3);
 135 }
 136
 137 uint8_t mUsbEPMapRd(uint8_t EPn)
 138 {
 139     //uint8_t *reg = (uint8_t*) (ZM_FUSB_BASE+0x30+(EPn-1));
 140     //return *reg;
 141     return (USB_BYTE_REG_READ((0x30+(EPn-1))));
 142 }
 143
 144 uint8_t mUsbFIFOCfgRd(uint8_t FIFOn)
 145 {
 146     //uint8_t *reg = (uint8_t*) (ZM_FUSB_BASE+0x90+FIFOn);
 147     //return *reg;
 148     return (USB_BYTE_REG_READ((0x90+FIFOn)));
 149 }
 150
 151 void vUsb_Data_Out0Byte(void)
 152 {
 153     //ZM_INTR_SOURCE_7_REG &= ~BIT7;
 154     USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, \
 155         (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_REG&(~BIT7))));
 156 }
 157
 158
 159 void vUsb_Data_In0Byte(void)
 160 {
 161     //ZM_INTR_SOURCE_7_REG &= ~BIT6;
 162
 163     USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, \
 164         (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_REG&(~BIT6))));
 165 }
 166
 167
 168 /***********************************************************************/
 169 //      vUsb_ep0end()
 170 //      Description:
 171 //          1. End this transfer.
 172 //      input: none
 173 //      output: none
 174 /***********************************************************************/
 175 void vUsb_ep0end(void)
 176 {
 177     eUsbCxCommand = CMD_VOID;
 178     //ZM_CX_CONFIG_STATUS_REG = 0x01;
 179     USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01);
 180     //mUsbEP0DoneSet();                               // Return EP0_Done flag
 181 }
 182
 183 /***********************************************************************/
 184 //      vUsb_ep0fail()
 185 //      Description:
 186 //          1. Stall this transfer.
 187 //      input: none
 188 //      output: none
 189 /***********************************************************************/
 190 void vUsb_ep0fail(void)
 191 {
 192     //ZM_CX_CONFIG_STATUS_REG = 0x04;
 193     USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04);
 194     //mUsbEP0StallSet();                              // Return EP0_Stall
 195 }
 196
 197
 198 /***********************************************************************/
 199 //      vUsb_rst()
 200 //      Description:
 201 //          1. Change descriptor table (High or Full speed).
 202 //      input: none
 203 //      output: none
 204 /***********************************************************************/
 205 void vUsb_rst(void)
 206 {
 207 //    zfUartSendStr((uint8_t *) "vUsb_rst\r\n");
 208     //ZM_INTR_SOURCE_7_REG &= ~0x02;
 209     USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
 210         (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&(~BIT1)));
 211     UsbChirpFinish = FALSE;
 212 }
 213
 214 /***********************************************************************/
 215 //      vUsb_suspend()
 216 //      Description:
 217 //          1. .
 218 //      input: none
 219 //      output: none
 220 /***********************************************************************/
 221 void vUsb_suspend(void)
 222 {
 223 // uP must do-over everything it should handle
 224 // and do before into the suspend mode
 225     //mUsbIntSuspClr();                       // Go Suspend status
 226     //ZM_INTR_SOURCE_7_REG &= ~0x04;
 227     USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
 228         (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&(~BIT2)));
 229 }
 230
 231 /***********************************************************************/
 232 //      vUsb_resm()
 233 //      Description:
 234 //          1. Change descriptor table (High or Full speed).
 235 //      input: none
 236 //      output: none
 237 /***********************************************************************/
 238 void vUsb_resm(void)
 239 {
 240 // uP must do-over everything it should handle
 241 // and do before into the suspend mode
 242
 243 //    mUsbIntResmClr();                       // uP must wakeup immediately
 244     //ZM_INTR_SOURCE_7_REG &= ~0x08;
 245     USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
 246         (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&(~BIT3)));
 247 }
 248
 249 #else
 250
 251 #define mUsbEPinRsTgSet(u8ep)   USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
 252                                     USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT4)
 253
 254 #define mUsbEPinRsTgClr(u8ep)   USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
 255                                     USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&~BIT4)
 256
 257 #define mUsbEPoutRsTgSet(u8ep)  USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
 258                                     USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT4)
 259
 260 #define mUsbEPoutRsTgClr(u8ep)  USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
 261                                     USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&~BIT4)
 262
 263 #define mUsbEPinStallSet(u8ep)  USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
 264                                     USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT3)
 265
 266 #define mUsbEPinStallClr(u8ep)  USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
 267                                     USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&~BIT3)
 268
 269 #define mUsbEPoutStallSet(u8ep) USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
 270                                     USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT3)
 271
 272 #define mUsbEPoutStallClr(u8ep) USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
 273                                     USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&~BIT3)
 274
 275 #define mUsbEPinStallST(u8ep) ((USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))& BIT3) >> 3)
 276
 277 #define mUsbEPoutStallST(u8ep) ((USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))& BIT3) >> 3)
 278
 279 #define mUsbEPMapRd(EPn)    (USB_BYTE_REG_READ((0x30+(EPn-1))))
 280
 281 #define mUsbFIFOCfgRd(FIFOn)    (USB_BYTE_REG_READ((0x90+FIFOn)))
 282
 283 #define vUsb_Data_Out0Byte(void)    USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, \
 284                                         USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_REG&~BIT7))
 285
 286
 287 #define vUsb_Data_In0Byte(void) USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, \
 288                                     USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_REG&~BIT6))
 289
 290 #define vUsb_ep0end(void)                                   \
 291 {                                                           \
 292     eUsbCxCommand = CMD_VOID;                               \
 293     USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01);   \
 294 }
 295
 296 #define vUsb_ep0fail(void)  USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04)
 297
 298 #define vUsb_rst()                                              \
 299 {                                                               \
 300     USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET,                 \
 301         (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT1));    \
 302     UsbChirpFinish = FALSE;                                     \
 303 }
 304
 305 #define vUsb_suspend()  USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
 306                             (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT2))
 307
 308 #define vUsb_resm() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET,     \
 309                         (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT3))
 310
 311
 312 #endif
 313
 314 LOCAL void flash_read_data(void)
 315 {
 316     uint8_t u8temp;
 317
 318     // to keep tracking the txrx fifo
 319     // max 64 bytes for transmission one time,
 320     if (u16TxRxCounter < EP0MAXPACKETSIZE)
 321         u8temp = (uint8_t) u16TxRxCounter;
 322     else
 323         u8temp = EP0MAXPACKETSIZE;
 324
 325     u16TxRxCounter -= (uint16_t) u8temp;
 326
 327     {
 328         register uint8_t u8count;
 329         uint8_t remainder;
 330
 331         for (u8count = 0; u8count < (u8temp/4); u8count ++)
 332         {
 333             uint32_t ep0_data;
 334             uint16_t ep0_low;
 335             uint16_t ep0_high;
 336
 337             // pack data into word size
 338             ep0_low = *pu8DescriptorEX++;
 339             ep0_high = *pu8DescriptorEX++;
 340
 341             // composed the data as a word
 342             ep0_data = (ep0_high << 16) + ep0_low;
 343
 344             USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, ep0_data);
 345         }
 346
 347         remainder = u8temp % 4;
 348
 349         // Check whether there are data needed to be filled into the FIFO
 350         if (remainder == 3)
 351         {
 352             uint32_t ep0_data;
 353             uint16_t ep0_low;
 354             uint16_t ep0_high;
 355
 356             // pack data into word size
 357             ep0_low = *pu8DescriptorEX++;
 358             ep0_high = *pu8DescriptorEX++;
 359
 360             ep0_data = (ep0_high << 16) + ep0_low;
 361
 362             USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7);
 363             USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, ep0_data);
 364         }
 365         else if (remainder == 2)
 366         {
 367             USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3);
 368             USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, *pu8DescriptorEX);
 369         }
 370         else if (remainder == 1)
 371         {
 372             USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
 373             USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, *pu8DescriptorEX);
 374         }
 375
 376         // Restore CBus FIFO size to word size
 377         USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xf);
 378     }
 379
 380     // end of the data stage
 381     if (u16TxRxCounter == 0)
 382     {
 383         eUsbCxCommand = CMD_VOID;
 384         eUsbCxFinishAction = ACT_DONE;
 385     }
 386 }
 387
 388 /***********************************************************************/
 389 //      vUsb_ep0tx()
 390 //      Description:
 391 //          1. Transmit data to EP0 FIFO.
 392 //      input: none
 393 //      output: none
 394 /***********************************************************************/
 395 LOCAL void vUsb_ep0tx(void)
 396 {
 397     switch (eUsbCxCommand)
 398     {
 399         case CMD_GET_DESCRIPTOR:
 400             A_USB_EP0_TX_DATA();
 401             break;
 402
 403         default:
 404             /* Mark endpoint STALL */
 405             USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT6);
 406
 407             break;
 408     }
 409
 410 //    eUsbCxFinishAction = ACT_IDLE;
 411 }
 412
 413
 414 /***********************************************************************/
 415 //      vUsb_ep0rx()
 416 //      Description:
 417 //          1. Receive data from EP0 FIFO.
 418 //      input: none
 419 //      output: none
 420 /***********************************************************************/
 421 LOCAL void vUsb_ep0rx(void)
 422 {
 423
 424     switch (eUsbCxCommand)
 425     {
 426         case CMD_SET_DESCRIPTOR:
 427             A_USB_EP0_RX_DATA();
 428             break;
 429         default:
 430             //mUsbEP0StallSet();
 431             break;
 432     }
 433
 434     if (u16TxRxCounter != 0)
 435         eUsbCxFinishAction = ACT_IDLE;
 436 }
 437
 438
 439 LOCAL void vUsbClrEPx(void)
 440 {
 441     uint8_t u8ep;
 442
 443     // Clear All EPx Toggle Bit
 444     for (u8ep = 1; u8ep <= FUSB200_MAX_EP; u8ep ++)
 445     {
 446         mUsbEPinRsTgSet(u8ep);
 447         mUsbEPinRsTgClr(u8ep);
 448     }
 449     for (u8ep = 1; u8ep <= FUSB200_MAX_EP; u8ep ++)
 450     {
 451         mUsbEPoutRsTgSet(u8ep);
 452         mUsbEPoutRsTgClr(u8ep);
 453     }
 454 }
 455
 456
 457 /***********************************************************************/
 458 //      bGet_status()
 459 //      Description:
 460 //          1. Send 2 bytes status to host.
 461 //      input: none
 462 //      output: TRUE or FALSE (BOOLEAN)
 463 /***********************************************************************/
 464 LOCAL BOOLEAN bGet_status(void)
 465 {
 466     uint8_t RecipientStatusLow;
 467
 468     RecipientStatusLow = UsbStatus[mDEV_REQ_REQ_RECI() & 0x0F];
 469
 470     //ZM_CBUS_FIFO_SIZE_REG = 0x3;
 471     //ZM_EP0_DATA_REG = RecipientStatusLow;
 472
 473     USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3);
 474     USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, RecipientStatusLow);
 475
 476     // Restore CBus FIFO size to word size
 477     //ZM_CBUS_FIFO_SIZE_REG = 0xf;
 478     USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xf);
 479
 480     eUsbCxFinishAction = ACT_DONE;
 481     return TRUE;
 482 }
 483
 484 /***********************************************************************/
 485 //      bClear_feature()
 486 //      Description:
 487 //          1. Send 2 bytes status to host.
 488 //      input: none
 489 //      output: TRUE or FALSE (BOOLEAN)
 490 /***********************************************************************/
 491 LOCAL BOOLEAN bClear_feature(void)
 492 {
 493     if (mDEV_REQ_VALUE() > cUSB_FEATSEL_END)
 494         return FALSE;
 495
 496     if ((mDEV_REQ_VALUE() == 0) && (mDEV_REQ_REQ_RECI() != cUSB_REQTYPE_ENDPOINT))
 497         return FALSE;
 498
 499     UsbStatus[2] = 0;
 500     eUsbCxFinishAction = ACT_DONE;
 501
 502     return TRUE;
 503 }
 504
 505 /***********************************************************************/
 506 //      bSet_feature()
 507 //      Description:
 508 //          1. Send 2 bytes status to host.
 509 //      input: none
 510 //      output: TRUE or FALSE (BOOLEAN)
 511 /***********************************************************************/
 512 #if ZM_SELF_TEST_MODE
 513
 514 #define TEST_J                  0x02
 515 #define TEST_K                  0x04
 516 #define TEST_SE0_NAK            0x08
 517 #define TEST_PKY                0x10
 518
 519 uint16_t TestPatn0[] = { TEST_J, TEST_K, TEST_SE0_NAK };
 520 uint32_t TestPatn1[] = {
 521     0x00000000, 0x00000000, 0xAA00AA00,         // JKJKJKJK x 9
 522     0xAAAAAAAA, 0xEEAAAAAA,                     // AA x 8
 523     0xEEEEEEEE, 0xFEEEEEEE,                     // EE x 8
 524     0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF,         // FF x 11
 525     0xF7EFDFBF, 0x7EFCFDFB, 0xFDFBDFBF};
 526
 527 #endif
 528 LOCAL BOOLEAN bSet_feature(void)
 529 {
 530
 531     //A_PRINTF("bSet_feature...\n\r");
 532
 533     switch (mDEV_REQ_VALUE())       // FeatureSelector
 534     {
 535         case 0:     // ENDPOINT_HALE
 536             // AVM Patch:
 537             // always check RECEIPIENT
 538             if (mDEV_REQ_REQ_RECI() == cUSB_REQTYPE_ENDPOINT)
 539             {
 540                 eUsbCxFinishAction = ACT_DONE;
 541             }
 542             else
 543             {
 544                 return FALSE;
 545             }
 546
 547             break;
 548
 549         case 1 :        // Device Remote Wakeup
 550             // Set "Device_Remote_Wakeup", Turn on the"RMWKUP" bit in Mode Register
 551             mUsbRmWkupSet();
 552             //USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT0);
 553             eUsbCxFinishAction = ACT_DONE;
 554             break;
 555
 556     #if ZM_SELF_TEST_MODE
 557         case 2 :        // Test Mode
 558         //    ii = mDEV_REQ_INDEX() >> 8;
 559         //    switch (ii)    // TestSelector
 560             switch (mDEV_REQ_INDEX() >> 8)    // TestSelector
 561             {
 562                 case 0x1:   // Test_J
 563                 case 0x2:   // Test_K
 564                 case 0x3:   // TEST_SE0_NAK
 565                 //    mUsbTsMdWr(TestPatn0[(mDEV_REQ_INDEX() >> 8) - 1]);
 566                     //ZM_PHY_TEST_SELECT_REG = TestPatn0[(mDEV_REQ_INDEX() >> 8) - 1];
 567                     USB_BYTE_REG_WRITE(ZM_PHY_TEST_SELECT_OFFSET, (TestPatn0[(mDEV_REQ_INDEX() >> 8) - 1]));
 568                     eUsbCxFinishAction = ACT_DONE;
 569                     break;
 570
 571                 case 0x4:   // Test_Packet
 572                 //    mUsbTsMdWr(TEST_PKY);
 573                 //    mUsbEP0DoneSet();           // special case: follow the test sequence
 574                     //ZM_PHY_TEST_SELECT_REG = TEST_PKY;
 575                     //ZM_CX_CONFIG_STATUS_REG = 0x01;
 576                     USB_BYTE_REG_WRITE(ZM_PHY_TEST_SELECT_OFFSET, TEST_PKY);
 577                     USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT0);
 578                     /***********************************************************************///////
 579                     // Jay ask to modify, 91-6-5 (Begin)        //
 580                     /***********************************************************************///////
 581                 //    mUsbTsMdWr(TEST_PKY);
 582                 //    mUsbEP0DoneSet();           // special case: follow the test sequence
 583                     //ZM_PHY_TEST_SELECT_REG = TEST_PKY;
 584                     USB_BYTE_REG_WRITE(ZM_PHY_TEST_SELECT_OFFSET, TEST_PKY);
 585
 586                     //ZM_CX_CONFIG_STATUS_REG = 0x01;
 587                     /***********************************************************************///////
 588                     // Jay ask to modify, 91-6-5 (Begin)        //
 589                     /***********************************************************************///////
 590                     {
 591                     uint16_t ii;
 592
 593                         /* Set to two bytes mode */
 594                         //ZM_CBUS_FIFO_SIZE_REG = 0x0f;
 595                         USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f);
 596
 597                         for (ii = 0; ii < sizeof(TestPatn1)/sizeof(uint32_t); ii++)
 598                         {
 599                             //ZM_EP0_DATA_REG = TestPatn1[ii];
 600                             USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, TestPatn1[ii]);
 601                         }
 602
 603                         /* Set to one byte mode */
 604                         //ZM_CBUS_FIFO_SIZE_REG = 0x07;
 605                         //ZM_EP0_DATA_REG = 0x007EFDFB;
 606                         USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x07);
 607                         USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, 0x007EFDFB);
 608
 609                         /* Set to four bytes mode */
 610                         //ZM_CBUS_FIFO_SIZE_REG = 0x0f;
 611                         USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f);
 612                     }
 613                     /***********************************************************************///////
 614                     // Jay ask to modify, 91-6-5 (End)          //
 615                     /***********************************************************************///////
 616
 617                     // Turn on "r_test_packet_done" bit(flag) (Bit 5)
 618                     //mUsbTsPkDoneSet();
 619                     //ZM_CX_CONFIG_STATUS_REG = 0x02;
 620                     USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT1);
 621                     break;
 622
 623                 case 0x5:   // Test_Force_Enable
 624                     //FUSBPort[0x08] = 0x20;    //Start Test_Force_Enable
 625                     break;
 626
 627                 default:
 628                     return FALSE;
 629             }
 630             break;
 631     #endif
 632         default :
 633             return FALSE;
 634     }
 635
 636     if (eUsbCxFinishAction == ACT_DONE)
 637         UsbStatus[2] = 1;
 638
 639     return TRUE;
 640 }
 641
 642
 643 /***********************************************************************/
 644 //      bSet_address()
 645 //      Description:
 646 //          1. Set addr to FUSB200 register.
 647 //      input: none
 648 //      output: TRUE or FALSE (BOOLEAN)
 649 /***********************************************************************/
 650 LOCAL BOOLEAN bSet_address(void)
 651 {
 652
 653     //A_PRINTF("bSet_feature...\n\r");
 654
 655     if (mDEV_REQ_VALUE() >= 0x0100)
 656         return FALSE;
 657     else
 658     {
 659 //        zfUartSendStrAndHex((uint8_t *) "USB_SET_ADDRESS=", mDEV_REQ_VALUE());
 660         //ZM_DEVICE_ADDRESS_REG = mDEV_REQ_VALUE();
 661         USB_BYTE_REG_WRITE(ZM_DEVICE_ADDRESS_OFFSET, mDEV_REQ_VALUE());
 662
 663         eUsbCxFinishAction = ACT_DONE;
 664         return TRUE;
 665     }
 666 }
 667
 668 /***********************************************************************/
 669 //      bGet_descriptor()
 670 //      Description:
 671 //          1. Point to the start location of the correct descriptor.
 672 //          2. set the transfer length
 673 //      input: none
 674 //      output: TRUE or FALSE (BOOLEAN)
 675 /***********************************************************************/
 676 LOCAL BOOLEAN bGet_descriptor(void)
 677 {
 678     //A_PRINTF("bGet_descriptor...\n\r");
 679
 680 // Change Descriptor type
 681 #if 0
 682     u8ConfigDescriptorEX[mTABLE_IDX(1)] =
 683         m2BYTE(CONFIG_LENGTH, DT_CONFIGURATION);
 684     u8OtherSpeedConfigDescriptorEX[mTABLE_IDX(1)] =
 685         m2BYTE(CONFIG_LENGTH, DT_OTHER_SPEED_CONFIGURATION);
 686 #endif
 687
 688     //*(volatile uint32_t*)0x1c0004 = 'G';
 689
 690     switch (mDEV_REQ_VALUE_HIGH())
 691     {
 692         case 1:                 // device descriptor
 693             pu8DescriptorEX = u8UsbDeviceDescriptor;
 694             u16TxRxCounter = mTABLE_LEN(u8UsbDeviceDescriptor[0]);
 695             //u16TxRxCounter = 18;
 696             break;
 697
 698         case 2:                 // configuration descriptor
 699                                 // It includes Configuration, Interface and Endpoint Table
 700 //            zfUartSendStr((uint8_t *)"Configuration Descriptor\r\n");
 701             switch (mDEV_REQ_VALUE_LOW())
 702             {
 703                 case 0x00:      // configuration no: 0
 704                     pu8DescriptorEX = u8ConfigDescriptorEX;
 705                     u16TxRxCounter = u8ConfigDescriptorEX[1];
 706                     //u16TxRxCounter = 46;
 707                     break;
 708                 default:
 709                     return FALSE;
 710             }
 711             break;
 712
 713         case 3:                 // string descriptor
 714                                 // DescriptorIndex = low_byte of wValue
 715 //            zfUartSendStr((uint8_t *)"String Descriptor\r\n");
 716             switch (mDEV_REQ_VALUE_LOW())
 717             {
 718                 case 0x00:
 719                     pu8DescriptorEX = u8String00Descriptor;
 720                     //u16TxRxCounter = 4;
 721                     break;
 722
 723                 case 0x10:
 724                     pu8DescriptorEX = u8String10Descriptor;
 725                     //u16TxRxCounter = 12;
 726                     break;
 727
 728                 case 0x20:
 729                     pu8DescriptorEX = u8String20Descriptor;
 730                     //u16TxRxCounter = 24;
 731                     break;
 732
 733                 case 0x30:
 734                     pu8DescriptorEX = u8String30Descriptor;
 735                     break;
 736
 737                 default:
 738                     return FALSE;
 739             }
 740             u16TxRxCounter = mTABLE_LEN(pu8DescriptorEX[0]);
 741             break;
 742
 743         case 6:                     // Device_Qualifier descritor
 744 //            zfUartSendStr((uint8_t *) "Device_Qualifier Descriptor\r\n");
 745             pu8DescriptorEX = u8DeviceQualifierDescriptorEX;
 746             u16TxRxCounter = mTABLE_LEN(u8DeviceQualifierDescriptorEX[0]);
 747             //u16TxRxCounter = 10;
 748             break;
 749
 750         case 7:                     // Other_Speed_Configuration
 751 //            zfUartSendStr((uint8_t *)"Other_Speed Descriptor\r\n");
 752             // It includes Configuration, Interface and Endpoint Table
 753             pu8DescriptorEX = u8OtherSpeedConfigDescriptorEX;
 754             u16TxRxCounter = u8OtherSpeedConfigDescriptorEX[1];
 755             //u16TxRxCounter = 46;
 756             break;
 757
 758         default:
 759 //            zfUartSendStrAndHex((uint8_t *) "Descriptor error=", mDEV_REQ_VALUE_HIGH());
 760             return FALSE;
 761     }
 762
 763     if (u16TxRxCounter > mDEV_REQ_LENGTH())
 764         u16TxRxCounter = mDEV_REQ_LENGTH();
 765
 766 //    vUsbEP0TxData();
 767     A_USB_EP0_TX_DATA();
 768
 769     // somehow if there is still data need to send out, we shouldn't set CX_DONE
 770     // wait for another EP0_IN
 771     if( u16TxRxCounter > 0 )
 772     {
 773         eUsbCxCommand = CMD_GET_DESCRIPTOR;
 774     }
 775
 776     return TRUE;
 777 }
 778
 779
 780 /***********************************************************************/
 781 //      bGet_configuration()
 782 //      Description:
 783 //          1. Send 1 bytes configuration value to host.
 784 //      input: none
 785 //      output: none
 786 /***********************************************************************/
 787 LOCAL BOOLEAN bGet_configuration(void)
 788 {
 789
 790     //A_PRINTF("bGet_configuration...\n\r");
 791
 792     //ZM_CBUS_FIFO_SIZE_REG = 0x1;
 793     //ZM_EP0_DATA_REG = u8UsbConfigValue;
 794     USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
 795     USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, u8UsbConfigValue);
 796
 797     // Restore CBus FIFO size to word size
 798     //ZM_CBUS_FIFO_SIZE_REG = 0xf;
 799     USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xf);
 800
 801     eUsbCxFinishAction = ACT_DONE;
 802
 803     return TRUE;
 804 }
 805
 806 /***********************************************************************/
 807 //      bSet_configuration()
 808 //      Description:
 809 //          1. Get 1 bytes configuration value from host.
 810 //          2-1. if (value == 0) then device return to address state
 811 //          2-2. if (value match descriptor table)
 812 //                  then config success & Clear all EP toggle bit
 813 //          2-3  else stall this command
 814 //      input: none
 815 //      output: TRUE or FALSE
 816 /***********************************************************************/
 817 LOCAL BOOLEAN bSet_configuration(void)
 818 {
 819 void vUsbClrEPx(void);
 820
 821     //A_PRINTF("bSet_configuration...\n\r");
 822
 823     if (mLOW_BYTE(mDEV_REQ_VALUE()) == 0)
 824     {
 825         u8UsbConfigValue = 0;
 826         //mUsbCfgClr();
 827         //ZM_DEVICE_ADDRESS_REG &= ~BIT7;
 828         USB_BYTE_REG_WRITE(ZM_DEVICE_ADDRESS_OFFSET, (USB_BYTE_REG_READ(ZM_DEVICE_ADDRESS_OFFSET)&~BIT7));
 829     }
 830     else
 831     {
 832         if (mUsbHighSpeedST())                  // First judge HS or FS??
 833         {
 834             if (mLOW_BYTE(mDEV_REQ_VALUE()) > HS_CONFIGURATION_NUMBER)
 835                 return FALSE;
 836
 837             u8UsbConfigValue = mLOW_BYTE(mDEV_REQ_VALUE());
 838             vUsbFIFO_EPxCfg_HS();
 839
 840             // Set into 512 byte mode */
 841             //ZM_SOC_USB_MODE_CTRL_REG |= BIT2;
 842             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
 843                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT2));
 844         //    mUsbSOFMaskHS();
 845         }
 846         else
 847         {
 848             if (mLOW_BYTE(mDEV_REQ_VALUE()) > FS_CONFIGURATION_NUMBER)
 849                 return FALSE;
 850
 851             u8UsbConfigValue = mLOW_BYTE(mDEV_REQ_VALUE());
 852             vUsbFIFO_EPxCfg_FS();
 853
 854             // Set into 64 byte mode */
 855             //M_SOC_USB_MODE_CTRL_REG &= ~BIT2;
 856             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
 857                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&~BIT2));
 858         //    mUsbSOFMaskFS();
 859         }
 860         //mUsbCfgSet();
 861         //ZM_DEVICE_ADDRESS_REG |= BIT7;
 862         USB_BYTE_REG_WRITE(ZM_DEVICE_ADDRESS_OFFSET, \
 863             (USB_BYTE_REG_READ(ZM_DEVICE_ADDRESS_OFFSET)|BIT7));
 864
 865         vUsbClrEPx();
 866
 867         mUsbGlobIntEnable();
 868         mUSB_REG_OUT_INT_ENABLE();
 869
 870     }
 871
 872     eUsbCxFinishAction = ACT_DONE;
 873     return TRUE;
 874 }
 875
 876
 877 /***********************************************************************/
 878 //      bGet_interface()
 879 //      Description:
 880 //          Getting interface
 881 //      input: none
 882 //      output: TRUE or FALSE
 883 /***********************************************************************/
 884 LOCAL BOOLEAN bGet_interface(void)
 885 {
 886
 887 //    A_PRINTF("bGet_interface...\n\r");
 888     if (mUsbCfgST() == 0)
 889         return FALSE;
 890
 891     // If there exists many interfaces, Interface0,1,2,...N,
 892     // You must check & select the specific one
 893     switch (u8UsbConfigValue)
 894     {
 895         #if (HS_CONFIGURATION_NUMBER >= 1)
 896         // Configuration 1
 897         case 1:
 898             if (mDEV_REQ_INDEX() > HS_C1_INTERFACE_NUMBER)
 899                 return FALSE;
 900             break;
 901         #endif
 902         #if (HS_CONFIGURATION_NUMBER >= 2)
 903         // Configuration 2
 904         case 2:
 905             if (mDEV_REQ_INDEX2() > HS_C2_INTERFACE_NUMBER)
 906                 return FALSE;
 907             break;
 908         #endif
 909         default:
 910             return FALSE;
 911     }
 912
 913     //ZM_CBUS_FIFO_SIZE_REG = 0x1;
 914     //ZM_EP0_DATA_REG = u8UsbInterfaceAlternateSetting;
 915     USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
 916     USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, u8UsbInterfaceAlternateSetting);
 917
 918     // Restore CBus FIFO size to word size
 919     //ZM_CBUS_FIFO_SIZE_REG = 0xf;
 920     USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f);
 921
 922     u16TxRxCounter = 1; //sizeof(u8UsbInterfaceAlternateSetting);
 923     eUsbCxFinishAction = ACT_DONE;
 924     return TRUE;
 925 }
 926
 927 /***********************************************************************/
 928 //      bSet_interface()
 929 //      Description:
 930 //          1-1. If (the device stays in Configured state)
 931 //                  &(command match the alternate setting)
 932 //                      then change the interface
 933 //          1-2. else stall it
 934 //      input: none
 935 //      output: TRUE or FALSE
 936 /***********************************************************************/
 937 LOCAL BOOLEAN bSet_interface(void)
 938 {
 939 void vUsbClrEPx(void);
 940
 941     //A_PRINTF("bSet_interface...\n\r");
 942
 943     if (mUsbCfgST())
 944     {
 945
 946         // If there exists many interfaces, Interface0,1,2,...N,
 947         // You must check & select the specific one
 948         switch (mDEV_REQ_INDEX())
 949         {
 950             case 0: // Interface0
 951
 952                 if (mLOW_BYTE(mDEV_REQ_VALUE()) == mLOW_BYTE(u8ConfigDescriptorEX[mTABLE_IDX(12)]))
 953                 {
 954                     u8UsbInterfaceValue = (uint8_t) mDEV_REQ_INDEX();
 955                     u8UsbInterfaceAlternateSetting = mLOW_BYTE(mDEV_REQ_VALUE());
 956                     if (mUsbHighSpeedST())                  // First judge HS or FS??
 957                     {
 958                         vUsbFIFO_EPxCfg_HS();
 959
 960                         // Set into 512 byte mode */
 961                         USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
 962                             (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT2));
 963                     }
 964                     else
 965                     {
 966                         vUsbFIFO_EPxCfg_FS();
 967
 968                         // Set into 64 byte mode */
 969                         USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
 970                             (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&~BIT2));
 971                     }
 972                     vUsbClrEPx();
 973                     eUsbCxFinishAction = ACT_DONE;
 974
 975                     mUsbGlobIntEnable();
 976                     mUSB_REG_OUT_INT_ENABLE();
 977                     return TRUE;
 978                 }
 979         //    case 1: // Interface1
 980         //    case 2: // Interface2
 981         //    default:
 982         //        break;
 983         }
 984     }
 985     return FALSE;
 986 }
 987
 988 /***********************************************************************/
 989 //      vUsbEP0TxData()
 990 //      Description:
 991 //          1. Send data(max or short packet) to host.
 992 //      input: none
 993 //      output: none
 994 /***********************************************************************/
 995 LOCAL void vUsbEP0TxData(void)
 996 {
 997     uint8_t u8temp;
 998     uint32_t idx=0;
 999
1000     //wait a little to make sure ep0 fifo is empty before sending data out
1001     while(1)
1002     {
1003         if(idx++>0xffff) {
1004             USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, USB_BYTE_REG_READ(ZM_CX_CONFIG_STATUS_OFFSET)|BIT3);
1005             break;
1006         }
1007
1008         if(USB_BYTE_REG_READ(ZM_CX_CONFIG_STATUS_OFFSET)&BIT5)
1009         {
1010             break;
1011         }
1012     }
1013     // to keep tracking the txrx fifo
1014     // max 64 bytes for transmission one time,
1015     if (u16TxRxCounter < EP0MAXPACKETSIZE)
1016         u8temp = (uint8_t) u16TxRxCounter;
1017     else
1018         u8temp = EP0MAXPACKETSIZE;
1019
1020     u16TxRxCounter -= (uint16_t) u8temp;
1021
1022     {
1023         register uint8_t u8count;
1024         uint8_t remainder;
1025
1026         for (u8count = 0; u8count < (u8temp/4); u8count ++)
1027         {
1028             uint32_t ep0_data;
1029             uint16_t ep0_low;
1030             uint16_t ep0_high;
1031
1032             // pack data into word size
1033             ep0_low = *pu8DescriptorEX++;
1034             ep0_high = *pu8DescriptorEX++;
1035
1036             // composed the data as a word
1037             ep0_data = (ep0_high << 16) + ep0_low;
1038
1039             USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, ep0_data);
1040         }
1041
1042         remainder = u8temp % 4;
1043
1044         // Check whether there are data needed to be filled into the FIFO
1045         if (remainder == 3)
1046         {
1047             uint32_t ep0_data;
1048             uint16_t ep0_low;
1049             uint16_t ep0_high;
1050
1051             // pack data into word size
1052             ep0_low = *pu8DescriptorEX++;
1053             ep0_high = *pu8DescriptorEX++;
1054
1055             ep0_data = (ep0_high << 16) + ep0_low;
1056
1057             USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7);
1058             USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, ep0_data);
1059         }
1060         else if (remainder == 2)
1061         {
1062             USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3);
1063             USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, *pu8DescriptorEX);
1064         }
1065         else if (remainder == 1)
1066         {
1067             USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
1068             USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, *pu8DescriptorEX);
1069         }
1070
1071         // Restore CBus FIFO size to word size
1072         USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xf);
1073     }
1074
1075     // end of the data stage
1076     if (u16TxRxCounter == 0)
1077     {
1078         eUsbCxCommand = CMD_VOID;
1079         eUsbCxFinishAction = ACT_DONE;
1080     }
1081 }
1082
1083 /***********************************************************************/
1084 //      vUsbEP0RxData()
1085 //      Description:
1086 //          1. Receive data(max or short packet) from host.
1087 //      input: none
1088 //      output: none
1089 /***********************************************************************/
1090 LOCAL void vUsbEP0RxData(void)
1091 {
1092     uint8_t u8temp;
1093
1094     if (u16TxRxCounter < EP0MAXPACKETSIZE)
1095         u8temp = (uint8_t) u16TxRxCounter;
1096     else
1097         u8temp = EP0MAXPACKETSIZE;
1098
1099     u16TxRxCounter -= (uint16_t) u8temp;
1100
1101     // Receive u8Temp bytes data
1102     {
1103     register uint8_t u8count;
1104     uint8_t *p = (uint8_t *) pu8DescriptorEX;
1105
1106         for (u8count = 0; u8count < ((u8temp+3) >> 2); u8count ++)
1107         {
1108             uint32_t ep0_data;
1109
1110             ep0_data = USB_WORD_REG_READ(ZM_EP0_DATA_OFFSET);   //read usb ep0 fifo data,
1111
1112             {
1113 // skip the writing to ram if not build for rom code
1114 #if 0 //1 defined(_ROM_)
1115                 *p++ = mGetByte0(ep0_data);
1116                 *p++ = mGetByte1(ep0_data);
1117                 *p++ = mGetByte2(ep0_data);
1118                 *p++ = mGetByte3(ep0_data);
1119 #endif
1120                 fwCheckSum = fwCheckSum ^ ep0_data;
1121              }
1122         }
1123
1124         pu8DescriptorEX += (u8count << 1);
1125     }
1126
1127     // end of the data stage
1128     if (u16TxRxCounter == 0)
1129     {
1130         eUsbCxCommand = CMD_VOID;
1131         eUsbCxFinishAction = ACT_DONE;
1132     }
1133 }
1134
1135
1136 /***********************************************************************/
1137 //      vUsb_SetupDescriptor()
1138 //      Description:
1139 //          Setup the pointer to the descriptor in the SRAM and EEPROM
1140 //
1141 /***********************************************************************/
1142 LOCAL void vUsb_SetupDescriptor(void)
1143 {
1144 // eeprom exist the usb configuration is only supportted in rom version
1145 #if defined(_ROM_)
1146     //
1147     // check the offset of PID's value is correct or not, need to be defined!!, ryan
1148     //
1149
1150     if( *((uint32_t*)USB_DESC_IN_EEPROM_FLAG_ADDR) == USB_DESC_IN_EEP_PATTERN)
1151     {
1152         A_PRINTF("- custom usb config\n");
1153
1154         u8UsbDeviceDescriptor = (uint16_t *) USB_DEVICE_DESCRIPTOR_ADDR;
1155         u8String00Descriptor = (uint16_t *) USB_STRING00_DESCRIPTOR_ADDR;
1156         u8String10Descriptor = (uint16_t *) USB_STRING10_DESCRIPTOR_ADDR;
1157         u8String20Descriptor = (uint16_t *) USB_STRING20_DESCRIPTOR_ADDR;
1158         u8String30Descriptor = (uint16_t *) USB_STRING30_DESCRIPTOR_ADDR;
1159     }
1160     else
1161 #endif
1162     {
1163         u8UsbDeviceDescriptor = (uint16_t *) &UsbDeviceDescriptor;
1164         u8String00Descriptor = (uint16_t *) &String00Descriptor;
1165         u8String10Descriptor = (uint16_t *) &String10Descriptor;
1166         u8String20Descriptor = (uint16_t *) &String20Descriptor;
1167         u8String30Descriptor = (uint16_t *) &String30Descriptor;
1168     }
1169
1170     /* Point Device Qualifierdescriptors and Other Speed Descriptor
1171          *  - Device Qualifierdescriptor is located in RAM segment, extern these
1172          *    symbol at the beginning of this file
1173      */
1174 }
1175
1176
1177 /***********************************************************************/
1178 //      bStandardCommand()
1179 //      Description:
1180 //          1. Process standard command.
1181 //      input: none
1182 //      output: TRUE or FALSE
1183 /***********************************************************************/
1184 LOCAL BOOLEAN bStandardCommand(void)
1185 {
1186     switch (mDEV_REQ_REQ())                 // by Standard Request codes
1187     {
1188         case USB_GET_STATUS:
1189             return (A_USB_GET_STATUS());
1190
1191         case USB_CLEAR_FEATURE:
1192             return (A_USB_CLEAR_FEATURE());
1193
1194         case USB_SET_FEATURE:
1195             return (A_USB_SET_FEATURE());
1196
1197         case USB_SET_ADDRESS:
1198             return (A_USB_SET_ADDRESS());
1199
1200         case USB_GET_DESCRIPTOR:
1201             return (A_USB_GET_DESCRIPTOR());
1202
1203 #if 0
1204         case USB_SET_DESCRIPTOR:
1205 //            if (!bUsbEP0HaltSt)
1206             return (bSet_descriptor());
1207 #endif
1208
1209         case USB_GET_CONFIGURATION:
1210             return (A_USB_GET_CONFIG());
1211
1212         case USB_SET_CONFIGURATION:
1213             //A_PRINTF(" \n--> SET_CONFIGURATION\r\n");
1214 //            if (!bUsbEP0HaltSt)
1215 //              return (A_USB_SET_CONFIG());
1216
1217         {
1218             A_USB_SET_CONFIG();
1219
1220 #if ENABLE_SWAP_DATA_MODE
1221             // SWAP FUNCTION should be enabled while DMA engine is not working,
1222             // the best place to enable it is before we trigger the DMA
1223             MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1;
1224             MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1;
1225
1226         #if SYSTEM_MODULE_HP_EP5
1227             MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1;
1228         #endif
1229
1230         #if SYSTEM_MODULE_HP_EP6
1231             MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1;
1232         #endif
1233
1234 #endif //ENABLE_SWAP_DATA_MODE
1235
1236
1237 #if !ENABLE_STREAM_MODE
1238             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT3);
1239
1240  /*
1241  // ryan:
1242  // 04/01: bit0 could disable lpdn dma, which is good at debugging while async_fifo have problem,
1243  //            we could disable this and check the fifo_rcv_size to see if we have correct at fifo or not
1244  */
1245             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT1))); // upstream DMA enable
1246             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT0))); // downstream DMA enable
1247
1248         #if SYSTEM_MODULE_HP_EP5
1249             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)));
1250         #endif
1251
1252         #if SYSTEM_MODULE_HP_EP6
1253             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)));
1254         #endif
1255
1256 #else
1257 /////////////ENABLE_STREAM_MODE/////////////////
1258             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1259                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT1)));  // disable upstream DMA mode
1260             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1261                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT3)));  // enable upstream stream mode
1262             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,
1263                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT1)));    // enable upstream DMA mode
1264
1265         #if SYSTEM_MODULE_HP_EP1
1266             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1267                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0)));  // diable LP downstream DMA mode
1268             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1269                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT6)));    // enable LP downstream stream mode
1270             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1271                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT0)));   // enable LP downstream DMA mode
1272         #endif
1273
1274         #if SYSTEM_MODULE_HP_EP5
1275             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1276                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT8)));     // disable HP downstream DMA mode
1277             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1278                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT7)));    // enable HP downstream stream mode
1279             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1280                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8));     // enable HP downstream DMA mode
1281         #endif
1282
1283
1284         #if SYSTEM_MODULE_HP_EP6
1285             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1286                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT9)));    // disable MP downstream DMA mode
1287             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1288                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT10));      // enable MP downstream stream mode
1289             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1290                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9));    // enable MP downstream DMA mode
1291         #endif
1292
1293             USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1294                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT4)));   // define the host dma buffer size - 4096(00) 8192 (01) 16384(10) 32768(11) bytes
1295
1296             USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, USB_STREAM_MODE_TIMEOUT_CTRL);  // set stream mode timeout critirea
1297
1298             USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, USB_STREAM_MODE_AGG_CNT); // set stream mode packet buffer critirea
1299 #endif  //!ENABLE_STREAM_MODE
1300
1301
1302
1303 //extern void Magpie_init(void);
1304 //Magpie_init();
1305
1306             return TRUE;
1307         }
1308
1309         case USB_GET_INTERFACE:
1310 //            A_PRINTF(" \n--> GET_INTERFACE\r\n");
1311 //            if (!bUsbEP0HaltSt)
1312                 //return (bGet_interface());
1313             return (A_USB_GET_INTERFACE());
1314
1315         case USB_SET_INTERFACE:
1316 //            A_PRINTF(" \n--> SET_INTERFACE\r\n");
1317 //            if (!bUsbEP0HaltSt)
1318 //          return (bSet_interface());
1319 //          return (A_USB_SET_INTERFACE());
1320             A_USB_SET_INTERFACE();
1321             return TRUE;
1322     }
1323     return FALSE;
1324 }
1325
1326
1327 LOCAL void flash_read(uint16_t len, uint16_t ofset)
1328 {
1329     uint16_t i=0;
1330
1331     uint8_t buf[64];
1332     uint16_t end_addr = 0x0;
1333     uint16_t start_addr = 0x0;
1334     uint32_t ep0_data = 0x0;
1335
1336 #if 0
1337     //sanity check, just in case
1338     if(u16TxRxCounter < EP0MAXPACKETSIZE)
1339         u8temp = (uint8_t) u16TxRxCounter;
1340     else
1341
1342     if( u16TxRxCounter > 64 )
1343         len = EP0MAXPACKETSIZE;
1344     else
1345         len = u16TxRxCounter + 4-(u16TxRxCounter%4);
1346 #endif
1347
1348     start_addr = ofset;
1349     end_addr = start_addr + len;
1350
1351     A_PRINTF("read flash from %x to %x\n", ofset, end_addr);
1352
1353     USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
1354
1355     for (i = 0; start_addr < end_addr; i++, start_addr+=4)
1356     {
1357 //        A_SFLASH_READ(1, ofset, 4, buf + i*4);
1358 //        *((volatile uint32_t *)(buf+i*4)) = *(uint32_t *)(0xf000000+start_addr);
1359 //    A_PRINTF(" %08x ", *(uint32_t *)(0xf000000+start_addr));
1360     USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, *(uint32_t *)(0xf000000+start_addr));
1361     }
1362
1363 //    A_PRINTF("\n\n\r");
1364     USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT0);
1365
1366
1367
1368
1369 #if 0
1370      USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
1371
1372     for(i=0; i<len; i+4)
1373     {
1374         ep0_data = *(uint32_t *)(buf+i);
1375
1376         USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, ep0_data);
1377     }
1378
1379     USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
1380
1381     USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT0);
1382 #endif
1383 }
1384
1385 extern BOOLEAN download_enable;
1386
1387 LOCAL void VendorCommand(void)
1388 {
1389 #define cUSB_REQ_DOWNLOAD          0x30
1390 #define cUSB_REQ_DOWNLOAD_COMP     0x31
1391 #define cUSB_REQ_BOOT              0x32
1392 #define cUSB_REQ_RESERVED_1        0x33
1393 #define cUSB_REQ_RESERVED_2        0x34
1394
1395 #define cUSB_REQ_FLASH_READ        0x35
1396 #define cUSB_REQ_FLASH_READ_COMP   0x36
1397
1398 //#define ZM_FIRMWARE_ADDR           0x200000
1399
1400     void (*funcPtr)(void);
1401     uint16_t *text_addr = 0;
1402     uint32_t ep0_data = 0x0;
1403 //    static download_enable = FALSE;
1404
1405     CURRENT_PROGRAM = (uint32_t)VendorCommand;
1406
1407     switch (mDEV_REQ_REQ())
1408     {
1409         case cUSB_REQ_FLASH_READ:
1410
1411             ep0_data = *(uint32_t *)(0xf000000);
1412
1413             u16TxRxCounter = mDEV_REQ_LENGTH();
1414             pu8DescriptorEX = (uint16_t*)( (mDEV_REQ_VALUE()));
1415
1416 //            A_PRINTF("Get a flash_read (%x) request with lenght:%d, and offset %x...\n", cUSB_REQ_FLASH_READ, u16TxRxCounter, pu8DescriptorEX);
1417
1418 //            eUsbCxCommand = CMD_GET_CUSTOM_DATA;
1419
1420 #if 1
1421             flash_read(u16TxRxCounter, (uint16_t)pu8DescriptorEX);
1422 #else
1423             eUsbCxCommand = CMD_GET_CUSTOM_DATA;
1424             USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, ep0_data);
1425             USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
1426             USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT0);
1427 #endif
1428             break;
1429
1430         case cUSB_REQ_FLASH_READ_COMP:
1431
1432             ep0_data = *(uint32_t *)(0xf000004);
1433             A_PRINTF("get a upload complete request...\n");
1434
1435             //eUsbCxCommand = CMD_SET_DESCRIPTOR;
1436 //                USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
1437                 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, ep0_data);
1438                 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
1439                 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT0);
1440
1441             //download_enable = TRUE;
1442
1443             break;
1444
1445         case cUSB_REQ_DOWNLOAD:
1446             //if( download_enable )
1447             {
1448                 u16TxRxCounter = mDEV_REQ_LENGTH();
1449                 pu8DescriptorEX = (uint16_t*)( (mDEV_REQ_VALUE() << 8));
1450                 A_PRINTF("\t[cUSB_REQ_DOWNLOAD]: 0x%08x, %02x\n\r", pu8DescriptorEX, u16TxRxCounter);
1451
1452                 eUsbCxCommand = CMD_SET_DESCRIPTOR;
1453
1454             }
1455 //            else
1456 //                A_PRINTF("firmware download deny!!\n\r");
1457             break;
1458
1459         case cUSB_REQ_DOWNLOAD_COMP:
1460
1461             text_addr = (uint16_t*)( (mDEV_REQ_VALUE() << 8));
1462             A_PRINTF("\t\n\r==>[cUSB_REQ_COMP]: 0x%08x\n\r", text_addr);
1463 #if 0
1464             if (fwCheckSum != 0)
1465             {
1466                 A_PRINTF("cksum=%x", fwCheckSum);
1467                 fwCheckSum = 0;
1468                 //Return fail
1469                 DEBUG_SYSTEM_STATE |= BIT27;
1470
1471                 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
1472                 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, 1);
1473                 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
1474                 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT0);
1475             }
1476             else
1477 #endif
1478             {
1479                 /* Set EP0 Done */
1480                 //ZM_CX_CONFIG_STATUS_REG = 0x01;
1481                 fwCheckSum = 0;
1482                 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
1483                 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, 0);
1484                 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
1485                 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT0);
1486
1487                 A_PRINTF("VendorCmd: DownloadComplete!\n");
1488
1489                                 DEBUG_SYSTEM_STATE &= ~BIT27;
1490                 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x3f;
1491
1492                 // this value should be assign from host along with the DOWNLOAD_COMP in wValue
1493                 if( text_addr != 0 )
1494                     funcPtr = (void *)(text_addr);
1495
1496                 download_enable = TRUE;
1497
1498                                 // only jump to text address in ROM version
1499                                 #if defined(_ROM_)
1500                 //    funcPtr();    // jump to the firmware and never return
1501                                 #endif
1502                 //app_start();
1503                         }
1504 //            else
1505 //                A_PRINTF("Integrity is not fine!\n\r");
1506
1507             break;
1508     }
1509 }
1510
1511
1512 /***********************************************************************/
1513 //      vUsb_ep0setup()
1514 //      Description:
1515 //          1. Read 8-byte setup packet.
1516 //          2. Decode command as Standard, Class, Vendor or NOT support command
1517 //      input: none
1518 //      output: none
1519 /***********************************************************************/
1520 extern uint16_t u8HSConfigDescriptor01[];
1521 extern uint16_t u8FSConfigDescriptor01[];
1522
1523 LOCAL void vUsb_ep0setup(void)
1524 {
1525 register uint8_t ii;
1526 volatile uint32_t ep0_data;
1527 //BOOLEAN bStandardCommand(void);
1528 //BOOLEAN bClassCommand(void);
1529 //void VendorCommand(void);
1530
1531     //zcPrint._printf("\t---> %s <---\n\r", __FUNCTION__);
1532     if (UsbChirpFinish != TRUE)
1533     {
1534         UsbChirpFinish = TRUE;
1535
1536         // Setup Descriptor pointer
1537         //vUsb_SetupDescriptor();
1538         A_USB_SETUP_DESC();
1539
1540         u8OtherSpeedConfigDescriptorEX[0] = 0x0709;
1541
1542         if (mUsbHighSpeedST())                  // Judge HS or FS??
1543         {
1544             u8ConfigDescriptorEX = u8HSConfigDescriptor01;
1545
1546         // copy Device Qualifierdescriptors (from rom to sram)
1547             for (ii = 1; ii < 4; ii++)
1548             {
1549                 u8DeviceQualifierDescriptorEX[ii] = u8UsbDeviceDescriptor[ii];
1550             }
1551
1552         // Number of Other-speed Configurations
1553         // byte 9 Reserved for future use, must be zero
1554             u8DeviceQualifierDescriptorEX[4] = (u8UsbDeviceDescriptor[8] >> 8) & 0x00ff;
1555
1556          // copy Other Speed Descriptor
1557             for (ii = 1; ii < (USB_TOTAL_DESC_LEN/2); ii++)
1558             {
1559                 u8OtherSpeedConfigDescriptorEX[ii] = u8FSConfigDescriptor01[ii];
1560             }
1561
1562 #if 0
1563             MaxPktSize = HS_C1_I0_A0_EP1_MAX_PACKET;
1564         // Device stays in High Speed
1565             u8DeviceDescriptorEX = u8HSDeviceDescriptor;
1566
1567         // copy Device Qualifierdescriptors (from rom to sram)
1568             for (ii = mTABLE_WID(2) ; ii < mTABLE_WID(8); ii ++)
1569                 u8DeviceQualifierDescriptorEX[ii] = u8FSDeviceDescriptor[ii];
1570
1571         // Number of Other-speed Configurations
1572         // byte 9 Reserved for future use, must be zero
1573             u8DeviceQualifierDescriptorEX[mTABLE_IDX(8)]
1574                 = mHIGH_BYTE(u8FSDeviceDescriptor[mTABLE_IDX(17)]);
1575             u8ConfigDescriptorEX = u8HSConfigDescriptor01;
1576             u8OtherSpeedConfigDescriptorEX = u8FSConfigDescriptor01;
1577 #endif
1578         }
1579         else
1580         {
1581             u8ConfigDescriptorEX = u8FSConfigDescriptor01;
1582
1583         // copy Device Qualifierdescriptors (from rom to sram)
1584             for (ii = 1; ii < 4; ii++)
1585             {
1586                 u8DeviceQualifierDescriptorEX[ii] = u8UsbDeviceDescriptor[ii];
1587             }
1588
1589         // Number of Other-speed Configurations
1590         // byte 9 Reserved for future use, must be zero
1591             u8DeviceQualifierDescriptorEX[4] = (u8UsbDeviceDescriptor[8] >> 8) & 0x00ff;
1592
1593          // copy Other Speed Descriptor
1594             for (ii = 1; ii < (USB_TOTAL_DESC_LEN/2); ii++)
1595             {
1596                 u8OtherSpeedConfigDescriptorEX[ii] = u8HSConfigDescriptor01[ii];
1597             }
1598
1599 #if 0
1600             MaxPktSize = FS_C1_I0_A0_EP1_MAX_PACKET;
1601         // Device stays in Full Speed
1602             u8DeviceDescriptorEX = u8FSDeviceDescriptor;
1603
1604         // copy Device Qualifierdescriptors (from rom to sram)
1605             for (ii = mTABLE_WID(2) ; ii < mTABLE_WID(8); ii ++)
1606                 u8DeviceQualifierDescriptorEX[ii] = u8HSDeviceDescriptor[ii];
1607
1608         // Number of Other-speed Configurations
1609         // byte 9 Reserved for future use, must be zero
1610             u8DeviceQualifierDescriptorEX[mTABLE_IDX(8)]
1611                 = mHIGH_BYTE(u8HSDeviceDescriptor[mTABLE_IDX(17)]);
1612             u8ConfigDescriptorEX = u8FSConfigDescriptor01;
1613             u8OtherSpeedConfigDescriptorEX = u8HSConfigDescriptor01;
1614 #endif
1615         }
1616      //Change bLength
1617         u8DeviceQualifierDescriptorEX[0] = 0x060A;
1618     }
1619
1620     if( USB_BYTE_REG_READ(ZM_CX_CONFIG_STATUS_OFFSET) & BIT5)
1621     {
1622         int kkk=0;
1623         kkk++;
1624     }
1625     //ep0_data = ZM_EP0_DATA_REG;
1626     ep0_data = USB_WORD_REG_READ(ZM_EP0_DATA_OFFSET);
1627
1628     ii = mGetByte0(ep0_data);
1629
1630     ControlCmd.Direction = (uint8_t)(ii & 0x80);// xfer Direction(IN, OUT)
1631     ControlCmd.Type = (uint8_t)(ii & 0x60);     // type(Standard, Class, Vendor)
1632     ControlCmd.Object = (uint8_t)(ii & 0x03);   // Device, Interface, Endpoint
1633
1634     ControlCmd.Request = mGetByte1(ep0_data);
1635     ControlCmd.Value = mGetByte2(ep0_data) + (mGetByte3(ep0_data) << 8);
1636
1637     //ep0_data = ZM_EP0_DATA_REG;
1638     ep0_data = USB_WORD_REG_READ(ZM_EP0_DATA_OFFSET);
1639
1640     ControlCmd.Index = mGetByte0(ep0_data) + (mGetByte1(ep0_data) << 8);
1641     ControlCmd.Length = mGetByte2(ep0_data) + (mGetByte3(ep0_data) << 8);
1642
1643 //  Command Decode
1644     if (mDEV_REQ_REQ_TYPE() == (cUSB_REQTYPE_STD << bmREQ_TYPE))
1645     {                                       // standard command
1646         //if (bStandardCommand() == FALSE)
1647         if (A_USB_STANDARD_CMD() == FALSE)
1648         {
1649             eUsbCxFinishAction = ACT_STALL;
1650         }
1651     }
1652     else if (mDEV_REQ_REQ_TYPE() == (cUSB_REQTYPE_VENDOR << bmREQ_TYPE))
1653     {                                       // vendor command
1654         //VendorCommand();
1655         A_USB_VENDOR_CMD();
1656     }
1657     else
1658     {
1659     // Invalid(bad) command, Return EP0_STALL flag
1660         A_PRINTF("request not support..  stall", __FUNCTION__);
1661         eUsbCxFinishAction = ACT_STALL;
1662     }
1663
1664     //zcPrint._printf("\t<--- %s --->\n\r", __FUNCTION__);
1665 }
1666
1667
1668 /*! - init FUSB phy
1669  *
1670  */
1671 LOCAL void cFUSB200Init(void)
1672 {
1673     /* Clear USB reset interrupt */
1674     USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&0xfd));
1675
1676     // Disable all fifo interrupt
1677     /* Clear all USB OUT FIFO */
1678     USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_1_OFFSET, 0xff);
1679     USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_2_OFFSET, 0xff);
1680     USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_3_OFFSET, 0xff);
1681
1682     /* Clear all USB IN FIFO */
1683     USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_5_OFFSET, 0xff);
1684     USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, 0xff);
1685
1686     // Soft Reset
1687     //ZM_MAIN_CTRL_REG = 0x10;
1688     //ZM_MAIN_CTRL_REG &= ~0x10;
1689
1690     // Soft Reset
1691     USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, 0x10);
1692     USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, 0x0);
1693
1694     // Clear all fifo
1695     USB_BYTE_REG_WRITE(ZM_TEST_OFFSET, BIT0); // will be cleared after one cycle.
1696     USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_0_OFFSET, 0); //BIT6);  // Mask out INT status
1697
1698     // reset the specific mode
1699     USB_BYTE_REG_WRITE(ZM_VDR_SPECIFIC_MODE_OFFSET, 0x0);
1700
1701     // reset the zero-length fifo indication ? workaround...
1702     USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, 0x0);
1703
1704     // Enable Chip
1705     USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, (BIT5|BIT2));
1706
1707     USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_1_OFFSET, 0x0);
1708     USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_2_OFFSET, 0x0);
1709     USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_3_OFFSET, 0x0);
1710
1711 //    USB_WORD_REG_WRITE(0x104, 0x000000C0);
1712
1713 }
1714
1715
1716 LOCAL void _usbfifo_enable_event_isr(void)
1717 {
1718     mUSB_STATUS_IN_INT_ENABLE();
1719 }
1720
1721 LOCAL void _usbfifo_init(USB_FIFO_CONFIG *pConfig)
1722 {
1723     usbFifoConf.get_command_buf = pConfig->get_command_buf;
1724     usbFifoConf.recv_command    = pConfig->recv_command;
1725     usbFifoConf.get_event_buf   = pConfig->get_event_buf;
1726     usbFifoConf.send_event_done = pConfig->send_event_done;
1727 }
1728
1729 LOCAL void vUsb_Reg_Out(void)
1730 {
1731     uint16_t usbfifolen;
1732     uint16_t ii;
1733     volatile uint32_t *regaddr;    // = (volatile uint32_t *) ZM_CMD_BUFFER;
1734     uint16_t cmdLen;
1735     uint32_t ep4_data;
1736     VBUF *buf;
1737
1738     //mUSB_REG_OUT_INT_DISABLE();
1739
1740     buf = usbFifoConf.get_command_buf();
1741
1742     if ( buf != NULL )     // copy free
1743         regaddr = (uint32_t *)buf->desc_list->buf_addr;
1744     else
1745         goto ERR;
1746
1747     // read fifo size of the current packet.
1748     usbfifolen = USB_BYTE_REG_READ(ZM_EP4_BYTE_COUNT_LOW_OFFSET);
1749
1750     cmdLen = usbfifolen;
1751
1752     if(usbfifolen % 4)
1753         usbfifolen = (usbfifolen >> 2) + 1;
1754     else
1755         usbfifolen = usbfifolen >> 2;
1756
1757     for(ii = 0; ii < usbfifolen; ii++)
1758     {
1759         ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET);   // read fifo data out
1760         *regaddr = ep4_data;
1761         regaddr++;
1762     }
1763
1764     if ( buf != NULL )
1765     {
1766 //        zfUartSendStrAndHex((u8_t *) "cmdLen=", cmdLen);
1767 //        zfMemoryCopyInWord(buf->desc_list->buf_addr, ZM_CMD_BUFFER, usbfifolen*4);
1768         buf->desc_list->next_desc = NULL;
1769         buf->desc_list->data_offset = 0;
1770         buf->desc_list->data_size = cmdLen;
1771         buf->desc_list->control = 0;
1772         buf->next_buf = NULL;
1773         buf->buf_length = cmdLen;
1774
1775         usbFifoConf.recv_command(buf);
1776     }
1777     goto DONE;
1778 ERR:
1779 //    we might get no command buffer here?
1780 //    but if we return here, the ep4 fifo will be lock out,
1781 //    so that we still read them out but just drop it ?
1782     for(ii = 0; ii < usbfifolen; ii++)
1783     {
1784         ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET);   // read fifo data out
1785     }
1786
1787 DONE:
1788     //mUSB_STATUS_IN_INT_ENABLE();
1789
1790 }
1791
1792 LOCAL void vUsb_Status_In(void)
1793 {
1794     uint16_t count;
1795     uint16_t remainder;
1796     volatile u32_t *regaddr;
1797     u16_t RegBufLen;
1798     VBUF *evntbuf = NULL;
1799
1800     //regaddr = (volatile uint32_t *) ZM_CMD_BUFFER;
1801
1802     //mUSB_STATUS_IN_INT_DISABLE();
1803
1804     evntbuf = usbFifoConf.get_event_buf();
1805     if ( evntbuf != NULL )
1806     {
1807 //zfUartSendStr((u8_t *) "#G1\r\n");
1808 //        A_PRINTF("#G1\n\r");
1809         regaddr = VBUF_GET_DATA_ADDR(evntbuf);
1810         RegBufLen = evntbuf->buf_length;
1811 //        A_PRINTF("RegBufLen=%d\n\r", RegBufLen);
1812 //zfUartSendStrAndHex((u8_t *) "RegBufLen=", RegBufLen);
1813     }
1814     else
1815     {
1816         mUSB_STATUS_IN_INT_DISABLE();
1817 //        A_PRINTF("#G2\n\r");
1818         goto ERR_DONE;
1819     }
1820
1821     /* INT use EP3 */
1822     for(count = 0; count < (RegBufLen / 4); count++)
1823     {
1824 //zfUartSendStrAndHex((u8_t *) "data=", *regaddr);
1825         USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr);
1826         regaddr++;
1827     }
1828
1829     remainder = RegBufLen % 4;
1830
1831     if (remainder)
1832     {
1833         switch(remainder)
1834         {
1835         case 3:
1836             USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7);
1837             break;
1838         case 2:
1839             USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3);
1840             break;
1841         case 1:
1842             USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
1843             break;
1844         }
1845
1846         USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr);
1847     }
1848
1849     // Restore CBus FIFO size to word size
1850     USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
1851
1852     mUSB_EP3_XFER_DONE();
1853
1854     if ( evntbuf != NULL )
1855     {
1856         usbFifoConf.send_event_done(evntbuf);
1857     }
1858
1859 ERR_DONE:
1860     //mUSB_REG_OUT_INT_ENABLE();
1861 }
1862
1863 /////////////////////////////////////////////////////////
1864 /***********************************************************************/
1865 //      zfResetUSBFIFO()
1866 //      Description:
1867 //          1. Reset all the USB FIFO used for WLAN
1868 //      input: none
1869 //      output: none
1870 /***********************************************************************/
1871 LOCAL void zfResetUSBFIFO(void)
1872 {
1873     A_PUTS("zfResetUSBFIFO\n\r");
1874
1875 }
1876
1877 /***********************************************************************/
1878 //      zfTurnOffPower()
1879 //      Description:
1880 //          1. Function to turn off ADDA/RF power, PLL
1881 //      input: none
1882 //      output: none
1883 /***********************************************************************/
1884 LOCAL void zfTurnOffPower(void)
1885 {
1886     A_PUTS("zfTurnOffPower\n\r");
1887 #if defined(MAGPIE_ASIC)
1888 /*
1889  *  1. set CPU bypass
1890  *  2. turn off CPU PLL
1891  *  3. turn off ETH PLL
1892  *  4. disable ETH PLL bypass and update
1893  *  5. set SUSPEND_ENABLE
1894  */
1895
1896     /*HAL_WORD_REG_WRITE(MAGPIE_REG_USB_DIVIDE_ADDR,((0x8<<8)|0x8));  */
1897     /* 1. */ HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR,
1898                 (HAL_WORD_REG_READ(MAGPIE_REG_CPU_PLL_BYPASS_ADDR)|(BIT0|BIT4)));
1899              A_DELAY_USECS(100); // wait for stable
1900
1901     /* 2. */ HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR,
1902                 (HAL_WORD_REG_READ(MAGPIE_REG_CPU_PLL_ADDR)|(BIT16)));
1903
1904     /* 3. */ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR,
1905                 (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)|(BIT16)));
1906
1907     /* 4. */ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR,
1908                 (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)|(BIT16|BIT0)));
1909
1910     /* 5. */ HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR,
1911                 (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(BIT0)));
1912 #endif
1913
1914 }
1915
1916
1917 LOCAL void zfGenWatchDogEvent(void)
1918 {
1919     uint32_t event= 0x0000C600;
1920
1921     mUSB_STATUS_IN_INT_DISABLE();
1922
1923     //ZM_CBUS_FIFO_SIZE_REG = 0xf;
1924     USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f);
1925
1926     //ZM_EP3_DATA_REG = event;
1927     USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, event);
1928
1929     mUSB_EP3_XFER_DONE();
1930 }
1931
1932 LOCAL void zfJumpToBootCode(void)
1933 {
1934     extern int _start(void);
1935
1936     /* Jump to the boot code */
1937     _start();
1938 }
1939
1940 LOCAL void _usb_rom_task(void)
1941 {
1942     register uint8_t usb_interrupt_level1;
1943     register uint8_t usb_interrupt_level2;
1944     register uint8_t usb_ctrl_err_indication;
1945
1946     usb_interrupt_level1 = USB_BYTE_REG_READ(ZM_INTR_GROUP_OFFSET);
1947
1948     if (usb_interrupt_level1 & BIT6)
1949     {
1950         A_USB_GEN_WDT();
1951         A_PRINTF("Generate Event\n");
1952     }
1953
1954     if (usb_interrupt_level1 & BIT0)            //Group Byte 0
1955     {
1956         usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET);
1957
1958         // refer to FUSB200, p 48, offset:21H, bit7 description, should clear the command abort interrupt first!?
1959         if (usb_interrupt_level2 & BIT7)
1960         {
1961             USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_0_OFFSET, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET)& ~BIT7));
1962         }
1963
1964         if (usb_interrupt_level2 & BIT1)
1965         {
1966             A_PRINTF("![USB] ep0 IN in \n\r");
1967             A_USB_EP0_TX();                       // USB EP0 tx interrupt
1968         }
1969         if (usb_interrupt_level2 & BIT2)
1970         {
1971             //A_PRINTF("![USB] ep0 OUT in\n\r");
1972             A_USB_EP0_RX();                       // USB EP0 rx interrupt
1973         }
1974         if (usb_interrupt_level2 & BIT0)
1975         {
1976             //A_PRINTF("![USB] ep0 SETUP in\n\r");
1977             A_USB_EP0_SETUP();
1978         }
1979
1980         if (eUsbCxFinishAction == ACT_STALL)
1981         {
1982             USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04);
1983 //            A_PRINTF("![USB] ZM_CX_CONFIG_STATUS_REG = 0x04\n\r");
1984         }
1985         else if (eUsbCxFinishAction == ACT_DONE)
1986         {
1987             // set CX_DONE to indicate the transmistion of control frame
1988             USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01);
1989         }
1990         eUsbCxFinishAction = ACT_IDLE;
1991     }
1992
1993     if (usb_interrupt_level1 & BIT7)            //Group Byte 7
1994     {
1995         //usb_interrupt_level2 = ZM_INTR_SOURCE_7_REG;
1996         usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET);
1997
1998         if (usb_interrupt_level2 & BIT1)
1999         {
2000             vUsb_rst();
2001         }
2002         if (usb_interrupt_level2 & BIT2)
2003         {
2004             vUsb_suspend();
2005         }
2006         if (usb_interrupt_level2 & BIT3)
2007         {
2008             vUsb_resm();
2009         }
2010     }
2011
2012 }
2013
2014
2015 LOCAL void _usb_fw_task(void)
2016 {
2017     register uint8_t usb_interrupt_level1;
2018     register uint8_t usb_interrupt_level2;
2019     register uint8_t usb_ctrl_err_indication;
2020
2021     usb_interrupt_level1 = USB_BYTE_REG_READ(ZM_INTR_GROUP_OFFSET);
2022
2023 #if 0 // these endpoints are handled by DMA
2024     if (usb_interrupt_level1 & BIT5)            //Group Byte 5
2025     {
2026         vUsb_Data_In();
2027     }
2028 #endif
2029     if (usb_interrupt_level1 & BIT4)
2030     {
2031         usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_4_OFFSET);
2032         if( usb_interrupt_level2 & BIT6)
2033             A_USB_REG_OUT();//vUsb_Reg_Out();
2034     }
2035
2036     if (usb_interrupt_level1 & BIT6)
2037     {
2038         //zfGenWatchDogEvent();
2039     usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_6_OFFSET);
2040         if( usb_interrupt_level2 & BIT6)
2041              A_USB_STATUS_IN();//vUsb_Status_In();
2042     }
2043
2044     if (usb_interrupt_level1 & BIT0)            //Group Byte 0
2045     {
2046         //usb_interrupt_level2 = ZM_INTR_SOURCE_0_REG;
2047         usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET);
2048
2049         // refer to FUSB200, p 48, offset:21H, bit7 description, should clear the command abort interrupt first!?
2050         if (usb_interrupt_level2 & BIT7)
2051         {
2052             //ZM_INTR_SOURCE_0_REG &= 0x7f;       // Handle command abort
2053             USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_0_OFFSET, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET)& ~BIT7));
2054             A_PRINTF("![SOURCE_0] bit7 on\n\r");
2055         }
2056
2057         if (usb_interrupt_level2 & BIT1)
2058         {
2059             //A_PRINTF("![USB] ep0 IN in \n\r");
2060             A_USB_EP0_TX();                       // USB EP0 tx interrupt
2061         }
2062         if (usb_interrupt_level2 & BIT2)
2063         {
2064             //A_PRINTF("![USB] ep0 OUT in\n\r");
2065             A_USB_EP0_RX();                       // USB EP0 rx interrupt
2066         }
2067         if (usb_interrupt_level2 & BIT0)
2068         {
2069             //A_PRINTF("![USB] ep0 SETUP in\n\r");
2070             A_USB_EP0_SETUP();
2071             //vWriteUSBFakeData();
2072         }
2073 //        else if (usb_interrupt_level2 & BIT3)
2074         if (usb_interrupt_level2 & BIT3)
2075         {
2076             vUsb_ep0end();
2077 //            A_PRINTF("![SOURCE_0] ep0 CMD_END\n\r");
2078         }
2079         if (usb_interrupt_level2 & BIT4)
2080         {
2081             vUsb_ep0fail();
2082 //            A_PRINTF("![SOURCE_0] ep0 CMD_FAIL\n\r");
2083         }
2084         if (eUsbCxFinishAction == ACT_STALL)
2085         {
2086             // set CX_STL to stall Endpoint0 & will also clear FIFO0
2087             USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04);
2088 //            A_PRINTF("![USB] ZM_CX_CONFIG_STATUS_REG = 0x04\n\r");
2089         }
2090         else if (eUsbCxFinishAction == ACT_DONE)
2091         {
2092             // set CX_DONE to indicate the transmistion of control frame
2093             USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01);
2094         }
2095         eUsbCxFinishAction = ACT_IDLE;
2096     }
2097
2098     if (usb_interrupt_level1 & BIT7)            //Group Byte 7
2099     {
2100         //usb_interrupt_level2 = ZM_INTR_SOURCE_7_REG;
2101         usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET);
2102
2103 #if 0
2104         if (usb_interrupt_level2 & BIT7)
2105         {
2106             vUsb_Data_Out0Byte();
2107 //            A_PRINTF("![SOURCE_7] bit7 on, clear it\n\r");
2108         }
2109         if (usb_interrupt_level2 & BIT6)
2110         {
2111             vUsb_Data_In0Byte();
2112 //            A_PRINTF("![SOURCE_7] bit6 on, clear it\n\r");
2113         }
2114 #endif
2115
2116         if (usb_interrupt_level2 & BIT1)
2117         {
2118             vUsb_rst();
2119             //USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~0x2));
2120             A_PRINTF("!USB reset\n\r");
2121 //            A_PRINTF("![0x1012c]: %\n\r", USB_WORD_REG_READ(0x12c));
2122         }
2123         if (usb_interrupt_level2 & BIT2)
2124         {
2125            // TBD: the suspend resume code should put here, Ryan, 07/18
2126            //
2127            //  issue, jump back to rom code and what peripherals should we reset here?
2128            //
2129
2130                         /* Set GO_TO_SUSPEND bit to USB main control register */
2131             vUsb_suspend();
2132             A_PRINTF("!USB suspend\n\r");
2133
2134             // keep the record of suspend
2135 #if defined(PROJECT_MAGPIE)
2136             *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) = SUS_MAGIC_PATTERN;
2137 #elif defined(PROJECT_K2)
2138             HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN);
2139 #endif /* #if defined(PROJECT_MAGPIE) */
2140
2141             /* Reset USB FIFO */
2142             A_USB_RESET_FIFO();
2143
2144             /* Turn off power */
2145             A_USB_POWER_OFF();
2146
2147 // DON'T restart when not in ASIC
2148 #if defined(MAGPIE_ASIC)
2149             /* Jump to boot code */
2150             A_USB_JUMP_BOOT();
2151 #endif
2152
2153         }
2154         if (usb_interrupt_level2 & BIT3)
2155         {
2156             vUsb_resm();
2157             A_PRINTF("!USB resume\n\r");
2158         }
2159     }
2160
2161 }
2162
2163 #if 0 // old
2164
2165 void _usb_init(void)
2166 {
2167
2168 // init variables
2169 //    u16TxRxCounter = 0;
2170 //    eUsbCxCommand = CMD_VOID;
2171 //    u8UsbConfigValue = 0;
2172     u8UsbInterfaceValue = 0;
2173     u8UsbInterfaceAlternateSetting = 0;
2174 //    bUsbEP0HaltSt = FALSE;
2175 //    u16FirmwareComplete = 0;
2176 //    eUsbCxFinishAction = ACT_IDLE;
2177     UsbStatus[0] = !fBUS_POWER;
2178
2179 // init hardware
2180
2181 //    cFUSB200Init();
2182     A_USB_INIT_PHY();
2183
2184     //ZM_PHY_TEST_SELECT_REG = 0;             // Plug In
2185     USB_BYTE_REG_WRITE(ZM_PHY_TEST_SELECT_OFFSET, 0x0);
2186
2187     // reset the address, just in case...
2188     //USB_BYTE_REG_WRITE(ZM_DEVICE_ADDRESS_OFFSET, 0x0);
2189
2190 }
2191
2192 #else // new
2193
2194 #if defined(PROJECT_MAGPIE)
2195
2196 /* -  spec, ch11, reset
2197  *
2198  *  1. turn on ETH PLL and set ETH PLL to 384Mhz
2199  *  2. set "USB_DMA, USB_CORE, ETH_PLL, CPU_PLL, USB_POR reset" bit
2200  *  3. clear "ETH_PLL, CPU_PLL" reset bit
2201  *  4. set USB divider to 48, 192/16=12
2202  *  5. disable ETH PLL bypass
2203  *  6. clear USB_POR
2204  *  7. clear USB_DMA, USB_CORE
2205  *  8. enable USB_AHB_ARB
2206  *
2207  *  note: don't know why bit3, bit4 should deassert? here especially bit4?
2208  *        since if we don't deassert this, clk won't come up
2209  *
2210  */
2211 #if defined(MAGPIE_ASIC)
2212 #define RST_USB_COLD_INIT()      \
2213 {                               \
2214     /********* number of PLLDIV_LOW and PLLDIV_HIGH ***********/        \
2215     /*HAL_WORD_REG_WRITE(MAGPIE_REG_USB_DIVIDE_ADDR,((0x8<<8)|0x8));  */    \
2216     /* 1. */ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR, 0x305);                            \
2217     /* 2. */ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR,                                  \
2218                 (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)|(BIT0|BIT1|BIT2|BIT3|BIT4))); \
2219     /* 3. */ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR,                                  \
2220                 (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT1|BIT2))));            \
2221     /* 4. */ HAL_WORD_REG_WRITE(MAGPIE_REG_USB_DIVIDE_ADDR, 0x1010);                        \
2222     /* 5. */ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR, 0x0);                       \
2223     A_DELAY_USECS(100);  /* wait for clock source stable */                                 \
2224     /* 6. */ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR,                                  \
2225                 (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT0))));                 \
2226     /* 7. */ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR,                                  \
2227                 (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT3|BIT4))));            \
2228     /* 8. */ HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR,                                    \
2229                 (HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)|BIT2));                       \
2230     /* HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, ); */                                  \
2231     /* HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)|((BIT0|BIT3|BIT4))));  */  \
2232     /* HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT0|BIT3|BIT4)))); */  \
2233 }
2234
2235 /* -  back from suspend
2236  *
2237  *  1. turn on ETH PLL , 0x5600c, ~bit0
2238  *  2. clear USB SUSPEND_ENABLE, 0x56030, ~bit0
2239  *
2240  */
2241 #define RST_USB_SUSP_INIT()                                                                 \
2242 {                                                                                           \
2243     /* 1. */ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR,                             \
2244                 (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)&(~BIT0)));               \
2245     /* 2. */ HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR,                             \
2246                 (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)&(~BIT0)));               \
2247 }
2248
2249 /* -  back from watchdog
2250  *
2251  */
2252 #define RST_USB_WDT_INIT()
2253
2254
2255 #elif defined(MAGPIE_FPGA)
2256 // fpag don't have PLL, skip 1~5
2257 #define RST_USB_COLD_INIT()                                                                      \
2258 {                                                                                           \
2259     /* 6. */ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR,                                  \
2260                 (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT0))));                 \
2261     /* 7. */ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR,                                  \
2262                 (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT3|BIT4))));            \
2263     /* 8. */ HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR,                                    \
2264                 (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)|BIT2));                       \
2265     A_DELAY_USECS(100);  /* wait for clock source stable */                                 \
2266 }
2267
2268 /* -  back from suspend
2269  *
2270  */
2271 #define RST_USB_SUSP_INIT()
2272
2273 /* -  back from watchdog
2274  *
2275  */
2276 #define RST_USB_WDT_INIT()
2277
2278
2279 #endif
2280
2281
2282 #elif defined(PROJECT_K2)
2283 #define RST_USB_INIT()      \
2284 {                               \
2285     HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT12);  \
2286     A_DELAY_USECS(10); \
2287     HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)&(~BIT12));  \
2288 }
2289 #endif
2290 /*
2291     @ToDo: this is used to enable usb access internal memory, dma need this
2292     HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)&(~(BIT2))));  \
2293     A_DELAY_USECS(20); \
2294     HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)|(BIT2))); \
2295     A_DELAY_USECS(20); \
2296 */
2297
2298
2299 LOCAL void _usb_clk_init(void)
2300 {
2301     T_BOOT_TYPE mBootMode;
2302
2303     DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x31;
2304
2305     mBootMode = A_WDT_LASTBOOT();
2306
2307 #if defined(PROJECT_MAGPIE)
2308
2309     if( mBootMode == ENUM_WDT_BOOT )
2310     {
2311         RST_USB_WDT_INIT();
2312     }
2313     else if ( mBootMode == ENUM_SUSP_BOOT )
2314     {
2315         RST_USB_SUSP_INIT();
2316     }
2317     else
2318     {
2319         RST_USB_COLD_INIT();
2320     }
2321
2322 #elif defined(PROJECT_K2)
2323     if( mBootMode == ENUM_COLD_BOOT )
2324     {
2325         RST_USB_INIT();
2326     }
2327 #endif
2328
2329     DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x32;
2330
2331     //A_DELAY_USECS(300); // delay 300 micro seconds, wait for clock stable!
2332 }
2333
2334
2335 void _usb_init(void)
2336 {
2337     u32_t   cold_start;
2338
2339 //    A_PUTS("\n - _usb_init - \n\r");
2340
2341 #if defined(PROJECT_MAGPIE)
2342     //if ( *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) == WDT_MAGIC_PATTERN || *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) == SUS_MAGIC_PATTERN )
2343     if( A_WDT_LASTBOOT()!= ENUM_COLD_BOOT)
2344 #elif defined(PROJECT_K2)
2345     if (HAL_WORD_REG_READ(MAGPIE_REG_RST_STATUS_ADDR) == WDT_MAGIC_PATTERN || HAL_WORD_REG_READ(MAGPIE_REG_RST_STATUS_ADDR) == SUS_MAGIC_PATTERN)
2346 #endif /* #if defined(PROJECT_MAGPIE) */
2347         cold_start = 0;
2348     else
2349         cold_start = 1;
2350
2351     DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x30;
2352 // init variables
2353 //    u16TxRxCounter = 0;
2354 //    eUsbCxCommand = CMD_VOID;
2355 //    u8UsbConfigValue = 0;
2356     u8UsbInterfaceValue = 0;
2357     u8UsbInterfaceAlternateSetting = 0;
2358 //    bUsbEP0HaltSt = FALSE;
2359 //    u16FirmwareComplete = 0;
2360 //    eUsbCxFinishAction = ACT_IDLE;
2361     UsbStatus[0] = !fBUS_POWER;
2362
2363
2364 /*!
2365  * move the setting to A_USB_CLK_INIT(), so that we could patch these things
2366  */
2367 #if 1
2368     A_USB_CLK_INIT();
2369
2370 #else
2371
2372 #if defined(PROJECT_MAGPIE)
2373
2374 //#if defined(MAGPIE_ASIC)
2375     //
2376     // @Bug 36267 - wdt reset or other reset will reset usb phy, we need to init again here
2377     //            - this won't work at FPGA, skip this checking if build for FPGA
2378     //
2379     // @Bug 36947 - L3 fpga's reset behavior of usb is not as what I expect!, need to confirm
2380     //
2381     // ToBeNote: if (Bug36947), skip the checking and reset usb anyway, but will see the connection broken
2382 //    if (cold_start)
2383 //#endif
2384     A_USB_CLK_INIT();
2385 #elif defined(PROJECT_K2)
2386     if (cold_start)
2387     {
2388         DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x31;
2389         RST_USB_INIT();
2390     }
2391 #endif /* #if defined(PROJECT_MAGPIE) */
2392
2393 #endif
2394
2395         A_DELAY_USECS(300); // delay 300 usecs, wait for clock stable!
2396
2397         while( 1 )
2398     {
2399         /*
2400          * wait for USBSOC_HCLK_RDY tight high, indicate the 30Mhz is ready for use
2401          */
2402         if(HAL_WORD_REG_READ(0x10128)& BIT8)
2403             break;
2404
2405         //A_DELAY_USECS(200); // delay 200 micro seconds, wait for clock stable!
2406         }
2407
2408     DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x33;
2409     A_PUTS("6. usb_hclk rdy\n\r");
2410
2411     //
2412     // @Bug 36267 - wdt reset or other reset will reset usb phy, we need to init again here
2413     //
2414     // @Bug 36947 - L3 fpga's reset behavior of usb is not as what I expect!, need to confirm
2415 #if defined(PROJECT_MAGPIE)
2416
2417     // in cold or suspend boot, we do reinit the USB_PHY, skip only when watchdog start
2418     //
2419     //
2420 #if defined(MAGPIE_ASIC)
2421     if (cold_start)
2422 #endif
2423 #elif defined(PROJECT_K2)
2424     if (cold_start)
2425 #endif /* #if defined(PROJECT_MAGPIE) */
2426     {
2427         DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x34;
2428         A_USB_INIT_PHY();
2429
2430         DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x35;
2431         //ZM_PHY_TEST_SELECT_REG = 0;             // Plug In
2432         USB_BYTE_REG_WRITE(ZM_PHY_TEST_SELECT_OFFSET, 0x0);
2433
2434         // reset the address, just in case...
2435         //USB_BYTE_REG_WRITE(ZM_DEVICE_ADDRESS_OFFSET, 0x0);
2436     }
2437
2438      /* If watchdog reset happens, target needs to send a message to host through EP3 */
2439      if ( A_WDT_LASTBOOT() == ENUM_WDT_BOOT )
2440         mUSB_STATUS_IN_INT_ENABLE();
2441      else
2442         mUSB_STATUS_IN_INT_DISABLE();
2443
2444 }
2445
2446 #endif
2447
2448 ////////////////////////////////////////////////////////
2449 void usbfifo_module_install(struct usbfifo_api *apis)
2450 {
2451         /* hook in APIs */
2452     apis->_init = _usbfifo_init;
2453     apis->_enable_event_isr = _usbfifo_enable_event_isr;
2454 }
2455
2456
2457 void cmnos_usb_module_install(struct usb_api *apis)
2458 {
2459     apis->_usb_init = _usb_init;
2460     apis->_usb_rom_task = _usb_rom_task;
2461     apis->_usb_fw_task = _usb_fw_task;
2462     apis->_usb_init_phy = cFUSB200Init;
2463
2464     apis->_usb_ep0_setup = vUsb_ep0setup;
2465     apis->_usb_ep0_tx_data = vUsbEP0TxData;
2466     apis->_usb_ep0_rx_data = vUsbEP0RxData;
2467
2468     apis->_usb_get_configuration = bGet_configuration;
2469     apis->_usb_set_configuration = bSet_configuration;
2470
2471     apis->_usb_get_interface = bGet_interface;
2472     apis->_usb_set_interface = bSet_interface;
2473
2474     apis->_usb_standard_cmd = bStandardCommand;
2475     apis->_usb_vendor_cmd = VendorCommand;
2476
2477     apis->_usb_reset_fifo= zfResetUSBFIFO;
2478     apis->_usb_power_off = zfTurnOffPower;
2479     apis->_usb_gen_wdt = zfGenWatchDogEvent;
2480     apis->_usb_jump_boot = zfJumpToBootCode;
2481
2482     apis->_usb_get_descriptor = bGet_descriptor;
2483     apis->_usb_set_address = bSet_address;
2484     apis->_usb_set_feature = bSet_feature;
2485     apis->_usb_clr_feature = bClear_feature;
2486
2487     apis->_usb_get_status = bGet_status;
2488     apis->_usb_setup_desc = vUsb_SetupDescriptor;
2489
2490     apis->_usb_reg_out = vUsb_Reg_Out;
2491     apis->_usb_status_in = vUsb_Status_In;
2492
2493     apis->_usb_ep0_tx = vUsb_ep0tx;
2494     apis->_usb_ep0_rx = vUsb_ep0rx;
2495
2496     apis->_usb_clk_init = _usb_clk_init;
2497 }
2498
2499 #endif