ath9k_htc/local/patches/gcc.patch

   1 diff --git a/include/xtensa-config.h b/include/xtensa-config.h
   2 index 5ae4c80..8397564 100644
   3 --- a/include/xtensa-config.h
   4 +++ b/include/xtensa-config.h
   5 @@ -43,10 +43,7 @@
   6  #define XCHAL_HAVE_L32R                        1
   7
   8  #undef XSHAL_USE_ABSOLUTE_LITERALS
   9 -#define XSHAL_USE_ABSOLUTE_LITERALS    0
  10 -
  11 -#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
  12 -#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals.  */
  13 +#define XSHAL_USE_ABSOLUTE_LITERALS    1
  14
  15  #undef XCHAL_HAVE_MAC16
  16  #define XCHAL_HAVE_MAC16               0
  17 @@ -58,10 +55,10 @@
  18  #define XCHAL_HAVE_MUL32               1
  19
  20  #undef XCHAL_HAVE_MUL32_HIGH
  21 -#define XCHAL_HAVE_MUL32_HIGH          0
  22 +#define XCHAL_HAVE_MUL32_HIGH          1
  23
  24  #undef XCHAL_HAVE_DIV32
  25 -#define XCHAL_HAVE_DIV32               1
  26 +#define XCHAL_HAVE_DIV32               0
  27
  28  #undef XCHAL_HAVE_NSA
  29  #define XCHAL_HAVE_NSA                 1
  30 @@ -102,8 +99,6 @@
  31  #undef XCHAL_HAVE_FP_RSQRT
  32  #define XCHAL_HAVE_FP_RSQRT            0
  33
  34 -#undef XCHAL_HAVE_DFP_accel
  35 -#define XCHAL_HAVE_DFP_accel                   0
  36  #undef XCHAL_HAVE_WINDOWED
  37  #define XCHAL_HAVE_WINDOWED            1
  38
  39 @@ -118,32 +113,32 @@
  40
  41
  42  #undef XCHAL_ICACHE_SIZE
  43 -#define XCHAL_ICACHE_SIZE              16384
  44 +#define XCHAL_ICACHE_SIZE              0
  45
  46  #undef XCHAL_DCACHE_SIZE
  47 -#define XCHAL_DCACHE_SIZE              16384
  48 +#define XCHAL_DCACHE_SIZE              0
  49
  50  #undef XCHAL_ICACHE_LINESIZE
  51 -#define XCHAL_ICACHE_LINESIZE          32
  52 +#define XCHAL_ICACHE_LINESIZE          16
  53
  54  #undef XCHAL_DCACHE_LINESIZE
  55 -#define XCHAL_DCACHE_LINESIZE          32
  56 +#define XCHAL_DCACHE_LINESIZE          16
  57
  58  #undef XCHAL_ICACHE_LINEWIDTH
  59 -#define XCHAL_ICACHE_LINEWIDTH         5
  60 +#define XCHAL_ICACHE_LINEWIDTH         4
  61
  62  #undef XCHAL_DCACHE_LINEWIDTH
  63 -#define XCHAL_DCACHE_LINEWIDTH         5
  64 +#define XCHAL_DCACHE_LINEWIDTH         4
  65
  66  #undef XCHAL_DCACHE_IS_WRITEBACK
  67 -#define XCHAL_DCACHE_IS_WRITEBACK      1
  68 +#define XCHAL_DCACHE_IS_WRITEBACK      0
  69
  70
  71  #undef XCHAL_HAVE_MMU
  72  #define XCHAL_HAVE_MMU                 1
  73
  74  #undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
  75 -#define XCHAL_MMU_MIN_PTE_PAGE_SIZE    12
  76 +#define XCHAL_MMU_MIN_PTE_PAGE_SIZE    29
  77
  78
  79  #undef XCHAL_HAVE_DEBUG
  80 @@ -156,8 +151,11 @@
  81  #define XCHAL_NUM_DBREAK               2
  82
  83  #undef XCHAL_DEBUGLEVEL
  84 -#define XCHAL_DEBUGLEVEL               6
  85 +#define XCHAL_DEBUGLEVEL               4
  86 +
  87
  88 +#undef XCHAL_EXCM_LEVEL
  89 +#define XCHAL_EXCM_LEVEL                3
  90
  91  #undef XCHAL_MAX_INSTRUCTION_SIZE
  92  #define XCHAL_MAX_INSTRUCTION_SIZE     3