From 50a5ebfaff824904531a9b0b61244d11d89102e6 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Tue, 16 Sep 2014 19:38:32 +0200 Subject: [PATCH] carl9170 firmware: investigate 80/88MHz clock freezes The SoC can run up to 80/88MHz in HT40 mode. This improves throughput and timing accuracy over the 40/44MHz clock. However some devices seem to become unstable under load. Signed-off-by: Christian Lamparter --- carlfw/Kconfig | 10 ++++++++++ carlfw/src/rf.c | 4 ++++ 2 files changed, 14 insertions(+) diff --git a/carlfw/Kconfig b/carlfw/Kconfig index 656fcdb..b34d6c6 100644 --- a/carlfw/Kconfig +++ b/carlfw/Kconfig @@ -138,6 +138,16 @@ config CARL9170FW_NOISY_MAC_RESET prompt "Notify MAC RESET events" depends on CARL9170FW_FW_MAC_RESET +config CARL9170FW_80MHZ_CLOCK + def_bool n + prompt "Allow 80/88MHz clock for HT40" + depends on CARL9170FW_EXPERIMENTAL + ---help--- + The SoC can run up to 80/88MHz in HT40 mode. This improves + throughput and timing accuracy over the 40/44MHz clock. + However some devices don't have heat shields and they with + this option enabled, they become unstable under load. + config CARL9170FW_BROKEN_FEATURES def_bool n prompt "Broken Featurs" diff --git a/carlfw/src/rf.c b/carlfw/src/rf.c index e031dd8..5448abf 100644 --- a/carlfw/src/rf.c +++ b/carlfw/src/rf.c @@ -205,10 +205,14 @@ void rf_cmd(const struct carl9170_cmd *cmd, struct carl9170_rsp *resp) /* * Is the clock controlled by the PHY? */ +#ifdef CONFIG_CARL9170FW_80MHZ_CLOCK if ((fw.phy.ht_settings & EIGHTY_FLAG) == EIGHTY_FLAG) clock_set(AHB_80_88MHZ, true); else clock_set(AHB_40_44MHZ, true); +#else + clock_set(AHB_40_44MHZ, true); +#endif ret = rf_init(le32_to_cpu(cmd->rf_init.delta_slope_coeff_exp), le32_to_cpu(cmd->rf_init.delta_slope_coeff_man), -- 2.31.1