From 10280c74bd62f63b1483bf1b17d40b0eeb35845e Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Wed, 5 Jan 2011 17:14:59 +0100 Subject: [PATCH] carl9170 firmware: fix inaccurate delay calculation The internal refclock is set by the driver to either: 44MHz - when the device operates on a 2.4 GHz channel 40MHz - 5GHz Band This patch removes the previously used "80MHz" constant (that's wrong anyway since this is the HT40 AHB/CPU clock) and enhance the code so it can deal with the slight clock speed variations. Reported-by: Ignacy Gawedzki Signed-off-by: Christian Lamparter --- carlfw/include/carl9170.h | 1 + carlfw/include/timer.h | 37 +++++++++++++++++++++++++------------ carlfw/src/main.c | 2 +- carlfw/src/rf.c | 4 ++-- include/shared/hw.h | 2 ++ 5 files changed, 31 insertions(+), 15 deletions(-) diff --git a/carlfw/include/carl9170.h b/carlfw/include/carl9170.h index 6902816..b61189b 100644 --- a/carlfw/include/carl9170.h +++ b/carlfw/include/carl9170.h @@ -70,6 +70,7 @@ enum carl9170_mac_reset_state { struct firmware_context_struct { /* timer / clocks */ + unsigned int ticks_per_msec; unsigned int counter; /* main() cycles */ /* misc */ diff --git a/carlfw/include/timer.h b/carlfw/include/timer.h index bf2f310..d649719 100644 --- a/carlfw/include/timer.h +++ b/carlfw/include/timer.h @@ -35,45 +35,56 @@ enum cpu_clock_t { AHB_80_88MHZ = 3 }; -#define AR9170_TICKS_PER_MICROSECOND 80 - static inline __inline uint32_t get_clock_counter(void) { return (get(AR9170_TIMER_REG_CLOCK_HIGH) << 16) | get(AR9170_TIMER_REG_CLOCK_LOW); } -static inline __inline bool is_after_msecs(uint32_t t0, uint32_t msecs) +/* + * works only up to 97 secs [44 MHz] or 107 secs for 40 MHz + * Also, the delay wait will be affected by 2.4GHz<->5GHz + * band changes. + */ +static inline __inline bool is_after_msecs(const uint32_t t0, const uint32_t msecs) { - return (get_clock_counter() - t0) / (AR9170_TICKS_PER_MICROSECOND * 1000) > msecs; + return ((get_clock_counter() - t0) / 1000) > (msecs * fw.ticks_per_msec); } -static inline __inline void delay(uint32_t msec) +/* + * Note: Be careful with [u]delay. They won't service the + * hardware watchdog timer. It might trigger if you + * wait long enough. Also they don't terminate if sec is + * above 97 sec [44MHz] or more than 107 sec [40MHz]. + */ +static inline __inline void delay(const uint32_t msec) { - uint32_t t1, t2, dt; + uint32_t t1, t2, dt, wt; + + wt = msec * fw.ticks_per_msec; t1 = get_clock_counter(); while (1) { t2 = get_clock_counter(); - dt = (t2 - t1) / AR9170_TICKS_PER_MICROSECOND / 1000; - if (dt >= msec) + dt = (t2 - t1) / 1000; + if (dt >= wt) break; } } -static inline __inline void udelay(uint32_t usec) +static inline __inline void udelay(const uint32_t usec) { uint32_t t1, t2, dt; t1 = get_clock_counter(); while (1) { t2 = get_clock_counter(); - dt = (t2 - t1) / AR9170_TICKS_PER_MICROSECOND; - if (dt >= usec) + dt = (t2 - t1); + if (dt >= (usec * fw.ticks_per_msec)) break; } } -static inline void clock_set(const bool on, const enum cpu_clock_t _clock) +static inline void clock_set(enum cpu_clock_t _clock, bool on) { /* * Word of Warning! @@ -81,6 +92,8 @@ static inline void clock_set(const bool on, const enum cpu_clock_t _clock) * So watch out, if you need _stable_ timer interrupts. */ + fw.ticks_per_msec = GET_VAL(AR9170_PWR_PLL_ADDAC_DIV, get(AR9170_PWR_REG_PLL_ADDAC)) >> 1; + set(AR9170_PWR_REG_CLOCK_SEL, (uint32_t) ((on ? 0x70 : 0x600) | _clock)); } diff --git a/carlfw/src/main.c b/carlfw/src/main.c index b9239c8..bf6602a 100644 --- a/carlfw/src/main.c +++ b/carlfw/src/main.c @@ -169,7 +169,7 @@ static void __noreturn main_loop(void) void start(void) { - clock_set(true, AHB_40MHZ_OSC); + clock_set(AHB_40MHZ_OSC, true); /* watchdog magic pattern check */ if ((get(AR9170_PWR_REG_WATCH_DOG_MAGIC) & 0xffff0000) == 0x12340000) { diff --git a/carlfw/src/rf.c b/carlfw/src/rf.c index 9bb8394..bb74b81 100644 --- a/carlfw/src/rf.c +++ b/carlfw/src/rf.c @@ -200,9 +200,9 @@ void rf_cmd(const struct carl9170_cmd *cmd, struct carl9170_rsp *resp) fw.phy.frequency = cmd->rf_init.freq; if ((fw.phy.ht_settings & EIGHTY_FLAG) == EIGHTY_FLAG) - clock_set(true, AHB_80_88MHZ); + clock_set(AHB_80_88MHZ, true); else - clock_set(true, AHB_40_44MHZ); + clock_set(AHB_40_44MHZ, true); ret = rf_init(le32_to_cpu(cmd->rf_init.delta_slope_coeff_exp), le32_to_cpu(cmd->rf_init.delta_slope_coeff_man), diff --git a/include/shared/hw.h b/include/shared/hw.h index 1220c96..90c84a6 100644 --- a/include/shared/hw.h +++ b/include/shared/hw.h @@ -463,6 +463,8 @@ #define AR9170_PWR_REG_CHIP_REVISION (AR9170_PWR_REG_BASE + 0x010) #define AR9170_PWR_REG_PLL_ADDAC (AR9170_PWR_REG_BASE + 0x014) +#define AR9170_PWR_PLL_ADDAC_DIV_S 2 +#define AR9170_PWR_PLL_ADDAC_DIV 0xffc #define AR9170_PWR_REG_WATCH_DOG_MAGIC (AR9170_PWR_REG_BASE + 0x020) /* Faraday USB Controller */ -- 2.31.1