X-Git-Url: https://jxself.org/git/?p=carl9170fw.git;a=blobdiff_plain;f=include%2Fshared%2Fwlan.h;h=9e1324b67e08e19cc0bea538b74ed9ab0b5fb924;hp=c882ede0a3c9956dffb893a6c0a07245bb5db1c0;hb=19e4d682fca010ef72e0a304335910f670c2268a;hpb=e72388a0aa23da8bc8e24a0cbe9d523c5a9ce294 diff --git a/include/shared/wlan.h b/include/shared/wlan.h index c882ede..9e1324b 100644 --- a/include/shared/wlan.h +++ b/include/shared/wlan.h @@ -1,7 +1,7 @@ /* - * Atheros AR9170 driver + * Shared Atheros AR9170 Header * - * Hardware-specific definitions + * RX/TX meta descriptor format * * Copyright 2008, Johannes Berg * Copyright 2009, 2010, Christian Lamparter @@ -56,7 +56,8 @@ #define AR9170_RX_ENC_SOFTWARE 0x8 -#define AR9170_RX_STATUS_MODULATION_MASK 0x03 +#define AR9170_RX_STATUS_MODULATION 0x03 +#define AR9170_RX_STATUS_MODULATION_S 0 #define AR9170_RX_STATUS_MODULATION_CCK 0x00 #define AR9170_RX_STATUS_MODULATION_OFDM 0x01 #define AR9170_RX_STATUS_MODULATION_HT 0x02 @@ -66,12 +67,16 @@ #define AR9170_RX_STATUS_SHORT_PREAMBLE 0x08 #define AR9170_RX_STATUS_GREENFIELD 0x08 -#define AR9170_RX_STATUS_MPDU_MASK 0x30 +#define AR9170_RX_STATUS_MPDU 0x30 +#define AR9170_RX_STATUS_MPDU_S 4 #define AR9170_RX_STATUS_MPDU_SINGLE 0x00 #define AR9170_RX_STATUS_MPDU_FIRST 0x20 #define AR9170_RX_STATUS_MPDU_MIDDLE 0x30 #define AR9170_RX_STATUS_MPDU_LAST 0x10 +#define AR9170_RX_STATUS_CONT_AGGR 0x40 +#define AR9170_RX_STATUS_TOTAL_ERROR 0x80 + #define AR9170_RX_ERROR_RXTO 0x01 #define AR9170_RX_ERROR_OVERRUN 0x02 #define AR9170_RX_ERROR_DECRYPT 0x04 @@ -79,12 +84,11 @@ #define AR9170_RX_ERROR_WRONG_RA 0x10 #define AR9170_RX_ERROR_PLCP 0x20 #define AR9170_RX_ERROR_MMIC 0x40 -#define AR9170_RX_ERROR_FATAL 0x80 /* these are either-or */ #define AR9170_TX_MAC_PROT_RTS 0x0001 #define AR9170_TX_MAC_PROT_CTS 0x0002 -#define AR9170_TX_MAC_PROT_MASK 0x0003 +#define AR9170_TX_MAC_PROT 0x0003 #define AR9170_TX_MAC_NO_ACK 0x0004 /* if unset, MAC will only do SIFS space before frame */ @@ -115,26 +119,30 @@ #define AR9170_TX_PHY_SHORT_PREAMBLE 0x00000004 #define AR9170_TX_PHY_GREENFIELD 0x00000004 -#define AR9170_TX_PHY_BW_SHIFT 3 -#define AR9170_TX_PHY_BW_MASK (3 << AR9170_TX_PHY_BW_SHIFT) +#define AR9170_TX_PHY_BW_S 3 +#define AR9170_TX_PHY_BW (3 << AR9170_TX_PHY_BW_SHIFT) #define AR9170_TX_PHY_BW_20MHZ 0 #define AR9170_TX_PHY_BW_40MHZ 2 #define AR9170_TX_PHY_BW_40MHZ_DUP 3 -#define AR9170_TX_PHY_TX_HEAVY_CLIP_SHIFT 6 -#define AR9170_TX_PHY_TX_HEAVY_CLIP_MASK (7 << AR9170_TX_PHY_TX_HEAVY_CLIP_SHIFT) +#define AR9170_TX_PHY_TX_HEAVY_CLIP_S 6 +#define AR9170_TX_PHY_TX_HEAVY_CLIP (7 << \ + AR9170_TX_PHY_TX_HEAVY_CLIP_S) -#define AR9170_TX_PHY_TX_PWR_SHIFT 9 -#define AR9170_TX_PHY_TX_PWR_MASK (0x3f << AR9170_TX_PHY_TX_PWR_SHIFT) +#define AR9170_TX_PHY_TX_PWR_S 9 +#define AR9170_TX_PHY_TX_PWR (0x3f << \ + AR9170_TX_PHY_TX_PWR_S) -#define AR9170_TX_PHY_TXCHAIN_SHIFT 15 -#define AR9170_TX_PHY_TXCHAIN_MASK (7 << AR9170_TX_PHY_TXCHAIN_SHIFT) +#define AR9170_TX_PHY_TXCHAIN_S 15 +#define AR9170_TX_PHY_TXCHAIN (7 << \ + AR9170_TX_PHY_TXCHAIN_S) #define AR9170_TX_PHY_TXCHAIN_1 1 /* use for cck, ofdm 6/9/12/18/24 and HT if capable */ #define AR9170_TX_PHY_TXCHAIN_2 5 -#define AR9170_TX_PHY_MCS_SHIFT 18 -#define AR9170_TX_PHY_MCS_MASK (0x7f << AR9170_TX_PHY_MCS_SHIFT) +#define AR9170_TX_PHY_MCS_S 18 +#define AR9170_TX_PHY_MCS (0x7f << \ + AR9170_TX_PHY_MCS_S) #define AR9170_TX_PHY_RATE_CCK_1M 0x0 #define AR9170_TX_PHY_RATE_CCK_2M 0x1 @@ -225,6 +233,13 @@ struct ar9170_tx_hw_phy_control { } __packed; } __packed; +struct ar9170_tx_rate_info { + u8 tries:3; + u8 erp_prot:2; + u8 ampdu:1; + u8 free:2; /* free for use (e.g.:RIFS/TXOP/AMPDU) */ +} __packed; + struct carl9170_tx_superdesc { __le16 len; u8 rix; @@ -235,12 +250,13 @@ struct carl9170_tx_superdesc { u8 ampdu_commit_density:1; u8 ampdu_commit_factor:1; u8 ampdu_unused_bit:1; - u8 queue:3; + u8 queue:2; + u8 assign_seq:1; u8 vif_id:3; u8 fill_in_tsf:1; u8 cab:1; u8 padding2; - u8 tries[CARL9170_TX_MAX_RATES]; + struct ar9170_tx_rate_info ri[CARL9170_TX_MAX_RATES]; struct ar9170_tx_hw_phy_control rr[CARL9170_TX_MAX_RETRY_RATES]; } __packed; @@ -281,13 +297,21 @@ struct _ar9170_tx_hwdesc { #define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR 0x40 #define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR_S 6 -#define CARL9170_TX_SUPER_MISC_QUEUE 0x7 +#define CARL9170_TX_SUPER_MISC_QUEUE 0x3 #define CARL9170_TX_SUPER_MISC_QUEUE_S 0 +#define CARL9170_TX_SUPER_MISC_ASSIGN_SEQ 0x4 #define CARL9170_TX_SUPER_MISC_VIF_ID 0x38 #define CARL9170_TX_SUPER_MISC_VIF_ID_S 3 #define CARL9170_TX_SUPER_MISC_FILL_IN_TSF 0x40 #define CARL9170_TX_SUPER_MISC_CAB 0x80 +#define CARL9170_TX_SUPER_RI_TRIES 0x7 +#define CARL9170_TX_SUPER_RI_TRIES_S 0 +#define CARL9170_TX_SUPER_RI_ERP_PROT 0x18 +#define CARL9170_TX_SUPER_RI_ERP_PROT_S 3 +#define CARL9170_TX_SUPER_RI_AMPDU 0x20 +#define CARL9170_TX_SUPER_RI_AMPDU_S 5 + struct _carl9170_tx_superdesc { __le16 len; u8 rix; @@ -296,7 +320,7 @@ struct _carl9170_tx_superdesc { u8 ampdu_settings; u8 misc; u8 padding; - u8 tries[CARL9170_TX_MAX_RATES]; + u8 ri[CARL9170_TX_MAX_RATES]; __le32 rr[CARL9170_TX_MAX_RETRY_RATES]; } __packed; @@ -308,13 +332,15 @@ struct _carl9170_tx_superframe { #define CARL9170_TX_SUPERDESC_LEN 24 #define AR9170_TX_HWDESC_LEN 8 -#define AR9170_TX_SUPERFRAME_LEN (CARL9170_TX_HWDESC_LEN + \ - AR9170_TX_SUPERDESC_LEN) +#define CARL9170_TX_SUPERFRAME_LEN (CARL9170_TX_SUPERDESC_LEN + \ + AR9170_TX_HWDESC_LEN) struct ar9170_rx_head { u8 plcp[12]; } __packed; +#define AR9170_RX_HEAD_LEN 12 + struct ar9170_rx_phystatus { union { struct { @@ -329,12 +355,16 @@ struct ar9170_rx_phystatus { u8 phy_err; } __packed; +#define AR9170_RX_PHYSTATUS_LEN 20 + struct ar9170_rx_macstatus { u8 SAidx, DAidx; u8 error; u8 status; } __packed; +#define AR9170_RX_MACSTATUS_LEN 4 + struct ar9170_rx_frame_single { struct ar9170_rx_head phy_head; struct ieee80211_hdr i3e; @@ -382,10 +412,25 @@ enum ar9170_txq { AR9170_TXQ_BK, __AR9170_NUM_TXQ, - - AR9170_TXQ_MGMT = 4, }; +/* + * This is an workaround for several undocumented bugs. + * Don't mess with the QoS/AC <-> HW Queue map, if you don't + * know what you are doing. + * + * Known problems [hardware]: + * * The MAC does not aggregate frames on anything other + * than the first HW queue. + * * when an AMPDU is placed [in the first hw queue] and + * additional frames are already queued on a different + * hw queue, the MAC will ALWAYS freeze. + * + * In a nutshell: The hardware can either do QoS or + * Aggregation but not both at the same time. As a + * result, this makes the device pretty much useless + * for any serious 802.11n setup. + */ static const u8 ar9170_qmap[__AR9170_NUM_TXQ] = { 2, 1, 0, 3 }; #define AR9170_TXQ_DEPTH 32