X-Git-Url: https://jxself.org/git/?p=carl9170fw.git;a=blobdiff_plain;f=include%2Fshared%2Fphy.h;h=024fb42bc7877bc61eb4d7ce8e0505c6af5f5854;hp=e4beeda57371724918419f77c2ae06dd726f5684;hb=57af6796bb1328c31e362fdceb73fb22e3dca903;hpb=0629466a3ee72bd525639a57af25a0a56e26101f

diff --git a/include/shared/phy.h b/include/shared/phy.h
index e4beeda..024fb42 100644
--- a/include/shared/phy.h
+++ b/include/shared/phy.h
@@ -1,4 +1,8 @@
 /*
+ * Shared Atheros AR9170 Header
+ *
+ * PHY register map
+ *
  * Copyright (c) 2008-2009 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
@@ -135,8 +139,8 @@
 #define		AR9170_PHY_AGC_CONTROL_NO_UPDATE_NF	0x00020000
 
 #define	AR9170_PHY_REG_CCA			(AR9170_PHY_REG_BASE + 0x0064)
-#define		AR9170_PHY_CCA_MINCCA_PWR		0x0ff80000
-#define		AR9170_PHY_CCA_MINCCA_PWR_S		19
+#define		AR9170_PHY_CCA_MIN_PWR			0x0ff80000
+#define		AR9170_PHY_CCA_MIN_PWR_S		19
 #define		AR9170_PHY_CCA_THRESH62			0x0007f000
 #define		AR9170_PHY_CCA_THRESH62_S		12
 
@@ -159,8 +163,6 @@
 
 #define	AR9170_PHY_REG_SLEEP_CTR_CONTROL	(AR9170_PHY_REG_BASE + 0x0070)
 #define	AR9170_PHY_REG_SLEEP_CTR_LIMIT		(AR9170_PHY_REG_BASE + 0x0074)
-/* ??? same address ??? */
-#define	AR9170_PHY_REG_SYNTH_CONTROL		(AR9170_PHY_REG_BASE + 0x0074)
 #define	AR9170_PHY_REG_SLEEP_SCAL		(AR9170_PHY_REG_BASE + 0x0078)
 
 #define	AR9170_PHY_REG_PLL_CTL			(AR9170_PHY_REG_BASE + 0x007c)
@@ -208,13 +210,6 @@
 #define		AR9170_PHY_FRAME_CTL_TX_CLIP		0x00000038
 #define		AR9170_PHY_FRAME_CTL_TX_CLIP_S		3
 
-#define	AR9170_PHY_REG_TXPWRADJ			(AR9170_PHY_REG_BASE + 0x014c)
-#define		AR9170_PHY_TXPWRADJ_CCK_GAIN_DELTA	0x00000fc0
-#define		AR9170_PHY_TXPWRADJ_CCK_GAIN_DELTA_S	6
-#define		AR9170_PHY_TXPWRADJ_CCK_PCDAC_INDEX	0x00fc0000
-#define		AR9170_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S	18
-
-/* ??? same address ??? */
 #define	AR9170_PHY_REG_SPUR_REG			(AR9170_PHY_REG_BASE + 0x014c)
 #define		AR9170_PHY_SPUR_REG_MASK_RATE_CNTL	(0xff << 18)
 #define		AR9170_PHY_SPUR_REG_MASK_RATE_CNTL_S	18
@@ -343,8 +338,8 @@
 #define		AR9170_PHY_EXT_CCA_CYCPWR_THR1_S	9
 #define		AR9170_PHY_EXT_CCA_THRESH62		0x007f0000
 #define		AR9170_PHY_EXT_CCA_THRESH62_S		16
-#define		AR9170_PHY_EXT_MINCCA_PWR		0xff800000
-#define		AR9170_PHY_EXT_MINCCA_PWR_S		23
+#define		AR9170_PHY_EXT_CCA_MIN_PWR		0xff800000
+#define		AR9170_PHY_EXT_CCA_MIN_PWR_S		23
 
 #define	AR9170_PHY_REG_SFCORR_EXT		(AR9170_PHY_REG_BASE + 0x01c0)
 #define		AR9170_PHY_SFCORR_EXT_M1_THRESH		0x0000007f
@@ -379,9 +374,6 @@
 #define		AR9170_PHY_CALMODE_ADC_DC_PER		0x00000002
 #define		AR9170_PHY_CALMODE_ADC_DC_INIT		0x00000003
 
-/* ??? same register ??? */
-#define	AR9170_PHY_REG_M_SLEEP			(AR9170_PHY_REG_BASE + 0x01f0)
-
 #define	AR9170_PHY_REG_REFCLKDLY		(AR9170_PHY_REG_BASE + 0x01f4)
 #define	AR9170_PHY_REG_REFCLKPD			(AR9170_PHY_REG_BASE + 0x01f8)
 
@@ -431,8 +423,8 @@
 #define		AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV	0x2000
 #define		AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S	13
 
-#define	AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2	(AR9170_PHY_REG_BASE + 0x2a0c)
 #define	AR9170_PHY_REG_GAIN_2GHZ		(AR9170_PHY_REG_BASE + 0x0a0c)
+#define	AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2	(AR9170_PHY_REG_BASE + 0x2a0c)
 #define		AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN	0x00fc0000
 #define		AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN_S	18
 #define		AR9170_PHY_GAIN_2GHZ_BSW_MARGIN		0x00003c00
@@ -554,22 +546,19 @@
 #define		AR9170_PHY_FORCE_XPA_CFG_S		0
 
 #define	AR9170_PHY_REG_CH1_CCA			(AR9170_PHY_REG_BASE + 0x1064)
-#define		AR9170_PHY_CH1_MINCCA_PWR		0x0ff80000
-#define		AR9170_PHY_CH1_MINCCA_PWR_S		19
+#define		AR9170_PHY_CH1_CCA_MIN_PWR		0x0ff80000
+#define		AR9170_PHY_CH1_CCA_MIN_PWR_S		19
 
 #define	AR9170_PHY_REG_CH2_CCA			(AR9170_PHY_REG_BASE + 0x2064)
-#define		AR9170_PHY_CH2_MINCCA_PWR		0x0ff80000
-#define		AR9170_PHY_CH2_MINCCA_PWR_S		19
+#define		AR9170_PHY_CH2_CCA_MIN_PWR		0x0ff80000
+#define		AR9170_PHY_CH2_CCA_MIN_PWR_S		19
 
 #define	AR9170_PHY_REG_CH1_EXT_CCA		(AR9170_PHY_REG_BASE + 0x11bc)
-#define		AR9170_PHY_CH1_EXT_MINCCA_PWR		0xff800000
-#define		AR9170_PHY_CH1_EXT_MINCCA_PWR_S		23
+#define		AR9170_PHY_CH1_EXT_CCA_MIN_PWR		0xff800000
+#define		AR9170_PHY_CH1_EXT_CCA_MIN_PWR_S	23
 
 #define	AR9170_PHY_REG_CH2_EXT_CCA		(AR9170_PHY_REG_BASE + 0x21bc)
-#define		AR9170_PHY_CH2_EXT_MINCCA_PWR		0xff800000
-#define		AR9170_PHY_CH2_EXT_MINCCA_PWR_S		23
-
-#define	REDUCE_CHAIN_0 0x00000050
-#define	REDUCE_CHAIN_1 0x00000051
+#define		AR9170_PHY_CH2_EXT_CCA_MIN_PWR		0xff800000
+#define		AR9170_PHY_CH2_EXT_CCA_MIN_PWR_S	23
 
 #endif	/* __CARL9170_SHARED_PHY_H */