carl9170 firmware: checkpatch fixes

[carl9170fw.git] / include / shared / phy.h

diff --git a/include/shared/phy.h b/include/shared/phy.h
index cb8033dfa50412b0cd1da557bf5097b403d0c93b..e4beeda57371724918419f77c2ae06dd726f5684 100644 (file)
--- a/include/shared/phy.h
+++ b/include/shared/phy.h
@@ -18,7 +18,8 @@
 #define __CARL9170_SHARED_PHY_H
 
 #define        AR9170_PHY_REG_BASE                     (0x1bc000 + 0x9800)
-#define        AR9170_PHY_REG(_n)                      (AR9170_PHY_REG_BASE + ((_n)<<2))
+#define        AR9170_PHY_REG(_n)                      (AR9170_PHY_REG_BASE + \
+                                                ((_n) << 2))
 
 #define        AR9170_PHY_REG_TEST                     (AR9170_PHY_REG_BASE + 0x0000)
 #define                AR9170_PHY_TEST_AGC_CLR                 0x10000000
@@ -179,7 +180,8 @@
 #define        AR9170_PHY_REG_SEARCH_START_DELAY       (AR9170_PHY_REG_BASE + 0x0118)
 #define                AR9170_PHY_RX_DELAY_DELAY               0x00003fff
 
-#define        AR9170_PHY_REG_TIMING_CTRL4(_i)         (AR9170_PHY_REG_BASE + (0x0120 + ((_i) << 12)))
+#define        AR9170_PHY_REG_TIMING_CTRL4(_i)         (AR9170_PHY_REG_BASE + \
+                                               (0x0120 + ((_i) << 12)))
 #define                AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF         0x01f
 #define                AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S       0
 #define                AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF         0x7e0
@@ -308,7 +310,8 @@
 #define                AR9170_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
 
 #define        AR9170_PHY_REG_RX_CHAINMASK             (AR9170_PHY_REG_BASE + 0x01a4)
-#define        AR9170_PHY_REG_NEW_ADC_DC_GAIN_CORR(_i) (AR9170_PHY_REG_BASE + 0x01b4 + ((_i) << 12))
+#define        AR9170_PHY_REG_NEW_ADC_DC_GAIN_CORR(_i) (AR9170_PHY_REG_BASE + \
+                                                0x01b4 + ((_i) << 12))
 #define                AR9170_PHY_NEW_ADC_GAIN_CORR_ENABLE             0x40000000
 #define                AR9170_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE        0x80000000
 
@@ -383,10 +386,14 @@
 #define        AR9170_PHY_REG_REFCLKPD                 (AR9170_PHY_REG_BASE + 0x01f8)
 
 
-#define        AR9170_PHY_REG_CAL_MEAS_0(_i)           (AR9170_PHY_REG_BASE + 0x0410 + ((_i) << 12))
-#define        AR9170_PHY_REG_CAL_MEAS_1(_i)           (AR9170_PHY_REG_BASE + 0x0414 + ((_i) << 12))
-#define        AR9170_PHY_REG_CAL_MEAS_2(_i)           (AR9170_PHY_REG_BASE + 0x0418 + ((_i) << 12))
-#define        AR9170_PHY_REG_CAL_MEAS_3(_i)           (AR9170_PHY_REG_BASE + 0x041c + ((_i) << 12))
+#define        AR9170_PHY_REG_CAL_MEAS_0(_i)           (AR9170_PHY_REG_BASE + \
+                                                0x0410 + ((_i) << 12))
+#define        AR9170_PHY_REG_CAL_MEAS_1(_i)           (AR9170_PHY_REG_BASE + \
+                                                0x0414 \ + ((_i) << 12))
+#define        AR9170_PHY_REG_CAL_MEAS_2(_i)           (AR9170_PHY_REG_BASE + \
+                                                0x0418 + ((_i) << 12))
+#define        AR9170_PHY_REG_CAL_MEAS_3(_i)           (AR9170_PHY_REG_BASE + \
+                                                0x041c + ((_i) << 12))
 
 #define        AR9170_PHY_REG_CURRENT_RSSI             (AR9170_PHY_REG_BASE + 0x041c)