carlfw/include/dma.h

   1 /*
   2  * carl9170 firmware - used by the ar9170 wireless device
   3  *
   4  * This module contains DMA descriptor related definitions.
   5  *
   6  * Copyright (c) 2000-2005 ZyDAS Technology Corporation
   7  * Copyright (c) 2007-2009 Atheros Communications, Inc.
   8  * Copyright    2009    Johannes Berg <johannes@sipsolutions.net>
   9  * Copyright 2009, 2010 Christian Lamparter <chunkeey@googlemail.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License along
  22  * with this program; if not, write to the Free Software Foundation, Inc.,
  23  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  24  */
  25
  26 #ifndef __CARL9170FW_DMA_H
  27 #define __CARL9170FW_DMA_H
  28
  29 #include "config.h"
  30 #include "types.h"
  31 #include "compiler.h"
  32 #include "hw.h"
  33 #include "ieee80211.h"
  34 #include "wlan.h"
  35
  36 struct dma_desc {
  37         volatile uint16_t status;       /* Descriptor status */
  38         volatile uint16_t ctrl;         /* Descriptor control */
  39         volatile uint16_t dataSize;     /* Data size */
  40         volatile uint16_t totalLen;     /* Total length */
  41         struct dma_desc *lastAddr;      /* Last address of this chain */
  42         union {
  43                 uint8_t *_dataAddr;     /* Data buffer address */
  44                 void *dataAddr;
  45         } __packed;
  46         struct dma_desc *nextAddr;      /* Next TD address */
  47 } __packed;
  48
  49 /* (Up, Dn, 5x Tx, Rx), USB Int, (5x delayed Tx + retry), CAB, BA */
  50 #define AR9170_TERMINATOR_NUMBER_B      8
  51
  52 #define AR9170_TERMINATOR_NUMBER_INT    1
  53
  54 #ifdef CONFIG_CARL9170FW_DELAYED_TX
  55 #define AR9170_TERMINATOR_NUMBER_DELAY  6
  56 #else
  57 #define AR9170_TERMINATOR_NUMBER_DELAY  0
  58 #endif /* CONFIG_CARL9170FW_DELAYED_TX */
  59
  60 #ifdef CONFIG_CARL9170FW_CAB_QUEUE
  61 #define AR9170_TERMINATOR_NUMBER_CAB    1
  62 #else
  63 #define AR9170_TERMINATOR_NUMBER_CAB    0
  64 #endif /* CONFIG_CARL9170FW_CAB_QUEUE */
  65
  66 #ifdef CONFIG_CARL9170FW_HANDLE_BACK_REQ
  67 #define AR9170_TERMINATOR_NUMBER_BA     1
  68 #else
  69 #define AR9170_TERMINATOR_NUMBER_BA     0
  70 #endif /* CONFIG_CARL9170FW_HANDLE_BACK_REQ */
  71 #define AR9170_TERMINATOR_NUMBER (AR9170_TERMINATOR_NUMBER_B + \
  72                                   AR9170_TERMINATOR_NUMBER_INT + \
  73                                   AR9170_TERMINATOR_NUMBER_DELAY + \
  74                                   AR9170_TERMINATOR_NUMBER_CAB + \
  75                                   AR9170_TERMINATOR_NUMBER_BA)
  76
  77 #define AR9170_BLOCK_SIZE           (256 + 64)
  78
  79 #define AR9170_DESCRIPTOR_SIZE      (sizeof(struct dma_desc))
  80
  81 struct ar9170_tx_ba_frame {
  82         struct ar9170_tx_hwdesc hdr;
  83         struct ieee80211_ba ba;
  84 } __packed;
  85
  86 struct carl9170_tx_ba_superframe {
  87         struct carl9170_tx_superdesc s;
  88         struct ar9170_tx_ba_frame f;
  89 } __packed;
  90
  91 #define CARL9170_BA_BUFFER_LEN  (__roundup(sizeof(struct carl9170_tx_ba_superframe), 16))
  92 #define CARL9170_RSP_BUFFER_LEN AR9170_BLOCK_SIZE
  93
  94 struct carl9170_sram_reserved {
  95 #ifdef CONFIG_CARL9170FW_HANDLE_BACK_REQ
  96         union {
  97                 uint32_t buf[CARL9170_BA_BUFFER_LEN / sizeof(uint32_t)];
  98                 struct carl9170_tx_ba_superframe ba;
  99         } ba;
 100 #endif /* CONFIG_CARL9170FW_HANDLE_BACK_REQ */
 101         union {
 102                 uint32_t buf[CARL9170_MAX_CMD_LEN / sizeof(uint32_t)];
 103                 struct carl9170_cmd cmd;
 104         } cmd;
 105
 106         union {
 107                 uint32_t buf[CARL9170_RSP_BUFFER_LEN / sizeof(uint32_t)];
 108                 struct carl9170_rsp rsp;
 109         } rsp;
 110
 111         union {
 112                 uint32_t buf[CARL9170_INTF_NUM][AR9170_MAC_BCN_LENGTH_MAX / sizeof(uint32_t)];
 113         } bcn;
 114 };
 115
 116 /*
 117  * Memory layout in RAM:
 118  *
 119  * 0x100000                     +--
 120  *                              | terminator descriptors (dma_desc)
 121  *                              |  - Up (to USB host)
 122  *                              |  - Down (from USB host)
 123  *                              |  - TX (5x, to wifi)
 124  *                              |  - RX (from wifi)
 125  *                              |  - CAB Queue
 126  *                              |  - FW cmd & req descriptor
 127  *                              |  - BlockAck descriptor
 128  *                              |  - Delayed TX (5x)
 129  *                              | total: AR9170_TERMINATOR_NUMBER
 130  *                              +--
 131  *                              | block descriptors (dma_desc)
 132  *                              | (AR9170_BLOCK_NUMBER)
 133  * AR9170_BLOCK_BUFFER_BASE     +-- align to multiple of 64
 134  *                              | block buffers (AR9170_BLOCK_SIZE each)
 135  *                              | (AR9170_BLOCK_NUMBER)
 136  * approx. 0x117c00             +--
 137  *                              | BA buffer (128 bytes)
 138  *                              +--
 139  *                              | CMD buffer (128 bytes)
 140  *                              +--
 141  *                              | RSP buffer (320 bytes)
 142  *                              +--
 143  *                              | BEACON buffer (256 bytes)
 144  *                              +--
 145  *                              | unaccounted space / padding
 146  *                              +--
 147  * 0x18000
 148  */
 149
 150 #define AR9170_SRAM_SIZE                0x18000
 151 #define CARL9170_SRAM_RESERVED          (sizeof(struct carl9170_sram_reserved))
 152
 153 #define AR9170_FRAME_MEMORY_SIZE        (AR9170_SRAM_SIZE - CARL9170_SRAM_RESERVED)
 154
 155 #define BLOCK_ALIGNMENT         64
 156
 157 #define NONBLOCK_DESCRIPTORS_SIZE       \
 158         (AR9170_DESCRIPTOR_SIZE * (AR9170_TERMINATOR_NUMBER))
 159
 160 #define NONBLOCK_DESCRIPTORS_SIZE_ALIGNED       \
 161         (ALIGN(NONBLOCK_DESCRIPTORS_SIZE, BLOCK_ALIGNMENT))
 162
 163 #define AR9170_BLOCK_NUMBER     ((AR9170_FRAME_MEMORY_SIZE - NONBLOCK_DESCRIPTORS_SIZE_ALIGNED) / \
 164                                  (AR9170_BLOCK_SIZE + AR9170_DESCRIPTOR_SIZE))
 165
 166 struct ar9170_data_block {
 167         uint8_t data[AR9170_BLOCK_SIZE];
 168 };
 169
 170 struct ar9170_dma_memory {
 171         struct dma_desc                 terminator[AR9170_TERMINATOR_NUMBER];
 172         struct dma_desc                 block[AR9170_BLOCK_NUMBER];
 173         struct ar9170_data_block        data[AR9170_BLOCK_NUMBER] __attribute__((aligned(BLOCK_ALIGNMENT)));
 174         struct carl9170_sram_reserved   reserved __attribute__((aligned(BLOCK_ALIGNMENT)));
 175 };
 176
 177 extern struct ar9170_dma_memory dma_mem;
 178
 179 #define AR9170_DOWN_BLOCK_RATIO 2
 180 #define AR9170_RX_BLOCK_RATIO   1
 181 /* Tx 16*2 = 32 packets => 32*(5*320) */
 182 #define AR9170_TX_BLOCK_NUMBER  (AR9170_BLOCK_NUMBER * AR9170_DOWN_BLOCK_RATIO / \
 183                                 (AR9170_RX_BLOCK_RATIO + AR9170_DOWN_BLOCK_RATIO))
 184 #define AR9170_RX_BLOCK_NUMBER  (AR9170_BLOCK_NUMBER - AR9170_TX_BLOCK_NUMBER)
 185
 186 /* Error code */
 187 #define AR9170_ERR_FS_BIT       1
 188 #define AR9170_ERR_LS_BIT       2
 189 #define AR9170_ERR_OWN_BITS     3
 190 #define AR9170_ERR_DATA_SIZE    4
 191 #define AR9170_ERR_TOTAL_LEN    5
 192 #define AR9170_ERR_DATA         6
 193 #define AR9170_ERR_SEQ          7
 194 #define AR9170_ERR_LEN          8
 195
 196 /* Status bits definitions */
 197 /* Own bits definitions */
 198 #define AR9170_OWN_BITS         0x3
 199 #define AR9170_OWN_BITS_S       0
 200 #define AR9170_OWN_BITS_SW      0x0
 201 #define AR9170_OWN_BITS_HW      0x1
 202 #define AR9170_OWN_BITS_SE      0x2
 203
 204 /* Control bits definitions */
 205 #define AR9170_CTRL_TXFAIL      1
 206 #define AR9170_CTRL_BAFAIL      2
 207 #define AR9170_CTRL_FAIL        (AR9170_CTRL_TXFAIL | AR9170_CTRL_BAFAIL)
 208
 209 /* First segament bit */
 210 #define AR9170_CTRL_LS_BIT      0x100
 211 /* Last segament bit */
 212 #define AR9170_CTRL_FS_BIT      0x200
 213
 214 struct dma_queue {
 215         struct dma_desc *head;
 216         struct dma_desc *terminator;
 217 };
 218
 219 #define DESC_PAYLOAD(a)                 ((void *)a->dataAddr)
 220 #define DESC_PAYLOAD_OFF(a, offset)     ((void *)((unsigned long)(a->_dataAddr) + offset))
 221
 222 struct dma_desc *dma_unlink_head(struct dma_queue *queue);
 223 void dma_init_descriptors(void);
 224 void dma_reclaim(struct dma_queue *q, struct dma_desc *desc);
 225 void dma_put(struct dma_queue *q, struct dma_desc *desc);
 226 void dma_queue_reclaim(struct dma_queue *dst, struct dma_queue *src);
 227 void queue_dump(void);
 228 void wlan_txq_hangfix(const unsigned int queue);
 229
 230 static inline __inline bool queue_empty(struct dma_queue *q)
 231 {
 232         return q->head == q->terminator;
 233 }
 234
 235 /*
 236  * Get a completed packet with # descriptors. Return the first
 237  * descriptor and pointer the head directly by lastAddr->nextAddr
 238  */
 239 static inline __inline struct dma_desc *dma_dequeue_bits(struct dma_queue *q,
 240                                                 uint16_t bits)
 241 {
 242         struct dma_desc *desc = NULL;
 243
 244         if ((q->head->status & AR9170_OWN_BITS) == bits)
 245                 desc = dma_unlink_head(q);
 246
 247         return desc;
 248 }
 249
 250 static inline __inline struct dma_desc *dma_dequeue_not_bits(struct dma_queue *q,
 251                                                     uint16_t bits)
 252 {
 253         struct dma_desc *desc = NULL;
 254
 255         /* AR9170_OWN_BITS_HW will be filtered out here too. */
 256         if ((q->head->status & AR9170_OWN_BITS) != bits)
 257                 desc = dma_unlink_head(q);
 258
 259         return desc;
 260 }
 261
 262 #define for_each_desc_bits(desc, queue, bits)                           \
 263         while ((desc = dma_dequeue_bits(queue, bits)))
 264
 265 #define for_each_desc_not_bits(desc, queue, bits)                       \
 266         while ((desc = dma_dequeue_not_bits(queue, bits)))
 267
 268 #define for_each_desc(desc, queue)                                      \
 269         while ((desc = dma_unlink_head(queue)))
 270
 271 #define __for_each_desc_bits(desc, queue, bits)                         \
 272         for (desc = (queue)->head;                                      \
 273              (desc != (queue)->terminator &&                            \
 274              (desc->status & AR9170_OWN_BITS) == bits);                 \
 275              desc = desc->lastAddr->nextAddr)
 276
 277 #define __while_desc_bits(desc, queue, bits)                            \
 278         for (desc = (queue)->head;                                      \
 279              (!queue_empty(queue) &&                                    \
 280              (desc->status & AR9170_OWN_BITS) == bits);                 \
 281              desc = (queue)->head)
 282
 283 #define __for_each_desc(desc, queue)                                    \
 284         for (desc = (queue)->head;                                      \
 285              desc != (queue)->terminator;                               \
 286              desc = (desc)->lastAddr->nextAddr)
 287
 288 #define __for_each_desc_safe(desc, tmp, queue)                          \
 289         for (desc = (queue)->head, tmp = desc->lastAddr->nextAddr;      \
 290              desc != (queue)->terminator;                               \
 291              desc = tmp, tmp = tmp->lastAddr->nextAddr)
 292
 293 #define __while_subdesc(desc, queue)                                    \
 294         for (desc = (queue)->head;                                      \
 295              desc != (queue)->terminator;                               \
 296              desc = (desc)->nextAddr)
 297
 298 static inline __inline unsigned int queue_len(struct dma_queue *q)
 299 {
 300         struct dma_desc *desc;
 301         unsigned int i = 0;
 302
 303         __while_subdesc(desc, q)
 304                 i++;
 305
 306         return i;
 307 }
 308
 309 /*
 310  * rearm a completed packet, so it will be processed agian.
 311  */
 312 static inline __inline void dma_rearm(struct dma_desc *desc)
 313 {
 314         /* Set OWN bit to HW */
 315         desc->status = ((desc->status & (~AR9170_OWN_BITS)) |
 316                         AR9170_OWN_BITS_HW);
 317 }
 318
 319 static inline void __check_desc(void)
 320 {
 321         struct ar9170_dma_memory mem;
 322         BUILD_BUG_ON(sizeof(struct ar9170_data_block) != AR9170_BLOCK_SIZE);
 323         BUILD_BUG_ON(sizeof(struct dma_desc) != 20);
 324
 325         BUILD_BUG_ON(sizeof(mem) > AR9170_SRAM_SIZE);
 326
 327 #ifdef CONFIG_CARL9170FW_HANDLE_BACK_REQ
 328         BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, ba.buf) & (BLOCK_ALIGNMENT - 1));
 329 #endif /* CONFIG_CARL9170FW_HANDLE_BACK_REQ */
 330         BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, cmd.buf) & (BLOCK_ALIGNMENT - 1));
 331         BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, rsp.buf) & (BLOCK_ALIGNMENT - 1));
 332         BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, bcn.buf) & (BLOCK_ALIGNMENT - 1));
 333 }
 334
 335 #endif /* __CARL9170FW_DMA_H */