carlfw/include/dma.h

   1 /*
   2  * carl9170 firmware - used by the ar9170 wireless device
   3  *
   4  * This module contains DMA descriptor related definitions.
   5  *
   6  * Copyright (c) 2000-2005 ZyDAS Technology Corporation
   7  * Copyright (c) 2007-2009 Atheros Communications, Inc.
   8  * Copyright    2009    Johannes Berg <johannes@sipsolutions.net>
   9  * Copyright 2009-2011  Christian Lamparter <chunkeey@googlemail.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License along
  22  * with this program; if not, write to the Free Software Foundation, Inc.,
  23  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  24  */
  25
  26 #ifndef __CARL9170FW_DMA_H
  27 #define __CARL9170FW_DMA_H
  28
  29 #include "config.h"
  30 #include "types.h"
  31 #include "compiler.h"
  32 #include "hw.h"
  33 #include "ieee80211.h"
  34 #include "wlan.h"
  35
  36 struct dma_desc {
  37         volatile uint16_t status;       /* Descriptor status */
  38         volatile uint16_t ctrl;         /* Descriptor control */
  39         volatile uint16_t dataSize;     /* Data size */
  40         volatile uint16_t totalLen;     /* Total length */
  41         struct dma_desc *lastAddr;      /* Last address of this chain */
  42         union {
  43                 uint8_t *_dataAddr;     /* Data buffer address */
  44                 void *dataAddr;
  45         } __packed;
  46         struct dma_desc *nextAddr;      /* Next TD address */
  47 } __packed __aligned(4);
  48
  49 /* Up, Dn, 5x Tx, retry, Rx, [USB Int], (CAB), FW */
  50 #define AR9170_TERMINATOR_NUMBER_B      10
  51
  52 #define AR9170_TERMINATOR_NUMBER_INT    1
  53
  54 #ifdef CONFIG_CARL9170FW_CAB_QUEUE
  55 #define AR9170_TERMINATOR_NUMBER_CAB    CARL9170_INTF_NUM
  56 #else
  57 #define AR9170_TERMINATOR_NUMBER_CAB    0
  58 #endif /* CONFIG_CARL9170FW_CAB_QUEUE */
  59
  60 #define AR9170_TERMINATOR_NUMBER (AR9170_TERMINATOR_NUMBER_B + \
  61                                   AR9170_TERMINATOR_NUMBER_INT + \
  62                                   AR9170_TERMINATOR_NUMBER_CAB)
  63
  64 #define AR9170_BLOCK_SIZE           (256 + 64)
  65
  66 #define AR9170_DESCRIPTOR_SIZE      (sizeof(struct dma_desc))
  67
  68 struct ar9170_tx_ba_frame {
  69         struct ar9170_tx_hwdesc hdr;
  70         struct ieee80211_ba ba;
  71 } __packed;
  72
  73 struct carl9170_tx_ba_superframe {
  74         struct carl9170_tx_superdesc s;
  75         struct ar9170_tx_ba_frame f;
  76 } __packed;
  77
  78 #define CARL9170_BA_BUFFER_LEN  (__roundup(sizeof(struct carl9170_tx_ba_superframe), 16))
  79 #define CARL9170_RSP_BUFFER_LEN AR9170_BLOCK_SIZE
  80
  81 struct carl9170_sram_reserved {
  82         union {
  83                 uint32_t buf[CARL9170_BA_BUFFER_LEN / sizeof(uint32_t)];
  84                 struct carl9170_tx_ba_superframe ba;
  85         } ba;
  86
  87         union {
  88                 uint32_t buf[CARL9170_MAX_CMD_LEN / sizeof(uint32_t)];
  89                 struct carl9170_cmd cmd;
  90         } cmd;
  91
  92         union {
  93                 uint32_t buf[CARL9170_RSP_BUFFER_LEN / sizeof(uint32_t)];
  94                 struct carl9170_rsp rsp;
  95         } rsp;
  96
  97         union {
  98                 uint32_t buf[CARL9170_INTF_NUM][AR9170_MAC_BCN_LENGTH_MAX / sizeof(uint32_t)];
  99         } bcn;
 100 };
 101
 102 /*
 103  * Memory layout in RAM:
 104  *
 105  * 0x100000                     +--
 106  *                              | terminator descriptors (dma_desc)
 107  *                              |  - Up (to USB host)
 108  *                              |  - Down (from USB host)
 109  *                              |  - TX (5x, to wifi)
 110  *                              |  - AMPDU TX retry
 111  *                              |  - RX (from wifi)
 112  *                              |  - CAB Queue
 113  *                              |  - FW cmd & req descriptor
 114  *                              |  - BlockAck descriptor
 115  *                              | total: AR9170_TERMINATOR_NUMBER
 116  *                              +--
 117  *                              | block descriptors (dma_desc)
 118  *                              | (AR9170_BLOCK_NUMBER)
 119  * AR9170_BLOCK_BUFFER_BASE     +-- align to multiple of 64
 120  *                              | block buffers (AR9170_BLOCK_SIZE each)
 121  *                              | (AR9170_BLOCK_NUMBER)
 122  * approx. 0x117c00             +--
 123  *                              | BA buffer (128 bytes)
 124  *                              +--
 125  *                              | CMD buffer (128 bytes)
 126  *                              +--
 127  *                              | RSP buffer (320 bytes)
 128  *                              +--
 129  *                              | BEACON buffer (256 bytes)
 130  *                              +--
 131  *                              | unaccounted space / padding
 132  *                              +--
 133  * 0x18000
 134  */
 135
 136 #define CARL9170_SRAM_RESERVED          (sizeof(struct carl9170_sram_reserved))
 137
 138 #define AR9170_FRAME_MEMORY_SIZE        (AR9170_SRAM_SIZE - CARL9170_SRAM_RESERVED)
 139
 140 #define BLOCK_ALIGNMENT         64
 141
 142 #define NONBLOCK_DESCRIPTORS_SIZE       \
 143         (AR9170_DESCRIPTOR_SIZE * (AR9170_TERMINATOR_NUMBER))
 144
 145 #define NONBLOCK_DESCRIPTORS_SIZE_ALIGNED       \
 146         (ALIGN(NONBLOCK_DESCRIPTORS_SIZE, BLOCK_ALIGNMENT))
 147
 148 #define AR9170_BLOCK_NUMBER     ((AR9170_FRAME_MEMORY_SIZE - NONBLOCK_DESCRIPTORS_SIZE_ALIGNED) / \
 149                                  (AR9170_BLOCK_SIZE + AR9170_DESCRIPTOR_SIZE))
 150
 151 struct ar9170_data_block {
 152         uint8_t data[AR9170_BLOCK_SIZE];
 153 };
 154
 155 struct ar9170_dma_memory {
 156         struct dma_desc                 terminator[AR9170_TERMINATOR_NUMBER];
 157         struct dma_desc                 block[AR9170_BLOCK_NUMBER];
 158         struct ar9170_data_block        data[AR9170_BLOCK_NUMBER] __aligned(BLOCK_ALIGNMENT);
 159         struct carl9170_sram_reserved   reserved __aligned(BLOCK_ALIGNMENT);
 160 };
 161
 162 extern struct ar9170_dma_memory dma_mem;
 163
 164 #define AR9170_DOWN_BLOCK_RATIO 2
 165 #define AR9170_RX_BLOCK_RATIO   1
 166 /* Tx 16*2 = 32 packets => 32*(5*320) */
 167 #define AR9170_TX_BLOCK_NUMBER  (AR9170_BLOCK_NUMBER * AR9170_DOWN_BLOCK_RATIO / \
 168                                 (AR9170_RX_BLOCK_RATIO + AR9170_DOWN_BLOCK_RATIO))
 169 #define AR9170_RX_BLOCK_NUMBER  (AR9170_BLOCK_NUMBER - AR9170_TX_BLOCK_NUMBER)
 170
 171 /* Error code */
 172 #define AR9170_ERR_FS_BIT       1
 173 #define AR9170_ERR_LS_BIT       2
 174 #define AR9170_ERR_OWN_BITS     3
 175 #define AR9170_ERR_DATA_SIZE    4
 176 #define AR9170_ERR_TOTAL_LEN    5
 177 #define AR9170_ERR_DATA         6
 178 #define AR9170_ERR_SEQ          7
 179 #define AR9170_ERR_LEN          8
 180
 181 /* Status bits definitions */
 182 /* Own bits definitions */
 183 #define AR9170_OWN_BITS         0x3
 184 #define AR9170_OWN_BITS_S       0
 185 #define AR9170_OWN_BITS_SW      0x0
 186 #define AR9170_OWN_BITS_HW      0x1
 187 #define AR9170_OWN_BITS_SE      0x2
 188
 189 /* Control bits definitions */
 190 #define AR9170_CTRL_TXFAIL      1
 191 #define AR9170_CTRL_BAFAIL      2
 192 #define AR9170_CTRL_FAIL        (AR9170_CTRL_TXFAIL | AR9170_CTRL_BAFAIL)
 193
 194 /* First segament bit */
 195 #define AR9170_CTRL_LS_BIT      0x100
 196 /* Last segament bit */
 197 #define AR9170_CTRL_FS_BIT      0x200
 198
 199 struct dma_queue {
 200         struct dma_desc *head;
 201         struct dma_desc *terminator;
 202 };
 203
 204 #define DESC_PAYLOAD(a)                 ((void *)a->dataAddr)
 205 #define DESC_PAYLOAD_OFF(a, offset)     ((void *)((unsigned long)(a->_dataAddr) + offset))
 206
 207 struct dma_desc *dma_unlink_head(struct dma_queue *queue);
 208 void dma_init_descriptors(void);
 209 void dma_reclaim(struct dma_queue *q, struct dma_desc *desc);
 210 void dma_put(struct dma_queue *q, struct dma_desc *desc);
 211
 212 static inline __inline bool is_terminator(struct dma_queue *q, struct dma_desc *desc)
 213 {
 214         return q->terminator == desc;
 215 }
 216
 217 static inline __inline bool queue_empty(struct dma_queue *q)
 218 {
 219         return q->head == q->terminator;
 220 }
 221
 222 /*
 223  * Get a completed packet with # descriptors. Return the first
 224  * descriptor and pointer the head directly by lastAddr->nextAddr
 225  */
 226 static inline __inline struct dma_desc *dma_dequeue_bits(struct dma_queue *q,
 227                                                 uint16_t bits)
 228 {
 229         struct dma_desc *desc = NULL;
 230
 231         if ((q->head->status & AR9170_OWN_BITS) == bits)
 232                 desc = dma_unlink_head(q);
 233
 234         return desc;
 235 }
 236
 237 static inline __inline struct dma_desc *dma_dequeue_not_bits(struct dma_queue *q,
 238                                                     uint16_t bits)
 239 {
 240         struct dma_desc *desc = NULL;
 241
 242         /* AR9170_OWN_BITS_HW will be filtered out here too. */
 243         if ((q->head->status & AR9170_OWN_BITS) != bits)
 244                 desc = dma_unlink_head(q);
 245
 246         return desc;
 247 }
 248
 249 #define for_each_desc_bits(desc, queue, bits)                           \
 250         while ((desc = dma_dequeue_bits(queue, bits)))
 251
 252 #define for_each_desc_not_bits(desc, queue, bits)                       \
 253         while ((desc = dma_dequeue_not_bits(queue, bits)))
 254
 255 #define for_each_desc(desc, queue)                                      \
 256         while ((desc = dma_unlink_head(queue)))
 257
 258 #define __for_each_desc_bits(desc, queue, bits)                         \
 259         for (desc = (queue)->head;                                      \
 260              (desc != (queue)->terminator &&                            \
 261              (desc->status & AR9170_OWN_BITS) == bits);                 \
 262              desc = desc->lastAddr->nextAddr)
 263
 264 #define __while_desc_bits(desc, queue, bits)                            \
 265         for (desc = (queue)->head;                                      \
 266              (!queue_empty(queue) &&                                    \
 267              (desc->status & AR9170_OWN_BITS) == bits);                 \
 268              desc = (queue)->head)
 269
 270 #define __for_each_desc_continue(desc, queue)                           \
 271         for (;desc != (queue)->terminator;                              \
 272              desc = (desc)->lastAddr->nextAddr)
 273
 274 #define __for_each_desc(desc, queue)                                    \
 275         for (desc = (queue)->head;                                      \
 276              desc != (queue)->terminator;                               \
 277              desc = (desc)->lastAddr->nextAddr)
 278
 279 #define __for_each_desc_safe(desc, tmp, queue)                          \
 280         for (desc = (queue)->head, tmp = desc->lastAddr->nextAddr;      \
 281              desc != (queue)->terminator;                               \
 282              desc = tmp, tmp = tmp->lastAddr->nextAddr)
 283
 284 #define __while_subdesc(desc, queue)                                    \
 285         for (desc = (queue)->head;                                      \
 286              desc != (queue)->terminator;                               \
 287              desc = (desc)->nextAddr)
 288
 289 static inline __inline unsigned int queue_len(struct dma_queue *q)
 290 {
 291         struct dma_desc *desc;
 292         unsigned int i = 0;
 293
 294         __while_subdesc(desc, q)
 295                 i++;
 296
 297         return i;
 298 }
 299
 300 /*
 301  * rearm a completed packet, so it will be processed agian.
 302  */
 303 static inline __inline void dma_rearm(struct dma_desc *desc)
 304 {
 305         /* Set OWN bit to HW */
 306         desc->status = ((desc->status & (~AR9170_OWN_BITS)) |
 307                         AR9170_OWN_BITS_HW);
 308 }
 309
 310 static inline __inline void dma_fix_downqueue(struct dma_desc *desc)
 311 {
 312         desc->status = AR9170_OWN_BITS_HW;
 313         desc->ctrl = 0;
 314         desc->dataSize = 0;
 315         desc->totalLen = AR9170_BLOCK_SIZE;
 316         desc->lastAddr = desc;
 317 }
 318
 319 static inline void __check_desc(void)
 320 {
 321         struct ar9170_dma_memory mem;
 322         BUILD_BUG_ON(sizeof(struct ar9170_data_block) != AR9170_BLOCK_SIZE);
 323         BUILD_BUG_ON(sizeof(struct dma_desc) != 20);
 324
 325         BUILD_BUG_ON(sizeof(mem) > AR9170_SRAM_SIZE);
 326
 327         BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, ba.buf) & (BLOCK_ALIGNMENT - 1));
 328         BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, cmd.buf) & (BLOCK_ALIGNMENT - 1));
 329         BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, rsp.buf) & (BLOCK_ALIGNMENT - 1));
 330         BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, bcn.buf) & (BLOCK_ALIGNMENT - 1));
 331 }
 332
 333 #endif /* __CARL9170FW_DMA_H */