From: Oleksij Rempel Date: Mon, 28 Apr 2014 15:48:18 +0000 (+0200) Subject: make a local copy of includes needed by magpie X-Git-Tag: 1.4.0~8^2~3 X-Git-Url: https://jxself.org/git/?a=commitdiff_plain;h=ba4f945a110a5acaf9a578c63184a2b2a2c62938;p=open-ath9k-htc-firmware.git make a local copy of includes needed by magpie Signed-off-by: Oleksij Rempel --- diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/Magpie_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/Magpie_api.h new file mode 100755 index 0000000..5103d64 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/Magpie_api.h @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * @File: Magpie_api.h + * + * @Abstract: Magpie FW api + * + * @Notes: + */ + +#ifndef _MAGPIE_API_H +#define _MAGPIE_API_H + +#define MAGPIE_FW_BUILD + +#include "cmnos_api.h" +#ifdef MAGPIE_FW_BUILD +#include "vbuf_api.h" +#include "vdesc_api.h" +#include "usbfifo_api.h" +//#include "allocram_api.h" +#endif + +#include "hif_api.h" +#include "htc_api.h" +#include "wmi_svc_api.h" +#include "buf_pool_api.h" +#include "dma_engine_api.h" +#include "dma_lib.h" + +#if (SYSTEM_MODULE_SFLASH != 0) +#include "sflash_api.h" +#endif + +#define A_INDIR(sym) _A_MAGPIE_INDIRECTION_TABLE->sym + +#if SYSTEM_MODULE_DBG +/* debug Support */ +#define DBG_MODULE_INSTALL() cmnos_dbg_module_install(&_A_MAGPIE_INDIRECTION_TABLE->dbg) +#define A_DBG_INIT() A_INDIR(dbg._dbg_init()) +#define A_DBG_TASK() A_INDIR(dbg._dbg_task()) +#else +#define A_DBG_INIT() +#define A_DBG_TASK() +#endif + +/* Serial Flash support */ +#if (SYSTEM_MODULE_SFLASH != 0) +#define SFLASH_MODULE_INSTALL() cmnos_sflash_module_install(&_A_MAGPIE_INDIRECTION_TABLE->sflash) +#define A_SFLASH_INIT() A_INDIR(sflash._sflash_init()) +#define A_SFLASH_ERASE(erase_type, addr) A_INDIR(sflash._sflash_erase(erase_type, addr)) +#define A_SFLASH_PROG(addr, len, buf) A_INDIR(sflash._sflash_program(addr, len, buf)) +#define A_SFLASH_READ(fast, addr, len, buf) A_INDIR(sflash._sflash_read(fast, addr, len, buf)) +#define A_SFLASH_RDSR() A_INDIR(sflash._sflash_rdsr()) +#else +#define A_SFLASH_INIT() +#define A_SFLASH_ERASE(erase_type, addr) +#define A_SFLASH_PROG(addr, len, buf) +#define A_SFLASH_READ(fast, addr, len, buf) +#define A_SFLASH_RDSR() +#endif + +/* DMA Engine Interface */ +#define DMA_ENGINE_MODULE_INSTALL() dma_engine_module_install(&_A_MAGPIE_INDIRECTION_TABLE->dma_engine); +#define DMA_Engine_init() A_INDIR(dma_engine._init()) +#define DMA_Engine_config_rx_queue(q, nDesc, size) A_INDIR(dma_engine._config_rx_queue(q, nDesc, size)) +#define DMA_Engine_xmit_buf(q, buf) A_INDIR(dma_engine._xmit_buf(q, buf)) +#define DMA_Engine_flush_xmit(q) A_INDIR(dma_engine._flush_xmit(q)) +#define DMA_Engine_reap_recv_buf(q) A_INDIR(dma_engine._reap_recv_buf(q)) +#define DMA_Engine_return_recv_buf(q,buf) A_INDIR(dma_engine._return_recv_buf(q, buf)) +#define DMA_Engine_reap_xmited_buf(q) A_INDIR(dma_engine._reap_xmited_buf(q)) +#define DMA_Engine_swap_data(desc) A_INDIR(dma_engine._swap_data(desc)) +#define DMA_Engine_init_rx_queue(q) A_INDIR(dma_engine._init_rx_queue(q)) +#define DMA_Engine_init_tx_queue(q) A_INDIR(dma_engine._init_tx_queue(q)) +#define DMA_Engine_has_compl_packets(q) A_INDIR(dma_engine._has_compl_packets(q)) +#define DMA_Engine_desc_dump(q) A_INDIR(dma_engine._desc_dump(q)) +#define DMA_Engine_get_packet(q) A_INDIR(dma_engine._get_packet(q)) +#define DMA_Engine_reclaim_packet(q,desc) A_INDIR(dma_engine._reclaim_packet(q,desc)) +#define DMA_Engine_put_packet(q,desc) A_INDIR(dma_engine._put_packet(q,desc)) + +/*DMA Library support for GMAC & PCI(E)*/ +#define DMA_LIB_MODULE_INSTALL() dma_lib_module_install(&_A_MAGPIE_INDIRECTION_TABLE->dma_lib) +#define dma_lib_tx_init(eng_no, if_type) A_INDIR(dma_lib.tx_init(eng_no, if_type)) +#define dma_lib_rx_init(eng_no, if_type) A_INDIR(dma_lib.rx_init(eng_no, if_type)) +#define dma_lib_rx_config(eng_no, desc, gran) A_INDIR(dma_lib.rx_config(eng_no, desc, gran)) +#define dma_lib_tx_start(eng_no) A_INDIR(dma_lib.tx_start(eng_no)) +#define dma_lib_rx_start(eng_no) A_INDIR(dma_lib.rx_start(eng_no)) +#define dma_lib_intr_status(if_type) A_INDIR(dma_lib.intr_status(if_type)) +#define dma_lib_hard_xmit(eng_no, buf) A_INDIR(dma_lib.hard_xmit(eng_no, buf)) +#define dma_lib_flush_xmit(eng_no) A_INDIR(dma_lib.flush_xmit(eng_no)) +#define dma_lib_xmit_done(eng_no) A_INDIR(dma_lib.xmit_done(eng_no)) +#define dma_lib_reap_xmitted(eng_no) A_INDIR(dma_lib.reap_xmitted(eng_no)) +#define dma_lib_reap_recv(eng_no) A_INDIR(dma_lib.reap_recv(eng_no)) +#define dma_lib_return_recv(eng_no, buf) A_INDIR(dma_lib.return_recv(eng_no, buf)) +#define dma_lib_recv_pkt(eng_no) A_INDIR(dma_lib.recv_pkt(eng_no)) + +/* HIF PCI Api's */ +#define hif_pci_boot_init() A_INDIR(hif_pci.pci_boot_init()) +#define hif_pci_init(pConfig) A_INDIR(hif_pci.pci_init(pConfig)) +#define hif_pci_reset() A_INDIR(hif_pci.pci_reset()) +#define hif_pci_enable() A_INDIR(hif_pci.pci_enable()) +#define hif_pci_get_pipe(eng) A_INDIR(hif_pci.pci_get_pipe(eng)) +#define hif_pci_get_tx_eng(pipe) A_INDIR(hif_pci.pci_get_tx_eng(pipe)) +#define hif_pci_get_rx_eng(pipe) A_INDIR(hif_pci.pci_get_rx_eng(pipe)) +#define hif_pci_reap_recv(sc, eng_no) A_INDIR(hif_pci.pci_reap_recv(sc, eng_no)) +#define hif_pci_reap_xmitted(sc, eng_no) A_INDIR(hif_pci.pci_reap_xmitted(sc, eng_no)) + +/* HIF support */ +#define HIF_MODULE_INSTALL() generic_hif_module_install(&_A_MAGPIE_INDIRECTION_TABLE->hif) +#define HIF_init(pConfig) A_INDIR(hif._init(pConfig)) +#define HIF_shutdown(h) A_INDIR(hif._shutdown(h)) +#define HIF_register_callback(h, pConfig) A_INDIR(hif._register_callback(h, pConfig)) +#define HIF_start(h) A_INDIR(hif._start(h)) +#define HIF_config_pipe(h, pipe, desc_list) A_INDIR(hif._config_pipe(h, pipe, desc_list)) +#define HIF_send_buffer(h, pipe, buf) A_INDIR(hif._send_buffer(h, pipe, buf)) +#define HIF_return_recv_buf(h, pipe, buf) A_INDIR(hif._return_recv_buf(h, pipe, buf)) +#define HIF_isr_handler(h) A_INDIR(hif._isr_handler(h)) +#define HIF_is_pipe_supported(h, pipe) A_INDIR(hif._is_pipe_supported(h, pipe)) +#define HIF_get_max_msg_len(h, pipe) A_INDIR(hif._get_max_msg_len(h, pipe)) +#define HIF_get_reserved_headroom(h) A_INDIR(hif._get_reserved_headroom(h)) +#define HIF_get_default_pipe(h,u,d) A_INDIR(hif._get_default_pipe(h,u,d)) +typedef void (*HIF_INSTALL_FUNC_T)(struct hif_api *apis); + +/* VBUF APIs */ +#ifdef MAGPIE_FW_BUILD +#define VBUF_MODULE_INSTALL() vbuf_module_install(&_A_MAGPIE_INDIRECTION_TABLE->vbuf) +#define VBUF_init(nBuf) A_INDIR(vbuf._init(nBuf)) +#define VBUF_alloc_vbuf() A_INDIR(vbuf._alloc_vbuf()) +#define VBUF_free_vbuf(buf) A_INDIR(vbuf._free_vbuf(buf)) +#endif + +/* VDESC APIs */ +#ifdef MAGPIE_FW_BUILD +#define VDESC_MODULE_INSTALL() vdesc_module_install(&_A_MAGPIE_INDIRECTION_TABLE->vdesc) +#define VDESC_init(nDesc) A_INDIR(vdesc._init(nDesc)) +#define VDESC_alloc_vdesc() A_INDIR(vdesc._alloc_vdesc()) +#define VDESC_get_hw_desc(desc) A_INDIR(vdesc._get_hw_desc(desc)) +#define VDESC_swap_vdesc(dst, src) A_INDIR(vdesc._swap_vdesc(dst, src)) +#endif + +#define HTC_MODULE_INSTALL() htc_module_install(&_A_MAGPIE_INDIRECTION_TABLE->htc) +#define HTC_init(SetupComplete, pConfig) A_INDIR(htc._HTC_Init(SetupComplete, pConfig)) +#define HTC_Shutdown(h) A_INDIR(htc._HTC_Shutdown(h)) +#define HTC_RegisterService(h, s) A_INDIR(htc._HTC_RegisterService(h, s)) +#define HTC_Ready(h) A_INDIR(htc._HTC_Ready(h)) +#define HTC_SendMsg(h, endpt, buf) A_INDIR(htc._HTC_SendMsg(h, endpt, buf)) +#define HTC_ReturnBuffers(h, endpt, buf) A_INDIR(htc._HTC_ReturnBuffers(h, endpt, buf)) +#define HTC_ReturnBuffersList(h, endpt, hd) A_INDIR(htc._HTC_ReturnBuffersList(h, endpt, hd)) +#define HTC_GetReservedHeadroom(h) A_INDIR(htc._HTC_GetReservedHeadroom(h)) + +#define HTC_NotifyTargetInserted(h) +#define HTC_NotifyTargetDetached(h) + +/* WMI SVC module */ +#define WMI_SERVICE_MODULE_INSTALL() WMI_service_module_install(&_A_MAGPIE_INDIRECTION_TABLE->wmi_svc_api) +#define WMI_Init(pCfg) A_INDIR(wmi_svc_api._WMI_Init(pCfg)) +#define WMI_RegisterDispatchTable(h,pT) A_INDIR(wmi_svc_api._WMI_RegisterDispatchTable(h, pT)) +#define WMI_AllocEvent(h,ec,len) A_INDIR(wmi_svc_api._WMI_AllocEvent(h, ec, len)) +#define WMI_SendEvent(h,ev,id,seq,len) A_INDIR(wmi_svc_api._WMI_SendEvent(h, ev, id, seq, len)) +#define WMI_GetPendingEventsCount() A_INDIR(wmi_svc_api._WMI_GetPendingEventsCount()) +#define WMI_GetControlEp() A_INDIR(wmi_svc_api._WMI_GetControlEp()) +#define WMI_SendCompleteHandler(ep, buf) A_INDIR(wmi_svc_api._WMI_SendCompleteHandler(ep, buf)) +#define WMI_Shutdown(h) A_INDIR(wmi_svc_api._WMI_Shutdown(h)) + +/* USB FIFO module */ +#define USBFIFO_MODULE_INSTALL() usbfifo_module_install(&_A_MAGPIE_INDIRECTION_TABLE->usbfifo_api) +#define USBFIFO_init(pConfig) A_INDIR(usbfifo_api._init(pConfig)) +#define USBFIFO_enable_event_isr() A_INDIR(usbfifo_api._enable_event_isr()) + +/* BUF pool module */ +#define BUF_POOL_MODULE_INSTALL() buf_pool_module_install(&_A_MAGPIE_INDIRECTION_TABLE->buf_pool) +#define BUF_Pool_init(h) A_INDIR(buf_pool._init(h)) +#define BUF_Pool_shutdown(h) A_INDIR(buf_pool._shutdown(h)) +#define BUF_Pool_create_pool(h, id, nItems, nSize) A_INDIR(buf_pool._create_pool(h, id, nItems, nSize)) +#define BUF_Pool_alloc_buf(h, id, reserve) A_INDIR(buf_pool._alloc_buf(h, id, reserve)) +#define BUF_Pool_alloc_buf_align(h, id, reserve,align) A_INDIR(buf_pool._alloc_buf_align(h, id, reserve,align)) +#define BUF_Pool_free_buf(h, id, buf) A_INDIR(buf_pool._free_buf(h, id, buf)) + +/* + * This defines the layout of the indirection table, which + * is used to access exported APIs of various modules. The + * layout is shared across ROM and RAM code. RAM code may + * call into ROM and ROM code may call into RAM. Because + * of the latter, existing offsets must not change for the + * lifetime of a revision of ROM; but new members may be + * added at the end. + */ +typedef struct _A_magpie_indirection_table { + _A_cmnos_indirection_table_t cmnos; + +//#if SYSTEM_MODULE_DBG + struct dbg_api dbg; // move to firmware not in cmnos +//#endif + struct hif_api hif; + struct htc_apis htc; + WMI_SVC_APIS wmi_svc_api; + struct usbfifo_api usbfifo_api; + struct buf_pool_api buf_pool; +#ifdef MAGPIE_FW_BUILD + struct vbuf_api vbuf; + struct vdesc_api vdesc; + struct allocram_api allocram; +#endif + struct dma_engine_api dma_engine; + struct dma_lib_api dma_lib; + +#if SYSTEM_MODULE_PCI + struct hif_pci_api hif_pci; +#endif + // structure to be added after this.... +#if (SYSTEM_MODULE_SFLASH != 0) + struct sflash_api sflash; +#endif +} _A_magpie_indirection_table_t; + +extern _A_magpie_indirection_table_t _indir_tbl; +#define _A_MAGPIE_INDIRECTION_TABLE_SIZE sizeof(_A_magpie_indirection_table_t) +#if defined(__mips__) +#define _A_MAGPIE_INDIRECTION_TABLE ((_A_magpie_indirection_table_t *)0x700) +#else +#define _A_MAGPIE_INDIRECTION_TABLE (&_indir_tbl) +#endif + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/adf_nbuf_pvt.h b/target_firmware/magpie_fw_dev/target/inc/magpie/adf_nbuf_pvt.h new file mode 100755 index 0000000..8c5f406 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/adf_nbuf_pvt.h @@ -0,0 +1,459 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * (c) Copyright Atheros Communications + * FreeBSD specific prototypes + */ +#ifndef _ADF_NBUF_PVT_H +#define _ADF_NBUF_PVT_H + +#include +//#include +#include +//#include + +#define __ADF_NBUF_NULL NULL +#define __ADF_NBUF_CTX_BUF + +typedef VBUF * __adf_nbuf_t; + +/** + * queue head + */ +typedef struct __adf_nbuf_qhead { + VBUF *head; + VBUF *tail; + a_uint32_t qlen; +}__adf_nbuf_qhead_t; + +typedef __adf_nbuf_qhead_t __adf_nbuf_queue_t; + +__adf_nbuf_t +__adf_nbuf_alloc(adf_os_size_t size, + a_uint32_t reserve, a_uint32_t align); + +void +__adf_nbuf_free(__adf_nbuf_t buf); + +#ifndef _ROM_ +a_uint8_t * +__adf_nbuf_push_head(__adf_nbuf_t buf, adf_os_size_t size); + +a_uint8_t * +__adf_nbuf_pull_head(__adf_nbuf_t buf, adf_os_size_t size); + +a_uint8_t * +__adf_nbuf_put_tail(__adf_nbuf_t buf, adf_os_size_t size); +#endif + +void +__adf_nbuf_trim_tail(__adf_nbuf_t buf, adf_os_size_t size); + +__adf_nbuf_t +__adf_nbuf_realloc_headroom(__adf_nbuf_t buf, + a_uint32_t headroom); + +__adf_nbuf_t +__adf_nbuf_realloc_tailroom(__adf_nbuf_t buf, + a_uint32_t tailroom); + +__adf_nbuf_t +__adf_nbuf_expand(__adf_nbuf_t buf, + a_uint32_t headroom, a_uint32_t tailroom); + +__adf_nbuf_t +__adf_nbuf_copy(__adf_nbuf_t src); + +__adf_nbuf_t +__adf_nbuf_unshare(__adf_nbuf_t src); + +void +__adf_nbuf_frag_info(__adf_nbuf_t buf, adf_os_sglist_t *sg); + +#ifndef _ROM_ +a_uint8_t * +__adf_nbuf_get_priv(__adf_nbuf_t buf); +#endif + +void +__adf_nbuf_queue_add(__adf_nbuf_qhead_t *qhead, + __adf_nbuf_t buf); + +__adf_nbuf_t +__adf_nbuf_queue_remove(__adf_nbuf_qhead_t *qhead); + +a_uint32_t +__adf_nbuf_tx_cksum_info(__adf_nbuf_t buf, + a_uint8_t **hdr_off, + a_uint8_t **where); + +void +__adf_nbuf_set_rx_cksum(__adf_nbuf_t buf, adf_nbuf_rx_cksum_t *cksum); +void +__adf_nbuf_get_tso_info(__adf_nbuf_t buf, adf_nbuf_tso_t *tso); + +a_status_t +__adf_nbuf_get_vlan_info(adf_net_handle_t hdl, + __adf_nbuf_t buf, + adf_net_vlanhdr_t *vlan); + +void +__adf_nbuf_dmamap_info(__adf_os_dma_map_t bmap, adf_os_dmamap_info_t *sg); + +/** + * @brief return the last mbuf + * + * @param m0 + * + * @return struct mbuf* + */ +#ifndef _ROM_ +VDESC * +__adf_nbuf_last(VBUF *buf); +#endif + +/** + * @brief num bytes in the head + * + * @param adf_nbuf + * + * @return num of bytes available + */ +#ifndef _ROM_ +a_uint32_t +__adf_nbuf_headroom(__adf_nbuf_t buf); +#endif + +/** + * @brief num of bytes available in the tail excluding the priv + * portion + * + * @param adf_nbuf + * + * @return num of bytes + */ +#ifndef _ROM_ +a_uint32_t +__adf_nbuf_tailroom(__adf_nbuf_t buf); +#endif + +/** + * @brief get the entire packet length + * + * @param adf_nbuf + * + * @return total length of packet (sum of all frag lengths) + */ +#ifndef _ROM_ +a_uint32_t +__adf_nbuf_len(__adf_nbuf_t buf); +#endif + +/** + * @brief Clone the nbuf (will not create writeable copies) + * + * @param adf_nbuf + * + * @return Read-only copy of the nbuf (including clusters) + */ +__adf_nbuf_t +__adf_nbuf_clone(__adf_nbuf_t src); + +void +__adf_nbuf_cat(__adf_nbuf_t dst, __adf_nbuf_t src); + + +/* + * @brief check if the mbuf is cloned or not + * + * @param buf + * + * @return a_bool_t + */ +a_bool_t +__adf_nbuf_is_cloned(__adf_nbuf_t buf); + +/** + * @brief This will return the header's addr & m_len + */ +#ifndef _ROM_ +void +__adf_nbuf_peek_header(__adf_nbuf_t buf, a_uint8_t **addr, + a_uint32_t *len); +#endif + +/** + * @brief init the queue + * @param qhead + */ +void +__adf_nbuf_queue_init(__adf_nbuf_qhead_t *qhead); + +/** + * @brief return the length of queue + * @param adf_qhead + * + * @return length + * + */ +a_uint32_t +__adf_nbuf_queue_len(__adf_nbuf_qhead_t *qhead); + +/** + * @brief returns the first guy in the Q + * @param qhead + * + * @return (NULL if the Q is empty) + */ +#ifndef _ROM_ +__adf_nbuf_t +__adf_nbuf_queue_first(__adf_nbuf_queue_t *qhead); + +/** + * @brief return the next packet from packet chain + * + * @param buf (packet) + * + * @return (NULL if no packets are there) + */ +__adf_nbuf_t +__adf_nbuf_queue_next(__adf_nbuf_t buf); +#endif + +/** + * @brief check if the queue is empty or not + * + * @param qhead + * + * @return a_bool_t + */ +a_bool_t +__adf_nbuf_is_queue_empty(__adf_nbuf_qhead_t *qhead); + +__adf_nbuf_t +__adf_nbuf_create_frm_frag(__adf_nbuf_queue_t *head); +void +__adf_nbuf_split_to_frag(__adf_nbuf_t buf, __adf_nbuf_queue_t *qhead); + +#ifdef _ROM_ + +/** + * @brief This will return the header's addr & m_len + */ +static inline void +__adf_nbuf_peek_header(__adf_nbuf_t buf, a_uint8_t **addr, + a_uint32_t *len) +{ + VDESC *desc = buf->desc_list; + + *addr = desc->buf_addr + desc->data_offset; + *len = desc->data_size; +} + +/** + * @brief return the last mbuf + * + * @param m0 + * + * @return struct mbuf* + */ +static inline VDESC * +__adf_nbuf_last(VBUF *buf) +{ + VDESC *desc = buf->desc_list; + + //for(; desc->next_desc != NULL; desc = desc->next_desc) + // ; + while(desc->next_desc != NULL) + { + desc = desc->next_desc; + } + + return desc; +} + +/** + * @brief num bytes in the head + * + * @param adf_nbuf + * + * @return num of bytes available + */ +static inline a_uint32_t +__adf_nbuf_headroom(__adf_nbuf_t buf) +{ + return buf->desc_list->data_offset; +} + +/** + * @brief num of bytes available in the tail excluding the priv + * portion + * + * @param adf_nbuf + * + * @return num of bytes + */ + +static inline a_uint32_t +__adf_nbuf_tailroom(__adf_nbuf_t buf) +{ + VDESC *last_desc = __adf_nbuf_last(buf); + + return last_desc->buf_size - last_desc->data_offset - last_desc->data_size; +} + +/** + * @brief get the entire packet length + * + * @param adf_nbuf + * + * @return total length of packet (sum of all frag lengths) + */ +static inline a_uint32_t +__adf_nbuf_len(__adf_nbuf_t buf) +{ + return buf->buf_length; +} + +/** + * @brief put data in the head + * + * @param buf + * @param len (how much data to put) + * + * @return new data pointer ,NULL if the len is more than the + * space available in the head frag. + */ +static inline a_uint8_t * +__adf_nbuf_push_head(__adf_nbuf_t buf, adf_os_size_t len) +{ + a_uint8_t *ptr = NULL; + VDESC *desc = buf->desc_list; + + desc->data_offset -= len; + desc->data_size += len; + buf->buf_length += len; + ptr = desc->buf_addr + desc->data_offset; + return(ptr); +} + +/** + * + * @brief add data in the end of tail + * + * @param buf + * @param len (how much data to put) + * + * @return previous tail (data+len),NULL if the len is more than + * space available + */ +static inline a_uint8_t * +__adf_nbuf_put_tail(__adf_nbuf_t buf, adf_os_size_t len) +{ + a_uint8_t *tail = NULL; + VDESC *last_desc = __adf_nbuf_last(buf); + + tail = last_desc->buf_addr + last_desc->data_offset + last_desc->data_size; + last_desc->data_size += len; + buf->buf_length += len; + + return tail; +} + +/** + * @brief strip data from head + * + * @param adf_nbuf + * @param len (how much data to rip) + * + * @return new data pointer + */ +static inline a_uint8_t * +__adf_nbuf_pull_head(__adf_nbuf_t buf, adf_os_size_t len) +{ + a_uint8_t *ptr = NULL; + VDESC *desc = buf->desc_list; + + desc->data_offset += len; + desc->data_size -= len; + buf->buf_length -= len; + ptr = desc->buf_addr + desc->data_offset; + + return ptr; +} + +/** + * @brief retrieve the priv space pointer from nbuf + * + * @param buf (nbuf to attach the priv space) + * + * @return uint8_t* ( pointer to the data ) + */ +static inline a_uint8_t * +__adf_nbuf_get_priv(__adf_nbuf_t buf) +{ + //adf_os_assert(buf != NULL); + + return buf->ctx; +} + +/** + * @brief returns the first guy in the Q + * @param qhead + * + * @return (NULL if the Q is empty) + */ +static inline __adf_nbuf_t +__adf_nbuf_queue_first(__adf_nbuf_queue_t *qhead) +{ + return qhead->head; +} +/** + * @brief return the next packet from packet chain + * + * @param buf (packet) + * + * @return (NULL if no packets are there) + */ +static inline __adf_nbuf_t +__adf_nbuf_queue_next(__adf_nbuf_t buf) +{ + return buf->next_buf; +} + +#endif + +#endif + diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/allocram_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/allocram_api.h new file mode 100755 index 0000000..2413f3a --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/allocram_api.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __ALLOCRAM_API_H__ +#define __ALLOCRAM_API_H__ + +/* API for Target-side startup-time RAM allocations */ + +struct allocram_api { + /* + * Initialize allocram, providing it with a block of RAM + * (an "arena") from which to allocate. + * + * If arena_start is 0, a default start -- the end of + * the application's text & data -- is used. + * + * If arena_sz is 0, a default size -- which uses most + * of physical RAM beyond arena_start -- is used. + * + * Return value is reserved for future use -- it's an arena handle. + */ + void *(* cmnos_allocram_init)(void *arena_start, A_UINT32 arena_sz); + + /* + * Allocate nbytes of memory, returning a pointer to the start + * of the allocated block. Allocation size is rounded up to the + * nearest A_CACHE_LINE_SIZE and the returned address similarly + * aligned. + * + * There is no need to check the return value from this function. + * A failure to satisfy a RAM allocation request is treated as a + * fatal error. + * + * Allocations are expected to occur only during startup; this + * API does not, for instance, guarantee atomicity with respect + * to allocations that might (foolishly) be attempted from + * interrupt handlers. + * + * The "which_arena" parameter is currently unused, and should + * be set to 0 -- only a single arena is currently supported. + */ + void *(* cmnos_allocram)(void *which_arena, A_UINT32 nbytes); + + void (* cmnos_allocram_debug)(void); +}; + +extern void allocram_module_install(struct allocram_api *api); + + +#endif /* __ALLOCRAM_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/athos_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/athos_api.h new file mode 100755 index 0000000..010dd63 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/athos_api.h @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __ATHOS_API_H__ +#define __ATHOS_API_H__ + +/* + * This file contains wrappers to OS operating system functions + * that are available in the Athos version of the operating system. + * + * Target software must always use these wrappers to access OS + * services -- it may not access any OS services directly. + * + * These wrappers are intended to provide OS-independence for applications. + * Using this header file, an application should be able to compile and + * fully link without any other OS header files, source files, or + * binary files. + */ + +#include +#include "dt_defs.h" +#include "cmnos_api.h" +//#include "HIF_api.h" +//#include "vbuf_api.h" +//#include "vdesc_api.h" +//#include "htc_api.h" +#include "Magpie_api.h" + +/* ROM Patch API */ + + +/* HTC API */ + + +/* WMI Adaptive API - required for WMI SVCs as they refer some of them*/ + + +/* WLAN WMI API - required for WMI SVCs and others...*/ + +#if 0 +#define A_INDIR(sym) _A_OS_INDIRECTION_TABLE->sym + +/* HIF support */ +#define HIF_MODULE_INSTALL() hif_module_install(&_A_OS_INDIRECTION_TABLE->hif) +#define HIF_init(pConfig) A_INDIR(hif._init(pConfig)) +#define HIF_start() A_INDIR(hif._start()) +#define HIF_config_pipe(pipe, desc_list) A_INDIR(hif._config_pipe(pipe, desc_list)) +#define HIF_send_buffer(pipe, buf) A_INDIR(hif._send_buffer(pipe, buf)) +#define HIF_return_recv_buf(pipe, buf) A_INDIR(hif._return_recv_buf(pipe, buf)) +#define HIF_isr_handler() A_INDIR(hif._isr_handler()) +#define HIF_is_pipe_supported(pipe) A_INDIR(hif._is_pipe_supported(pipe)) + +/* VBUF APIs */ +#define VBUF_MODULE_INSTALL() vbuf_module_install(&_A_OS_INDIRECTION_TABLE->vbuf) +#define VBUF_init(dataAddr, nBuf) A_INDIR(vbuf._init(dataAddr, nBuf)) +#define VBUF_alloc_vbuf() A_INDIR(vbuf._alloc_vbuf()) +#define VBUF_free_vbuf(buf) A_INDIR(vbuf._free_vbuf(buf)) + +/* VDESC APIs */ +#define VDESC_MODULE_INSTALL() vdesc_module_install(&_A_OS_INDIRECTION_TABLE->vdesc) +#define VDESC_init(dataAddr, nTxDesc, nRxDesc) A_INDIR(vdesc._init(dataAddr, nTxDesc, nRxDesc)) +#define VDESC_alloc_vdesc(type) A_INDIR(vdesc._alloc_vdesc(type)) +#define VDESC_get_hw_desc(type, desc) A_INDIR(vdesc._get_hw_desc(type, desc)) +//#define VDESC_free_vdesc(buf) A_INDIR(vdesc._free_vdesc(buf)) + +#define HTC_MODULE_INSTALL() htc_module_install(&_A_OS_INDIRECTION_TABLE->htc) +//#define HTC_init(dataAddr, SetupComplete, RecvBufferSize) A_INDIR(htc._HTC_Init(dataAddr, SetupComplete, RecvBufferSize)) +#define HTC_init(dataAddr, SetupComplete, pConfig) A_INDIR(htc._HTC_Init(dataAddr, SetupComplete, pConfig)) +#define HTC_RegisterService(s) A_INDIR(htc._HTC_RegisterService(s)) +#define HTC_Ready() A_INDIR(htc._HTC_Ready()) +#define HTC_SendMsg(endpt, buf) A_INDIR(htc._HTC_SendMsg(endpt, buf)) +#define HTC_ReturnBuffers(endpt, buf) A_INDIR(htc._HTC_ReturnBuffers(endpt, buf)) + +#if 0 +/* WMI SVC module */ +#define WMI_SERVICE_MODULE_INSTALL() WMI_service_module_install(&_A_OS_INDIRECTION_TABLE->wmi_svc_api) +#define WMI_Init(dataAddr, pCfg) A_INDIR(wmi_svc_api._WMI_Init(dataAddr, pCfg)) +#define WMI_RegisterDispatchTable(pT) A_INDIR(wmi_svc_api._WMI_RegisterDispatchTable(pT)) +#define WMI_AllocEvent(ec,len) A_INDIR(wmi_svc_api._WMI_AllocEvent(ec, len)) +#define WMI_SendEvent(ev,id,seq,len) A_INDIR(wmi_svc_api._WMI_SendEvent(ev, id, seq, len)) +#define WMI_GetPendingEventsCount() A_INDIR(wmi_svc_api._WMI_GetPendingEventsCount()) +#define WMI_GetControlEp() A_INDIR(wmi_svc_api._WMI_GetControlEp()) +#define WMI_SendCompleteHandler(ep, buf) A_INDIR(wmi_svc_api._WMI_SendCompleteHandler(ep, buf)) +#endif + +/* + * This defines the layout of the indirection table, which + * is used to access exported APIs of various modules. The + * layout is shared across ROM and RAM code. RAM code may + * call into ROM and ROM code may call into RAM. Because + * of the latter, existing offsets must not change for the + * lifetime of a revision of ROM; but new members may be + * added at the end. + */ +typedef struct _A_athos_indirection_table { + _A_cmnos_indirection_table_t cmnos; + + /* TBD: to be added */ + struct hif_api hif; + struct vbuf_api vbuf; + struct vdesc_api vdesc; + struct htc_apis htc; + //WMI_SVC_APIS wmi_svc_api; +} _A_athos_indirection_table_t; + +#if 1 +extern _A_athos_indirection_table_t _indir_tbl; +#define _A_OS_INDIRECTION_TABLE_SIZE sizeof(_A_athos_indirection_table_t) +#define _A_OS_INDIRECTION_TABLE (&_indir_tbl) +#endif +#endif + +extern unsigned int _data_start_in_rom; +extern unsigned int _data_start; +extern unsigned int _data_end; +extern unsigned int _bss_start; +extern unsigned int _bss_end; +extern unsigned int _stack_sentry; +extern unsigned int __stack; +extern unsigned int _fw_image_end; + +#if defined(__XTENSA__) +#define START_DATA _data_start +#define END_DATA _data_end +#define START_BSS _bss_start +#define END_BSS _bss_end + +#define STACK_START _stack_sentry +#define STACK_END __stack +#endif + + +struct _A_os_linkage_check { + int version; + int table; +}; + + +/* + * A_INIT() handles any initialization needed by the OS abstraction, + * and it clears the application's BSS, if necessary. (Application BSS + * is not cleared if the application is linked into a single image that + * includes AthOS.) + * + * A_INIT() must be called first thing in the application (from app_start) + * in order to guarantee that BSS has been cleared properly. + */ +static INLINE int +A_INIT(void) +{ + struct _A_os_linkage_check link_check; + unsigned int *clrptr; + + if (&START_BSS != _A_MAGPIE_INDIRECTION_TABLE->cmnos.start_bss) { + /* Clear BSS */ + for (clrptr = &START_BSS; clrptr < &END_BSS; clrptr++) { + *clrptr = 0; + } + } + + { + /* Copy writable data from flash to RAM. */ + unsigned int *srcptr, *destptr; + + /* + * The _data_start symbol points to the start of data IN FLASH. + * It is defined by flash.ld at application link time. If flash.ld + * is not used, it is defined (on the link line) as 0. + */ + static int *data_start_addr = &_data_start; + + if (data_start_addr != 0) { + for (srcptr = &_data_start, destptr = &START_DATA; + destptr < &END_DATA; + srcptr++, destptr++) + { + *destptr = *srcptr; + } + } + } + +#define OS_LINKAGE_VERSION 4 + link_check.version = OS_LINKAGE_VERSION; + link_check.table = _A_MAGPIE_INDIRECTION_TABLE_SIZE; + + return A_CMN(hal_linkage_check(sizeof(link_check), &link_check)); +} + + +#endif /* __ATHOS_API_H__ */ + diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/buf_pool_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/buf_pool_api.h new file mode 100755 index 0000000..b4ff2b5 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/buf_pool_api.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * @File: buf_pool_api.h + * + * @Abstract: BUF Pool api + * + * @Notes: + */ + +#ifndef _BUF_POOL_API_H +#define _BUF_POOL_API_H + +#include + +/* endpoint defines */ +typedef enum +{ + POOL_ID_HTC_CONTROL = 0, + POOL_ID_WMI_SVC_CMD_REPLY = 1, + POOL_ID_WMI_SVC_EVENT = 2, + POOL_ID_WLAN_RX_BUF = 3, + POOL_ID_MAX = 10 +} BUF_POOL_ID; + +typedef void* pool_handle_t; + +/* hardware API table structure (API descriptions below) */ +struct buf_pool_api { + pool_handle_t (*_init)(adf_os_handle_t handle); + + void (*_shutdown)(pool_handle_t handle); + + void (*_create_pool)(pool_handle_t handle, BUF_POOL_ID poolId, int nItems, int nSize); + + adf_nbuf_t (*_alloc_buf)(pool_handle_t handle, BUF_POOL_ID poolId, int reserve); + + adf_nbuf_t (*_alloc_buf_align)(pool_handle_t handle, BUF_POOL_ID poolId, int reserve, int align); + + void (*_free_buf)(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void buf_pool_module_install(struct buf_pool_api *apis); + +#endif /* #ifndef _BUF_POOL_API_H */ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/clock_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/clock_api.h new file mode 100755 index 0000000..c7aae71 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/clock_api.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __CLOCK_API_H__ +#define __CLOCK_API_H__ + +#define TICK_MSEC_RATIO 1 +#define TICK_TO_MSEC(tick) ((tick)/TICK_MSEC_RATIO) +#define MSEC_TO_TICK(msec) ((msec)* TICK_MSEC_RATIO) + +struct clock_api { + void (* _clock_init)(A_UINT32 ref_clk); + void (* _clockregs_init)(void); + A_UINT32 (* _uart_frequency)(void); + void (* _delay_us)(int); + void (* _wlan_band_set)(int); + A_UINT32 (* _refclk_speed_get)(void); + A_UINT32 (* _milliseconds)(void); + void (* _sysclk_change)(void); + + void (* _clock_tick)(void); +}; + +#endif /* __CLOCK_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/cmnos_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/cmnos_api.h new file mode 100755 index 0000000..392ec29 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/cmnos_api.h @@ -0,0 +1,662 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __CMNOS_API_H__ +#define __CMNOS_API_H__ + +/* + * This file contains wrappers to OS operating system functions + * that are available in all versions of the operating system. + * + * Target software must always use these wrappers to access OS + * services -- it may not access any OS services directly. + */ + +#include "sys_cfg.h" + +#include "xtensa/config/core.h" +#include "xtensa/hal.h" +#include "xtensa/xtruntime.h" + +/* cmnos interface */ +#include "printf_api.h" +#include "uart_api.h" +#include "dbg_api.h" +#include "mem_api.h" +#include "misc_api.h" +#include "string_api.h" +#include "timer_api.h" +#include "romp_api.h" +#include "allocram_api.h" +#include "tasklet_api.h" +#include "clock_api.h" +#include "intr_api.h" +#include "wdt_api.h" +#include "eeprom_api.h" +#include "usb_api.h" +#include +#include + +#if defined(PROJECT_K2) +#if SYSTEM_MODULE_SFLASH +#include "cmnos/sflash_api.h" +#endif +#endif + +#define AR6K_ROM_START 0x004e0000 +#define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset)) +#define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset) + +#define IML_SIGNAL_UNUSED0_ADDR TARG_ROM_ADDRS(0) /* Cannot be used -- aligned */ +#define IML_SIGNAL_ASSERT_ADDR TARG_ROM_ADDRS(1) /* Signal an assertion failure */ +#define IML_SIGNAL_PRINTF_ADDR TARG_ROM_ADDRS(2) /* Signal a printf request */ +#define IML_SIGNAL_UNUSED4_ADDR TARG_ROM_ADDRS(4) /* Cannot be used -- aligned */ +#define IML_SIGNAL_UNUSED8_ADDR TARG_ROM_ADDRS(8) /* Cannot be used -- aligned */ +#define IML_SIGNAL_UNUSEDC_ADDR TARG_ROM_ADDRS(0xc) /* Cannot be used -- aligned */ +#define IML_SIGNAL_MASK 0xfffe000f +#define IML_LINENUM_SHIFT 4 + +#define NOW() xthal_get_ccount() + +#if defined(__XTENSA__) +#define _A_BARRIER asm volatile("memw") +#else +#define _A_BARRIER +#endif + +#define A_ASSERT( __bool ) \ + do { \ + if (0 == (__bool)) { \ + (void)*((volatile int *)(IML_SIGNAL_ASSERT_ADDR+(__LINE__<<4)));\ + _A_BARRIER; \ + } \ + } while (0) + + +#define A_IML_IS_ASSERT(vaddr) \ + (((vaddr) & IML_SIGNAL_MASK) == (IML_SIGNAL_ASSERT_ADDR & IML_SIGNAL_MASK)) + + +#define PRINT_FAILURE_STATE() \ +do { \ + uint32_t epc1, epc2, epc3, epc4; \ + \ + asm volatile("rsr %0,%1" : "=r" (epc1) : "n" (EPC_1)); \ + asm volatile("rsr %0,%1" : "=r" (epc2) : "n" (EPC_2)); \ + asm volatile("rsr %0,%1" : "=r" (epc3) : "n" (EPC_3)); \ + asm volatile("rsr %0,%1" : "=r" (epc4) : "n" (EPC_4)); \ + \ + A_PRINTF("\tepc1=0x%x, epc2=0x%x, epc3=0x%x, epc4=0x%x\n", \ + epc1, epc2, epc3, epc4); \ + A_PRINTF("0x%08x, 0x%08x, 0x%08x, \n\r", \ + DEBUG_SYSTEM_STATE, WATCH_DOG_RESET_COUNTER, \ + WATCH_DOG_MAGIC_PATTERN); \ +} while(0) +//////////////////////////////////////////////////////////////////////////////////// + + +//#define A_CMN(sym) _A_OS_INDIRECTION_TABLE->cmnos.sym +#define A_CMN(sym) _A_MAGPIE_INDIRECTION_TABLE->cmnos.sym + +#if SYSTEM_MODULE_MEM +/* Mem interfaces */ +#define A_MEMSET(addr, value, size) \ + A_CMN(mem._memset((char *)(addr), (int)(value), (int)(size))) + +#define A_MEMZERO(addr, size) \ + A_CMN(mem._memset((char *)(addr), (int)0, (int)(size))) + +#define A_MEMCPY(dst, src, size) \ + A_CMN(mem._memcpy((char *)(dst), (char *)(src), (int)(size))) + +#define A_MEMMOVE(dst, src, size) \ + A_CMN(mem._memmove((char *)(dst), (char *)(src), (int)(size))) + +#define A_MEMCMP(p1, p2, nbytes) \ + A_CMN(mem._memcmp)((void *)(p1), (void *)(p2), (int)(nbytes)) +#else +/* Mem interfaces */ +#define A_MEMSET(addr, value, size) + +#define A_MEMZERO(addr, size) + +#define A_MEMCPY(dst, src, size) + +#define A_MEMMOVE(dst, src, size) + +#define A_MEMCMP(p1, p2, nbytes) +#endif + + +#if 1 + /* String interfaces */ + #define A_STRCPY(dst, src) A_CMN(string._strcpy((dst), (src))) + #define A_STRNCPY(dst, src, n) A_CMN(string._strncpy((dst), (src), (n))) + #define A_STRLEN(str) A_CMN(string._strlen(str)) + #define A_STRCMP(str1, str2) A_CMN(string._strcmp((str1), (str2))) + #define A_STRNCMP(str1, str2, n) A_CMN(string._strncmp((str1), (str2), (n))) +#endif + +#if SYSTEM_MODULE_PRINT +/* Printf support */ +#define A_PRINTF_INIT() A_CMN(printf._printf_init()) +#define A_PRINTF A_CMN(printf._printf) +#else +#define A_PRINTF_INIT() +#define A_PRINTF +#endif /* SYSTEM_MODULE_PRINT */ + +#if SYSTEM_MODULE_UART +/* Serial port support */ +#define A_UART_INIT() A_CMN(uart._uart_init()) + +#define A_UART_HWINIT(freq, baud) \ + A_CMN(uart._uart_hwinit((freq), (baud))) + +#define A_UART_ENABLED() (HOST_INTEREST->hi_uart_enable) + +#define A_PUTS(str) A_CMN(uart._uart_str_out(str)) + +#define A_PUTC(ch) A_CMN(uart._uart_char_put(ch)) +#define A_GETC(pCh) A_CMN(uart._uart_char_get(pCh)) + +#define A_UART_TASK() A_CMN(uart._uart_task()) +#define A_UART_CONFIG(x) A_CMN(uart._uart_config(x)) + +#else + +#define A_UART_INIT() + +#define A_UART_HWINIT(freq, baud) + +#define A_UART_ENABLED() + +#define A_PUTS(str) + +#define A_PUTC(ch) +#define A_GETC(pCh) + +#define A_UART_TASK() +#define A_UART_CONFIG(x) + +#endif + +#if SYSTEM_MODULE_MISC +/* Reset Support */ +#define A_RESET() A_CMN(misc._system_reset()) +#define A_RESET_MAC() A_CMN(misc._mac_reset()) + +/* Assertion failure */ +#define A_ASSFAIL(regdump) A_CMN(misc._assfail((regdump))) + +/* Report a failure to the Host */ +#define A_REPORT_FAILURE(data, len) \ + A_CMN(misc._report_failure_to_host((data), (len))) + +/* UNALIGNED references are used for ASSERTs */ +#define A_MISALIGNED_LOAD_HANDLER(dump) A_CMN(misc._misaligned_load_handler(dump)) + +/* reture the host interface type */ +#define A_IS_HOST_PRESENT() A_CMN(misc._is_host_present()) +#define A_KBHIT(delay) A_CMN(misc._kbhit(delay)) +#define A_GET_ROM_VER() A_CMN(misc._rom_version_get()) +#else +/* Reset Support */ +#define A_RESET() +#define A_RESET_MAC() + +/* Assertion failure */ +#define A_ASSFAIL(regdump) + +#define A_MISALIGNED_LOAD_HANDLER(dump) + +/* Report a failure to the Host */ +#define A_REPORT_FAILURE(data, len) + +#define A_IS_HOST_PRESENT() +#define A_KBHIT(delay) +#define A_GET_ROM_VER() +#endif + +//#if SYSTEM_MODULE_DBG +/* debug Support */ +//#define A_DBG_INIT() A_CMN(dbg._dbg_init()) +//#define A_DBG_TASK() A_CMN(dbg._dbg_task()) +//#else +//#define A_DBG_INIT() +//#define A_DBG_TASK() +//#endif + +#if SYSTEM_MODULE_USB +/* debug Support */ +#define A_USB_INIT() A_CMN(usb._usb_init()) +#define A_USB_ROM_TASK() A_CMN(usb._usb_rom_task()) +#define A_USB_FW_TASK() A_CMN(usb._usb_fw_task()) +#define A_USB_INIT_PHY() A_CMN(usb._usb_init_phy()) + +#define A_USB_EP0_SETUP() A_CMN(usb._usb_ep0_setup()) +#define A_USB_EP0_TX_DATA() A_CMN(usb._usb_ep0_tx_data()) +#define A_USB_EP0_RX_DATA() A_CMN(usb._usb_ep0_rx_data()) + +#define A_USB_GET_CONFIG() A_CMN(usb._usb_get_configuration()) +#define A_USB_SET_CONFIG() A_CMN(usb._usb_set_configuration()) + +#define A_USB_GET_INTERFACE() A_CMN(usb._usb_get_interface()) +#define A_USB_SET_INTERFACE() A_CMN(usb._usb_set_interface()) + +#define A_USB_STANDARD_CMD() A_CMN(usb._usb_standard_cmd()) +#define A_USB_VENDOR_CMD() A_CMN(usb._usb_vendor_cmd()) + +#define A_USB_POWER_OFF() A_CMN(usb._usb_power_off()) +#define A_USB_RESET_FIFO() A_CMN(usb._usb_reset_fifo()) +#define A_USB_GEN_WDT() A_CMN(usb._usb_gen_wdt()) +#define A_USB_JUMP_BOOT() A_CMN(usb._usb_jump_boot()) + +#define A_USB_GET_DESCRIPTOR() A_CMN(usb._usb_get_descriptor()) +#define A_USB_SET_ADDRESS() A_CMN(usb._usb_set_address()) +#define A_USB_SET_FEATURE() A_CMN(usb._usb_set_feature()) +#define A_USB_CLEAR_FEATURE() A_CMN(usb._usb_clr_feature()) + +#define A_USB_GET_STATUS() A_CMN(usb._usb_get_status()) +#define A_USB_SETUP_DESC() A_CMN(usb._usb_setup_desc()) +#define A_USB_STATUS_IN() A_CMN(usb._usb_status_in()) +#define A_USB_REG_OUT() A_CMN(usb._usb_reg_out()) + +#define A_USB_EP0_TX() A_CMN(usb._usb_ep0_tx()) +#define A_USB_EP0_RX() A_CMN(usb._usb_ep0_rx()) +#define A_USB_CLK_INIT() A_CMN(usb._usb_clk_init()) + +#else +#define A_USB_INIT() +#define A_USB_TASK() +#define A_USB_INIT_PHY() + +#define A_USB_EP0_SETUP() +#define A_USB_EP0_TX() +#define A_USB_EP0_RX() + +#define A_USB_GET_CONFIG() +#define A_USB_SET_CONFIG() + +#define A_USB_GET_INTERFACE() +#define A_USB_SET_INTERFACE() + +#define A_USB_STANDARD_CMD() +#define A_USB_VENDOR_CMD() + +#define A_USB_POWER_OFF() +#define A_USB_RESET_FIFO() +#define A_USB_GEN_WDT() +#define A_USB_JUMP_BOOT() + +#define A_USB_GET_DESCRIPTOR() +#define A_USB_SET_ADDRESS() +#define A_USB_SET_FEATURE() +#define A_USB_CLEAR_FEATURE() + +#define A_USB_GET_STATUS() +#define A_USB_SETUP_DESC() + + +#define A_USB_STATUS_IN() +#define A_USB_REG_OUT() + +#define A_USB_EP0_TX() +#define A_USB_EP0_RX() + +#define A_USB_CLK_INIT() +#endif + +#if SYSTEM_MODULE_INTR +/* Low-level interrupt support intended for use by OS modules */ +#define A_INTR_GET_INTRENABLE() A_CMN(intr._get_intrenable()) +#define A_INTR_SET_INTRENABLE(val) A_CMN(intr._set_intrenable(val)) +#define A_INTR_GET_INTRPENDING() A_CMN(intr._get_intrpending()) +#define A_INTR_UNBLOCK_ALL_INTRLVL() A_CMN(intr._unblock_all_intrlvl()) + +/* Interrupt support */ +#define A_INTR_INIT() A_CMN(intr._intr_init()) + +#define A_INTR_DISABLE(pOld) \ + do { \ + *(pOld) = A_CMN(intr._intr_disable()); \ + } while (0) + +#define A_INTR_RESTORE(old) A_CMN(intr._intr_restore((old))) + +#define A_INVOKE_ISR(inum) A_CMN(intr._intr_invoke_isr(inum)) + +#define A_INTR_MASK(inum) A_CMN(intr._intr_mask_inum(inum)) +#define A_INTR_UNMASK(inum) A_CMN(intr._intr_unmask_inum(inum)) + +#define A_ATTACH_ISR(inum, isr, arg) A_CMN(intr._intr_attach_isr(inum, isr, arg)) +#else +#define A_INTR_INIT() +#define A_INTR_DISABLE(pOld) +#define A_INTR_RESTORE(old) + +#define A_INTR_GET_INTRENABLE() +#define A_INTR_SET_INTRENABLE(val) +#define A_INTR_GET_INTRPENDING() +#define A_INTR_UNBLOCK_ALL_INTRLVL() +#define A_INVOKE_ISR(inum) +#define A_INTR_MASK(inum) +#define A_INTR_UNMASK(inum) +#define A_ATTACH_ISR(inum, isr, arg) + +#endif + +/* Tasklet Support */ +#define A_TASKLET_INIT() A_CMN(tasklet._tasklet_init()) +#define A_TASKLET_INIT_TASK(f, arg, t) A_CMN(tasklet._tasklet_init_task(f, arg, t)) +#define A_TASKLET_DISABLE(t) A_CMN(tasklet._tasklet_disable(t)) +#define A_TASKLET_SCHEDULE(t) A_CMN(tasklet._tasklet_schedule(t)) +#define A_TASKLET_RUN() A_CMN(tasklet._tasklet_run()) + + +/* RAM Allocation Support */ +#if defined(__mips__) +#define alloc_arena_start _end +#endif +#if defined(__XTENSA__) +#define alloc_arena_start _end +#endif + +#if SYSTEM_MODULE_CLOCK + +#define A_CLOCK_INIT(refclk_guess) A_CMN(clock._clock_init(refclk_guess)) +#define A_CLOCK_TICK() A_CMN(clock._clock_tick()) +#define A_CLOCK_GET_TICK() A_CMN(clock._clock_get_tick()) + +/* + * Get the number of millisecond ticks since the system was started. + * Note that this only approximates 1Ms. It's actually 32 ticks of + * a 32KHz clock. + * + * Returns a A_UINT32 value. + */ +#define A_MILLISECONDS() A_CMN(clock._milliseconds()) + +/* + * Get the frequency of the reference clock, expressed as + * an A_refclk_speed_t. + */ +#define A_REFCLK_SPEED_GET() A_CMN(clock._refclk_speed_get()) + +/* Spin delay */ +#define A_DELAY_USECS(us) A_CMN(clock._delay_us(us)) + +#define A_UART_FREQUENCY() A_CMN(clock._uart_frequency()) + +#define A_CLOCKREGS_INIT() A_CMN(clock._clockregs_init()) + +/* which_band is either A_BAND_24GHZ or A_BAND_5GHZ */ +#define A_WLAN_BAND_SET(which_band) \ + A_CMN(clock._wlan_band_set(which_band)) + +/* Called whenever the system clock changes speed */ +#define A_SYSCLK_CHANGE() A_CMN(clock._sysclk_change()) + +#else + +#define A_CLOCK_INIT(refclk_guess) +#define A_CLOCK_TICK() +#define A_CLOCK_GET_TICK() +#define A_MILLISECONDS() +#define A_REFCLK_SPEED_GET() +#define A_DELAY_USECS(us) +#define A_UART_FREQUENCY() +#define A_CLOCKREGS_INIT() +#define A_WLAN_BAND_SET(which_band) +#define A_SYSCLK_CHANGE() + +#endif + +// Timer +#define A_INIT_TIMER(pTimer, pFunction, pArg) \ + A_CMN(timer._timer_setfn((pTimer), (pFunction), (pArg))) + +/* Set a (possibly periodic) timer for "period" Milliseconds. */ +#define A_TIMEOUT_MS(pTimer, period) \ + A_CMN(timer._timer_arm((pTimer), (period))) + +#define A_UNTIMEOUT(pTimer) \ + A_CMN(timer._timer_disarm(pTimer)) + +#define A_TIMER_RUN() \ + A_CMN(timer._timer_run()) + +#define A_GMAC_BOOT_INIT() \ + A_CMN(gmac.gmac_boot_init()) + +#if SYSTEM_MODULE_ALLOCRAM +/* Default size of ALLOCRAM area */ +#define ARENA_SZ_DEFAULT 12000 + +#define A_ALLOCRAM_INIT(arena_start, arena_size) \ +do { \ + extern unsigned int alloc_arena_start; \ + void *astart; \ + int asize; \ + astart = (arena_start) ? (void *)(arena_start) : &alloc_arena_start; \ + asize = (arena_size) ? (arena_size) : (ARENA_SZ_DEFAULT); \ + A_CMN(allocram.cmnos_allocram_init((astart), (asize))); \ +} while (0) + +#define A_ALLOCRAM(nbytes) A_CMN(allocram.cmnos_allocram(0, (nbytes))) + +#define A_ALLOCRAM_DEBUG() A_CMN(allocram.cmnos_allocram_debug()) + +#else +#define A_ALLOCRAM_INIT(arena_start, arena_size) +#define A_ALLOCRAM(nbytes) +#define A_ALLOCRAM_DEBUG() +#endif + +#if SYSTEM_MODULE_ROM_PATCH + +#define A_ROMP_INIT() A_CMN(romp._romp_init()) +#define A_ROMP_DOWNLOAD(x) A_CMN(romp._romp_download(x)) +#define A_ROMP_DECODE(addr) A_CMN(romp._romp_decode(addr)) +#define A_ROMP_INSTALL() A_CMN(romp._romp_install()) +#else +#define A_ROMP_INIT() +#define A_ROMP_DOWNLOAD(x) +#define A_ROMP_DECODE(addr) +#define A_ROMP_INSTALL() +#endif + +#if SYSTEM_MODULE_WDT + +#define A_WDT_INIT() A_CMN(wdt_timer._wdt_init()) +#define A_WDT_ENABLE() A_CMN(wdt_timer._wdt_enable()) +#define A_WDT_DISABLE() A_CMN(wdt_timer._wdt_disable()) +#define A_WDT_SET(t) A_CMN(wdt_timer._wdt_set(t)) +#define A_WDT_TASK() A_CMN(wdt_timer._wdt_task()) +#define A_WDT_LASTBOOT() A_CMN(wdt_timer._wdt_last_boot()) +#define A_WDT_RESET() A_CMN(wdt_timer._wdt_reset()) + +#else +#define A_WDT_INIT() +#define A_WDT_ENABLE() +#define A_WDT_DISABLE() +#define A_WDT_SET(t) +#define A_WDT_TASK() +#define A_WDT_LASTBOOT() +#define A_WDT_RESET() +#endif + + +#if SYSTEM_MODULE_EEPROM +#define A_EEP_INIT() A_CMN(eep._eep_init()) +#define A_EEP_READ(off, len, buf) A_CMN(eep._eep_read(off, len, buf)) +#define A_EEP_WRITE(off, len, buf) A_CMN(eep._eep_write(off, len, buf)) +#define A_EEP_IS_EXIST() A_CMN(eep._eep_is_exist()) +#else +#define A_EEP_INIT() +#define A_EEP_READ(off, len, buf) +#define A_EEP_WRITE(off, len, buf) +#define A_EEP_IS_EXIST() +#endif + + + +struct _A_os_linkage_check; /* OS-dependent */ + +typedef struct _A_cmnos_indirection_table { + int (* hal_linkage_check)(int sz, struct _A_os_linkage_check *); + unsigned int *start_bss; + void (* app_start)(void); + +#if SYSTEM_MODULE_MEM + struct mem_api mem; +#endif + +#if SYSTEM_MODULE_MISC + struct misc_api misc; +#endif + +#if SYSTEM_MODULE_PRINT + struct printf_api printf; +#endif + +#if SYSTEM_MODULE_UART + struct uart_api uart; +#endif + +//#if SYSTEM_MODULE_DBG +// struct dbg_api dbg; +//#endif + + +#if SYSTEM_MODULE_GMAC + struct gmac_api gmac; +#endif + +#if SYSTEM_MODULE_USB + struct usb_api usb; +#endif + +#if SYSTEM_MODULE_CLOCK + struct clock_api clock; +#endif + +#if SYSTEM_MODULE_TIMER + struct timer_api timer; +#endif + +#if SYSTEM_MODULE_INTR + struct intr_api intr; +#endif + +#if SYSTEM_MODULE_ALLOCRAM + struct allocram_api allocram; +#endif + +#if SYSTEM_MODULE_ROM_PATCH + struct romp_api romp; +#endif + +#if SYSTEM_MODULE_WDT + struct wdt_api wdt_timer; +#endif + +#if SYSTEM_MODULE_EEPROM + struct eep_api eep; +#endif + + struct string_api string; + struct tasklet_api tasklet; + +} _A_cmnos_indirection_table_t; + +/* Module installation for cmnos modules */ + +#if SYSTEM_MODULE_MEM +extern void cmnos_mem_module_install(struct mem_api *); +#endif + +#if SYSTEM_MODULE_MISC +extern void cmnos_misc_module_install(struct misc_api *); +#endif + +#if SYSTEM_MODULE_PRINT +extern void cmnos_printf_module_install(struct printf_api *); +#endif + +#if SYSTEM_MODULE_UART +extern void cmnos_uart_module_install(struct uart_api *); +#endif + +//#if SYSTEM_MODULE_DBG +//extern void cmnos_dbg_module_install(struct dbg_api *); +//#endif + +#if SYSTEM_MODULE_USB +extern void cmnos_usb_module_install(struct usb_api *); +#endif + +#if SYSTEM_MODULE_INTR +extern void cmnos_intr_module_install(struct intr_api *); +#endif + +#if SYSTEM_MODULE_CLOCK +extern void cmnos_clock_module_install(struct clock_api *); +#endif + +#if SYSTEM_MODULE_TIMER +extern void cmnos_timer_module_install(struct timer_api *); +#endif + +#if SYSTEM_MODULE_ALLOCRAM +extern void cmnos_allocram_module_install(struct allocram_api *); +#endif + +#if SYSTEM_MODULE_ROM_PATCH +extern void cmnos_romp_module_install(struct romp_api *); +#endif + +#if SYSTEM_MODULE_WDT +extern void cmnos_wdt_module_install(struct wdt_api *); +#endif + +#if SYSTEM_MODULE_EEPROM +extern void cmnos_eep_module_install(struct eep_api *); +#endif + +extern void cmnos_tasklet_module_install(struct tasklet_api *); + +extern void cmnos_string_module_install(struct string_api *tbl); + +#endif /* __CMNOS_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/dma_engine_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/dma_engine_api.h new file mode 100755 index 0000000..2f80c24 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/dma_engine_api.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * @File: dma_engine_api.h + * + * @Abstract: DMA Engine api + * + * @Notes: + */ + +#ifndef _DMA_ENGINE_API_H +#define _DMA_ENGINE_API_H + +#include +#include + +struct zsDmaDesc +{ +#if 1 // BIG_ENDIAN + volatile u16_t ctrl; // Descriptor control + volatile u16_t status; // Descriptor status + volatile u16_t totalLen; // Total length + volatile u16_t dataSize; // Data size +#else + volatile u16_t status; // Descriptor status + volatile u16_t ctrl; // Descriptor control + volatile u16_t dataSize; // Data size + volatile u16_t totalLen; // Total length +#endif + struct zsDmaDesc* lastAddr; // Last address of this chain + volatile u32_t dataAddr; // Data buffer address + struct zsDmaDesc* nextAddr; // Next TD address +}; + +struct zsDmaQueue +{ + struct zsDmaDesc* head; + struct zsDmaDesc* terminator; +}; + +// Subclass of zsDmaQueue for TX +struct zsTxDmaQueue +{ + struct zsDmaDesc* head; + struct zsDmaDesc* terminator; + + /* Below are fields specific to TX */ + VBUF *xmited_buf_head; + VBUF *xmited_buf_tail; +}; + +/* hardware API table structure (API descriptions below) */ +struct dma_engine_api +{ + void (*_init)(); + + void (*_init_rx_queue)(struct zsDmaQueue *q); + + void (*_init_tx_queue)(struct zsTxDmaQueue *q); + + void (*_config_rx_queue)(struct zsDmaQueue *q, int num_desc, int buf_size); + + void (*_xmit_buf)(struct zsTxDmaQueue *q, VBUF *buf); + + void (*_flush_xmit)(struct zsDmaQueue *q); + + VBUF* (*_reap_recv_buf)(struct zsDmaQueue *q); + + void (*_return_recv_buf)(struct zsDmaQueue *q, VBUF *buf); + + VBUF* (*_reap_xmited_buf)(struct zsTxDmaQueue *q); + + void (*_swap_data)(struct zsDmaDesc* desc); + + int (*_has_compl_packets)(struct zsDmaQueue *q); + + void (*_desc_dump)(struct zsDmaQueue *q); + + /* The functions below are for patchable */ + struct zsDmaDesc* (*_get_packet)(struct zsDmaQueue* q); + void (*_reclaim_packet)(struct zsDmaQueue* q, struct zsDmaDesc* desc); + void (*_put_packet)(struct zsDmaQueue* q, struct zsDmaDesc* desc); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void dma_engine_module_install(struct dma_engine_api *apis); + +#endif /* #ifndef _DMA_ENGINE_API_H */ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/dma_lib.h b/target_firmware/magpie_fw_dev/target/inc/magpie/dma_lib.h new file mode 100755 index 0000000..7b44c56 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/dma_lib.h @@ -0,0 +1,57 @@ +#ifndef __DMA_LIB_H +#define __DMA_LIB_H + + +/***********************External***************************/ + +/** + * @brief DMA engine numbers, HIF need to map them to there + * respective order + */ +typedef enum dma_engine{ + DMA_ENGINE_RX0, + DMA_ENGINE_RX1, + DMA_ENGINE_RX2, + DMA_ENGINE_RX3, + DMA_ENGINE_TX0, + DMA_ENGINE_TX1, + DMA_ENGINE_MAX +}dma_engine_t; + +/** + * @brief Interface type, each HIF should call with its own interface type + */ +typedef enum dma_iftype{ + DMA_IF_GMAC = 0x0,/* GMAC */ + DMA_IF_PCI = 0x1,/*PCI */ + DMA_IF_PCIE = 0x2 /*PCI Express */ +}dma_iftype_t; + + +struct dma_lib_api{ + A_UINT16 (*tx_init)(dma_engine_t eng_no, dma_iftype_t if_type); + void (*tx_start)(dma_engine_t eng_no); + A_UINT16 (*rx_init)(dma_engine_t eng_no, dma_iftype_t if_type); + void (*rx_config)(dma_engine_t eng_no, a_uint16_t num_desc, + a_uint16_t gran); + void (*rx_start)(dma_engine_t eng_no); + A_UINT32 (*intr_status)(dma_iftype_t if_type); + A_UINT16 (*hard_xmit)(dma_engine_t eng_no, VBUF *buf); + void (*flush_xmit)(dma_engine_t eng_no); + A_UINT16 (*xmit_done)(dma_engine_t eng_no); + VBUF * (*reap_xmitted)(dma_engine_t eng_no); + VBUF * (*reap_recv)(dma_engine_t eng_no); + void (*return_recv)(dma_engine_t eng_no, VBUF *buf); + A_UINT16 (*recv_pkt)(dma_engine_t eng_no); +}; + + +/** + * @brief Install the DMA lib api's this for ROM patching + * support + * + * @param apis + */ +void dma_lib_module_install(struct dma_lib_api *apis); + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/eeprom_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/eeprom_api.h new file mode 100755 index 0000000..b9668c8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/eeprom_api.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __EEPROM_API_H__ +#define __EEPROM_API_H__ +/* + * + */ + + +typedef enum { + RET_SUCCESS = 0, + RET_NOT_INIT, + RET_NOT_EXIST, + RET_EEP_CORRUPT, + RET_EEP_OVERFLOW, + + // add return code from here + RET_UNKNOWN +}T_EEP_RET; + + +/*!- interface of eeprom access + * + */ +struct eep_api { + void (* _eep_init)(void); + T_EEP_RET (* _eep_read)(uint16_t, uint16_t, uint16_t *); + T_EEP_RET (* _eep_write)(uint16_t, uint16_t, uint16_t *); + T_EEP_RET (*_eep_is_exist)(void); + +}; + +#endif /* __EEPROM_API_H__ */ + diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/hif_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/hif_api.h new file mode 100755 index 0000000..eff92df --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/hif_api.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * @File: HIF_api.h + * + * @Abstract: Host Interface api + * + * @Notes: + */ + +#ifndef _HIF_API_H +#define _HIF_API_H + +#include + +/* mailbox hw module configuration structure */ +typedef struct _HIF_CONFIG { + int dummy; +} HIF_CONFIG; + +typedef struct _HIF_CALLBACK { + /* callback when a buffer has be sent to the host*/ + void (*send_buf_done)(adf_nbuf_t buf, void *context); + /* callback when a receive message is received */ + void (*recv_buf)(adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *context); + /* context used for all callbacks */ + void *context; +} HIF_CALLBACK; + +typedef void* hif_handle_t; + +/* hardware API table structure (API descriptions below) */ +struct hif_api { + hif_handle_t (*_init)(HIF_CONFIG *pConfig); + + void (* _shutdown)(hif_handle_t); + + void (*_register_callback)(hif_handle_t, HIF_CALLBACK *); + + int (*_get_total_credit_count)(hif_handle_t); + + void (*_start)(hif_handle_t); + + void (*_config_pipe)(hif_handle_t handle, int pipe, int creditCount); + + int (*_send_buffer)(hif_handle_t handle, int pipe, adf_nbuf_t buf); + + void (*_return_recv_buf)(hif_handle_t handle, int pipe, adf_nbuf_t buf); + //void (*_set_recv_bufsz)(int pipe, int bufsz); + //void (*_pause_recv)(int pipe); + //void (*_resume_recv)(int pipe); + int (*_is_pipe_supported)(hif_handle_t handle, int pipe); + + int (*_get_max_msg_len)(hif_handle_t handle, int pipe); + + int (*_get_reserved_headroom)(hif_handle_t handle); + + void (*_isr_handler)(hif_handle_t handle); + + void (*_get_default_pipe)(hif_handle_t handle, A_UINT8 *pipe_uplink, A_UINT8 *pipe_downlink); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void generic_hif_module_install(struct hif_api *apis); + +#endif /* #ifndef _HIF_API_H */ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/hif_gmac.h b/target_firmware/magpie_fw_dev/target/inc/magpie/hif_gmac.h new file mode 100755 index 0000000..3ca57b7 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/hif_gmac.h @@ -0,0 +1,290 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __HIF_GMAC_H +#define __HIF_GMAC_H + +#include +#include + + +#define ETH_ALEN 6 +#define GMAC_MAX_PKT_LEN 1600 +#define GMAC_MAX_DESC 5 + +#define GMAC_DISCV_PKT_SZ 1024 +#define GMAC_DISCV_WAIT 2000 + +#define ATH_P_MAGBOOT 0x12 /*Magpie GMAC 18 for boot downloader*/ +#define ATH_P_MAGNORM 0x13 /*Magpie GMAC 19 for HTC & others*/ + +#define ETH_P_ATH 0x88bd + +typedef enum hif_gmac_pipe{ + HIF_GMAC_PIPE_RX = 1, /*Normal Priority RX*/ + HIF_GMAC_PIPE_TX = 2, /*Normal Priority TX*/ +}hif_gmac_pipe_t; + +struct gmac_api{ + void (*gmac_boot_init)(void); +}; + +void cmnos_gmac_module_install(struct gmac_api *boot_apis); +void hif_gmac_module_install(struct hif_api *apis); + +enum __gmac_mii_mode { + GMAC_MIIMODE_NONE=0, + GMAC_MIIMODE_MII=1, + GMAC_MIIMODE_RMII=2, + GMAC_MIIMODE_GMII=3, + GMAC_MIIMODE_RGMII=4, + GMAC_MIIMODE_MAX=5 +}; +enum __gmac_msg_type{ + GMAC_HST_QUERY = 0x0001, + GMAC_HST_REPLY = 0x0002, + GMAC_TGT_QUERY = 0x0003, + GMAC_TGT_REPLY = 0x0004 +}; + +enum __magpie_regs{ + MAG_REG_GPIO_OE = 0x00052000,/*GPIO Output Enable*/ + MAG_REG_RST = 0x00050010,/*Magpie reset reg*/ + MAG_REG_RST_AHB = 0x00050018,/*Magpie AHB_ARB reset reg*/ + MAG_REG_MII0_CTRL = 0x00054100,/*Magpie MII0 Control reg*/ + MAG_REG_STAT_CTRL = 0x00054104,/*Magpie Status reg*/ + + MAG_REG_ETH_PLL = 0x5600c, + MAG_REG_ETHPLL_BYPASS = 0x56010, +}; + +enum __gmac_regs{ + GMAC_REG_BASE = 0x00060000, + GMAC_REG_MAC_CFG1 = 0x00 + GMAC_REG_BASE,/*MAC config 1*/ + GMAC_REG_MAC_CFG2 = 0x04 + GMAC_REG_BASE,/*MAC config 2*/ + GMAC_REG_IPG_IFG = 0x08 + GMAC_REG_BASE,/*Inter-packet-gap*/ + GMAC_REG_HALF_DPLX = 0x0c + GMAC_REG_BASE,/*Half duplex*/ + GMAC_REG_MAX_FRAME = 0x10 + GMAC_REG_BASE,/*Max frame length*/ + GMAC_REG_MII_CFG = 0x20 + GMAC_REG_BASE,/*MII mgmt config*/ + GMAC_REG_MII_CMD = 0x24 + GMAC_REG_BASE,/*MII mgmt command*/ + GMAC_REG_MII_ADDR = 0x28 + GMAC_REG_BASE,/*MII mgmt address*/ + GMAC_REG_MII_CTRL = 0x2c + GMAC_REG_BASE,/*MII mgmt control*/ + GMAC_REG_MII_STAT = 0x30 + GMAC_REG_BASE,/*MII mgmt status*/ + GMAC_REG_MII_PSTAT = 0x34 + GMAC_REG_BASE,/*MII mgmt Phy status/ind*/ + GMAC_REG_IF_CTRL = 0x38 + GMAC_REG_BASE,/*Interface control*/ + GMAC_REG_IF_STAT = 0x3c + GMAC_REG_BASE,/*Interface status*/ + GMAC_REG_MAC_ADDR1 = 0x40 + GMAC_REG_BASE,/*MAC address 1*/ + GMAC_REG_MAC_ADDR2 = 0x44 + GMAC_REG_BASE,/*MAC address 2*/ + GMAC_REG_FIFO_CFG0 = 0x48 + GMAC_REG_BASE,/*FIFO config reg0*/ + GMAC_REG_FIFO_CFG1 = 0x4c + GMAC_REG_BASE,/*FIFO config reg1*/ + GMAC_REG_FIFO_CFG2 = 0x50 + GMAC_REG_BASE,/*FIFO config reg2*/ + GMAC_REG_FIFO_CFG3 = 0x54 + GMAC_REG_BASE,/*FIFO config reg3*/ + GMAC_REG_FIFO_CFG4 = 0x58 + GMAC_REG_BASE,/*FIFO config reg4*/ + GMAC_REG_FIFO_CFG5 = 0x5c + GMAC_REG_BASE,/*FIFO config reg5*/ + GMAC_REG_FIFO_RAM0 = 0x60 + GMAC_REG_BASE,/*FIFO RAM access reg0*/ + GMAC_REG_FIFO_RAM1 = 0x64 + GMAC_REG_BASE,/*FIFO RAM access reg1*/ + GMAC_REG_FIFO_RAM2 = 0x68 + GMAC_REG_BASE,/*FIFO RAM access reg2*/ + GMAC_REG_FIFO_RAM3 = 0x6c + GMAC_REG_BASE,/*FIFO RAM access reg3*/ + GMAC_REG_FIFO_RAM4 = 0x70 + GMAC_REG_BASE,/*FIFO RAM access reg4*/ + GMAC_REG_FIFO_RAM5 = 0x74 + GMAC_REG_BASE,/*FIFO RAM access reg5*/ + GMAC_REG_FIFO_RAM6 = 0x78 + GMAC_REG_BASE,/*FIFO RAM access reg6*/ + GMAC_REG_FIFO_RAM7 = 0x7c + GMAC_REG_BASE,/*FIFO RAM access reg7*/ +}; + +enum __mag_reg_rst{ + RST_GMAC = (1 << 9),/*Reset the GMAC */ + RST_MII = (3 << 11),/*Reset the MII*/ + RST_OTHERS = 0x5df,/*Reset everybody other than GMAC & MII*/ +}; + +enum __mag_reg_rst_ahb{ + RST_AHB_GMAC = 0x1 +}; +enum __mag_mii0_ctrl_mode{ + MII0_CTRL_MODE_GMII = 0x00, /* GMII*/ + MII0_CTRL_MODE_MII = 0x01, /*MII*/ + MII0_CTRL_MODE_RGMII = 0x02,/* RGMII */ + MII0_CTRL_MODE_RMII = 0x03, /* RMII */ + MII0_CTRL_MASTER_MODE = 0x04 /* master mode */ +}; +enum __mag_mii0_ctrl_speed { + MII0_CTLR_SPEED_10 = 0x00, /* 10 mbps*/ + MII0_CTRL_SPEED_100 = 0x10, /*MII control address 100 Mbps*/ + MII0_CTRL_SPEED_1000 = 0x20 /* 1000 */ +}; + + +enum __gmac_reg_mac_cfg1{ + MAC_CFG1_TX_EN = (1 << 0),/*TX enable*/ + MAC_CFG1_RX_EN = (1 << 2),/*RX enable*/ + MAC_CFG1_TX_FLOW = (1 << 4),/*TX Flow control enable*/ + MAC_CFG1_RX_FLOW = (1 << 5),/*RX Flow control enable*/ + MAC_CFG1_LOOP_EN = (1 << 8),/*Enable loopback*/ +}; +enum __gmac_reg_mac_cfg2{ + MAC_CFG2_FULL_DUP = (1 << 0),/*Enable Full Duplex*/ + MAC_CFG2_PAD_CRC = (1 << 2),/*Enable MAC based CRC insertion*/ + MAC_CFG2_CHK_LEN = (1 << 4),/*Check Length field*/ + MAC_CFG2_HUGE_FRM = (1 << 5),/*Allow sending huge frames*/ + MAC_CFG2_MII = (1 << 8),/*MAC is MII in mode*/ + MAC_CFG2_GMII = (1 << 9),/*MAC is in GMII mode*/ + MAC_CFG2_PREAMBLE = (7 << 12),/*Default Preamble Length*/ +}; +enum __gmac_reg_mii_cfg{ + MII_CFG_CLK_2MHZ = 0x0006,/*Clock is 2Mhz*/ +}; + + +/* following are only for F1 phy on emulation board.*/ +enum __gmac_reg_mii_addr{ + MII_ADDR_RESET = 0x000,/*Flush the MII address register*/ + MII_ADDR_STATS = 0x001,/* Stauts register*/ + MII_ADDR_PHY_IDENT_1 = 0x002,/* phy identifier [18:3]*/ + MII_ADDR_PHY_IDENT_2 = 0x003,/* phy identifier [19:24]*/ + MII_ADDR_AUTONEG_ADV = 0x004,/* Autonegotiaion advertise*/ + MII_ADDR_LINKPART_ABILITY = 0x0005,/* link partner ability*/ + MII_ADDR_AUTONEG_EXP = 0x0006,/* Autonegotiation expansion*/ + MII_ADDR_NEXTPG_TX = 0x0007,/* Next page transmit*/ + MII_ADDR_LINKPART_NEXTPG = 0x0008,/* Link partnet next page*/ + MII_ADDR_1000BASET_CNTRL = 0x0009,/* 1000 base-t control*/ + MII_ADDR_1000BSAET_STATUS = 0x000a,/* 1000 base-t status*/ + MII_ADDR_EXTENDED_STATUS = 0x000f,/* extended status*/ + MII_ADDR_FUNCTION_CTRL = 0x0010,/* function control*/ + MII_ADDR_PHY_REG = 0x0011,/*Phy Status Reg*/ + MII_ADDR_INTERRUPT_ENA = 0x0012,/* interrupt enable*/ + MII_ADDR_INTERRUPT_STATUS = 0x0013,/* interrupt status*/ + MII_ADDR_EXTPHY_CTRL = 0x0014,/* extemded phy specific control*/ + MII_ADDR_CABDET_CTRL = 0x0016,/* cable detect testser control*/ + MII_ADDR_LED_CTRL = 0x0018,/* LED control*/ + MII_ADDR_MANLED_OVER = 0x0019,/* Manual LED override*/ + MII_ADDR_CABDET_STAT = 0x001c,/* cable detect tester status*/ + MII_ADDR_DEBUGPORT_OFF = 0x001d,/* Debug port address offset*/ + MII_ADDR_DEBUGPORT_DATA = 0x001e,/* Debug port data */ +}; + +/* definitions for MII_ADDR_RESET register definitions*/ +#define MII_ADDR_RESET_RESTART_AUTONEG (1 << 9) +#define MII_ADDR_RESET_ENABLE_AUTONEG (1 << 12) +#define MII_ADDR_RESET_ENABLE_LOOPBACK (1<<14) +#define MII_ADDR_RESET_SOFT_RESET (1<<15) +/* flags for autonegotiaion register MII_ADDR_AUTONEG_ADV, + All writes to this register should be followed by a soft + reset on the phy + The list is not exhaustive, only required fields added + */ +#define MII_AUTONEG_10BT_HALF (1<<5) +#define MII_AUTONEG_10BT_FULL (1<<6) +#define MII_AUTONEG_100BT_HALF (1<<7) +#define MII_AUTONEG_100BT_FULL (1<<8) +#define MII_AUTONEG_PAUSE (1<<9) +#define MII_1000BASET_1000BT_HALF (1<<8) +#define MII_1000BASET_1000BT_FULL (1<<9) +enum __gmac_reg_mii_ctrl{ + MII_CTRL_FULL_DPLX = 0x0100,/*Full Duplex mode*/ + MII_CTRL_SPEED_100 = 0x2000,/*Link Speed 100 Mbps*/ + MII_CTRL_LOOPBACK = 0x4000,/*Enable Loopback mode at PHY*/ + MII_CTRL_RESET = 0x8000,/*BMCR reset*/ +}; +enum __gma_reg_mii_cmd{ + MII_CMD_WRITE = 0x0, + MII_CMD_READ = 0x1,/*Perform a Read cycle*/ +}; +enum __gmac_reg_fifo_cfg0{ + FIFO_CFG0_EN = 0x1f00,/*Enable all the Fifo module*/ +}; +enum __gmac_reg_fifo_cfg1{ + FIFO_CFG1_SIZE_2K = (0x7ff << 16),/*Fifo size is 2K*/ +}; +enum __gmac_reg_fifo_cfg4{ + FIFO_CFG4_RX_ALL = 0x3ffff,/*receive all frames*/ +}; +enum __gmac_reg_if_ctrl{ + IF_CTRL_SPEED_100 = (1 << 16),/*Interface speed 100 Mbps for MII*/ +}; + + +#define MAX_MDIO_IO_LEN 14 +#define MDIO_REG_WIDTH 4 +#define MDIO_REG_BASE 0x54200 +#define MDIO_REG_TO_OFFSET( __reg_number__)\ + (MDIO_REG_BASE + (MDIO_REG_WIDTH * (__reg_number__))) + +#define MDIO_OWN_TGT 0x01 +#define MDIO_OWN_HST 0x02 +#define MDIO_REG_WRITE_DELAY 5 /* 5 micro seconds */ + +/*************************GMAC Data types*******************************/ +typedef enum __gmac_pkt_type{ + GMAC_PKT_IS_BCAST, + GMAC_PKT_IS_UCAST +}__gmac_pkt_type_t; + +struct __ethhdr{ + unsigned char dst[ETH_ALEN];/*destination eth addr */ + unsigned char src[ETH_ALEN]; /*source ether addr*/ + A_UINT16 etype;/*ether type*/ +}__attribute__((packed)); +/** + * @brief this is will be in big endian format + */ +struct __athhdr{ +#ifdef LITTLE_ENDIAN + A_UINT8 proto:6, + res:2; +#else + A_UINT8 res:2, + proto:6; +#endif + A_UINT8 res_lo; + A_UINT16 res_hi; +}__attribute__((packed)); + +typedef struct __gmac_hdr{ + struct __ethhdr eth; + struct __athhdr ath; + A_UINT16 align_pad;/*pad it for 4 byte boundary*/ +}__attribute__((packed)) __gmac_hdr_t; + +/*********************************GMAC softC************************/ + +typedef struct __gmac_softc{ + __gmac_hdr_t hdr; + A_UINT16 gran; + HIF_CALLBACK sw; +}__gmac_softc_t; + + + +#endif + diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/hif_pci.h b/target_firmware/magpie_fw_dev/target/inc/magpie/hif_pci.h new file mode 100755 index 0000000..485a659 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/hif_pci.h @@ -0,0 +1,49 @@ + +#ifndef __HIF_PCI_H +#define __HIF_PCI_H + +#include +#include + + +#define PCI_MAX_DATA_PKT_LEN 1664 +#define PCI_MAX_CMD_PKT_LEN 512 +#define PCI_MAX_BOOT_DESC 2 + +typedef enum hif_pci_pipe_rx{ + HIF_PCI_PIPE_RX0, /*Normal Priority RX*/ + HIF_PCI_PIPE_RX1, + HIF_PCI_PIPE_RX2, + HIF_PCI_PIPE_RX3, + HIF_PCI_PIPE_RX_MAX +}hif_pci_pipe_rx_t; + +typedef enum hif_pci_pipe_tx{ + HIF_PCI_PIPE_TX0, /*Normal Priority TX*/ + HIF_PCI_PIPE_TX1, + HIF_PCI_PIPE_TX_MAX +}hif_pci_pipe_tx_t; + +typedef struct __pci_softc{ + HIF_CALLBACK sw; +}__pci_softc_t; + +struct hif_pci_api{ + void (*pci_boot_init)(void); + hif_handle_t (*pci_init)(HIF_CONFIG *pConfig); + void (*pci_reset)(void); + void (*pci_enable)(void); + void (*pci_reap_xmitted)(__pci_softc_t *sc, + dma_engine_t eng_no); + void (*pci_reap_recv)(__pci_softc_t *sc, dma_engine_t eng_no); + A_UINT8 (*pci_get_pipe)(dma_engine_t eng); + dma_engine_t (*pci_get_tx_eng)(hif_pci_pipe_tx_t pipe); + dma_engine_t (*pci_get_rx_eng)(hif_pci_pipe_rx_t pipe); + +}; + +void hif_pci_api_install(struct hif_pci_api *apis); +void hif_pci_module_install(struct hif_api *apis); +#endif + + diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/hif_usb.h b/target_firmware/magpie_fw_dev/target/inc/magpie/hif_usb.h new file mode 100755 index 0000000..addc17e --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/hif_usb.h @@ -0,0 +1,58 @@ +/* + * @File: mbox_hw.h + * + * @Abstract: mailbox hardware definitions + * + * @Notes: + * * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef __HIF_USB_H__ +#define __HIF_USB_H__ + +#include + +#include +#include +#include +//#include +//#include + +#define HIF_USB_PIPE_TX 1 +#define HIF_USB_PIPE_RX 2 +#define HIF_USB_PIPE_INTERRUPT 3 +#define HIF_USB_PIPE_COMMAND 4 +#define HIF_USB_PIPE_HP_TX 5 +#define HIF_USB_PIPE_MP_TX 6 + +struct VBUF_QUEUE +{ + VBUF *head; + VBUF *tail; +}; + + /* the mailbox hardware layer context */ +typedef struct _HIF_USB_CONTEXT { + HIF_CALLBACK hifCb; + struct zsDmaQueue dnQ; + struct zsTxDmaQueue upQ; +#if SYSTEM_MODULE_HP_EP5 + struct zsDmaQueue hpdnQ; // high priority +#endif +#if SYSTEM_MODULE_HP_EP6 + struct zsDmaQueue mpdnQ; // medium priority +#endif + //struct VBUF_QUEUE upVbufQ; + VBUF *cmdQueue; + struct VBUF_QUEUE eventBufQ; + + // Left a door for extension the structure + void *pReserved; +} HIF_USB_CONTEXT; + +void hif_usb_module_install(struct hif_api *apis); + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/htc_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/htc_api.h new file mode 100755 index 0000000..ac053c0 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/htc_api.h @@ -0,0 +1,126 @@ +/* + * @File: htc_api.h + * + * @Abstract: host-target communications API + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef __HTC_API_H__ +#define __HTC_API_H__ + +#include +#include +//#include +//#include +#include +#include + +#define HTC_HDR_SZ HTC_HDR_LENGTH +#define HTC_BUFSZ_MAX_SEND 2048 + +typedef void (* HTC_SERVICE_ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, adf_nbuf_t, void *ServiceCtx); +typedef void (* HTC_SERVICE_ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, void *ServiceCtx); + +/* HTC service structure : + * the caller is required to allocate storage for the service structure and register the + * structure using HTC_RegisterService() The service must set the following fields: + * ProcessRecvMsg + * ProcessSendBufferComplete + * ProcessConnect + * ServiceID + * MaxSvcMsgSize (for message validation) + * */ +typedef struct _HTC_SERVICE { + struct _HTC_SERVICE *pNext; + /* Callback for processing receive messages. HTC calls this callback whenever a + * message arrives on the endpoint assigned to this service. + * HTC_BUFFER is a chain of buffers containing a full application message. + * HTC_BUFFER->buffer points to the start of the msg buffer (past the HTC header) */ + //void (* ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, HTC_BUFFER *); + void (* ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, adf_nbuf_t, void *ServiceCtx); + /* callback to process completed send buffers */ + //void (* ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, HTC_BUFFER *); + void (* ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, void *ServiceCtx); + /* optional callback when a connection request occurs. + * The EndpointID is the assigned endpoint, the callback returns a connect + * response status code to allow or disallow the connection. + * pDataIn points to the optional meta data supplied in the connection request + * pDataOut points to a buffer to send back meta data + * If no callback is supplied, HTC assumes the connect is allowed */ + A_UINT8 (* ProcessConnect)(struct _HTC_SERVICE *pService, + HTC_ENDPOINT_ID EndpointID, + A_UINT8 *pDataIn, + int LengthIn, + A_UINT8 *pDataOut, + int *pLengthOut); + A_UINT16 ServiceID; /* service ID to match connection requests */ + A_UINT16 ServiceFlags; /* service flags */ + A_UINT16 MaxSvcMsgSize; /* maximum length of service-specific messages exchanged on the endpoint */ + A_UINT16 TrailerSpcCheckLimit; /* amount of space in each send buffer that HTC can check for trailer + data. This should be set to the smallest HTC buffer that can be sent + through the service. The service can disable trailer data insertion + by setting this value to 0. */ + void *ServiceCtx; +} HTC_SERVICE; + +#define HTC_SERVICE_FLAGS_CONNECTED (1 << 0) /* service has at least 1 connection */ + +#define IS_SERVICE_CONNECTED(s) ((s)->ServiceFlags & HTC_SERVICE_FLAGS_CONNECTED) + + /* configuration settings for the WMI service */ +typedef struct _HTC_CONFIG { + int CreditSize; /* */ + int CreditNumber; + //int ControlDownLinkPipeID; + //int ControlUpLinkPipeID; + adf_os_handle_t OSHandle; + hif_handle_t HIFHandle; + pool_handle_t PoolHandle; +} HTC_CONFIG; + +typedef struct _HTC_BUF_CONTEXT { + A_UINT8 end_point; + A_UINT8 htc_flags; /* htc flags (used by HTC layer only) */ +} HTC_BUF_CONTEXT; + +typedef void* htc_handle_t; + +/* + * setup complete function, supplied by HTC caller at HTC_init time. + * HTC calls this function after the host has indicated that the service connection + * phase is complete. + * + */ +typedef void (* HTC_SETUP_COMPLETE_CB)(void); + +struct htc_apis { + htc_handle_t (* _HTC_Init)(HTC_SETUP_COMPLETE_CB, HTC_CONFIG *pConfig); + void (* _HTC_Shutdown)(htc_handle_t); + void (* _HTC_RegisterService)(htc_handle_t, HTC_SERVICE *); + void (* _HTC_Ready)(htc_handle_t); + void (* _HTC_ReturnBuffers)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t); + void (* _HTC_ReturnBuffersList)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_queue_t); + void (* _HTC_SendMsg)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t); + int (* _HTC_GetReservedHeadroom)(htc_handle_t handle); + + //void (* _HTC_PauseRecv)(HTC_ENDPOINT_ID EndpointID); + //void (* _HTC_ResumeRecv)(HTC_ENDPOINT_ID EndpointID); + //void (* _HTC_AddBufferResources)(int buffers); + + /* These APIs below are for patch purpose only */ + void (*_HTC_MsgRecvHandler)(adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *context); + void (*_HTC_SendDoneHandler)(adf_nbuf_t buf, void *context); + void (*_HTC_ControlSvcProcessMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *arg); + void (*_HTC_ControlSvcProcessSendComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers, void *arg); + + void *pReserved; /* for expansion if need be */ +}; + +extern void htc_module_install(struct htc_apis *pAPIs); + +#endif /* _HTC_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/intr_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/intr_api.h new file mode 100755 index 0000000..7481f6b --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/intr_api.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __INTR_API_H__ +#define __INTR_API_H__ + +/* + * Interrupt handler, for application-managed interrupts. + * When an interrupt occurs, it is automatically disabled. + * See A_WMAC_INTR_ATTACH() and A_MBOX_INTR_ATTACH(). + * + * If a handler returns A_HANDLER_DONE, the interrupt is + * re-enabled. The OS calls the handler next time service + * is required. This is the normal case for a handler. + * + * If a handler returns A_HANDLER_YIELD, the interrupt + * remains masked. The handler is called again when + * it is "convenient". This gives the OS an opportunity + * to run other code/handlers. A handler should return + * A_HANDLER_YIELD if it might dominate the CPU for too + * long. + * + * If a handler returns A_HANDLER_NOENABLE, the interrupt + * remains disabled. It is up to the application to re-enable + * the interrupt (via A_*_INTR_UNMASK) when it's appropriate. + * + * Note that many combinations of interrupt functions and + * interrupt vectors are NOT supported: Callers should use + * only the macros defined in cmnos_api.h to access the + * interrupt API. + */ +#include "cmnos_api.h" + +typedef uint32_t A_old_intr_t; + +////////////////////////////////////////////////////////////////// +// this is copied from mercury/cmnos_xtensa.h +/* + * These are CMNOS interrupt manifest constants. + * They have specially-chosen values that align with hardware and or + * operating system values (see cmnos_interrupt_info). + */ +#if defined(__XTENSA__) +/* + * Enumeration of low and medium priority interrupt numbers + * which match the CPU hardware configuration: + */ + +/* XTensa Level 1 interrupt */ +#define A_INUM_SOFTWARE 0 /* currently unused */ + +/* XTensa Level2 interrupts */ +#define A_INUM_XTTIMER 1 /* currently unused */ + +#define A_INUM_TBD_0 2 /* TBD */ +#define A_INUM_CPU_WDT 3 /* RST_CPU watchodg interrupt */ +#define A_INUM_GMAC_DMA 4 /* GMAC DMA interrupt */ +#define A_INUM_GMAC_MDIO 5 /* GMAC MDIO interrupt */ +#define A_INUM_HOST_DMA 6 /* HOST DMA */ +#define A_INUM_CPU_GEN_TIMER 7 /* CPU general timer */ +#define A_INUM_TBD_8 8 /* TBD */ +#define A_INUM_TBD_9 9 /* TBD */ +#define A_INUM_USB_CTRL 10 /* USB core control */ +#define A_INUM_USB_DMA 11 /* USB DMA */ +#define A_INUM_TBD_12 12 /* TBD */ +#define A_INUM_TBD_13 13 /* TBD */ +#define A_INUM_EMUX_CPU 14 /* EMUX CPU */ +#define A_INUM_GPIO_CPU 15 /* GPIO CPU interrupt */ +#define A_INUM_TBD_16 16 /* TBD */ +#define A_INUM_PCIE_CPU 17 /* CPU PCIE interrupt */ +#define A_INUM_RST_CPU_NMI 18 /* RST CPU nmi interrupt */ + +/* Number of interrupts that map directly into CPU/hal interrupt bits. */ +#define NUM_DIRECT_INTR 19 + +#endif +////////////////////////////////////////////////////////////////// + +#define CMNOS_IMASK_XTTIMER (1<>2)) + +#endif /* _MEM_ADDRS_H_ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/magpie_regdump.h b/target_firmware/magpie_fw_dev/target/inc/magpie/magpie_regdump.h new file mode 100755 index 0000000..c2e458e --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/magpie_regdump.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __MAGPIE_REGDUMP_H__ +#define __MAGPIE_REGDUMP_H__ + +#if !defined(__ASSEMBLER__) +/* + * XTensa CPU state + * This must match the state saved by the target exception handler. + */ +struct XTensa_exception_frame_s { + uint32_t xt_pc; + uint32_t xt_ps; + uint32_t xt_sar; + uint32_t xt_vpri; + uint32_t xt_a2; + uint32_t xt_a3; + uint32_t xt_a4; + uint32_t xt_a5; + uint32_t xt_exccause; + uint32_t xt_lcount; + uint32_t xt_lbeg; + uint32_t xt_lend; + + /* Extra info to simplify post-mortem stack walkback */ +#define MAGPIE_REGDUMP_FRAMES 5 + struct { + uint32_t a0; /* pc */ + uint32_t a1; /* sp */ + uint32_t a2; + uint32_t a3; + } wb[MAGPIE_REGDUMP_FRAMES]; +}; + +typedef struct XTensa_exception_frame_s CPU_exception_frame_t; +#define RD_SIZE sizeof(CPU_exception_frame_t) + +#endif +#endif /* __MAGPIE_REGDUMP_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/mem_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/mem_api.h new file mode 100755 index 0000000..aff26ef --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/mem_api.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __MEM_API_H__ +#define __MEM_API_H__ +struct mem_api { + void (* _mem_init)(void); + void *(* _memset)(void *, int, unsigned int); + void *(* _memcpy)(void *, const void *, unsigned int); + void *(* _memmove)(void *, const void *, unsigned int); + int (* _memcmp)(const void *, const void *, unsigned int); +}; +#endif /* __MEM_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/misc_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/misc_api.h new file mode 100755 index 0000000..9b9dc78 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/misc_api.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __MISC_API_H__ +#define __MISC_API_H__ + +enum hostif_s{ + HIF_USB = 0, + HIF_PCIE, + HIF_GMAC, + HIF_PCI, + + // HIF should be added above here + HIF_NUM, + HIF_NONE + +}; + +typedef enum hostif_s A_HOSTIF; + +struct register_dump_s; + +struct misc_api { + void (* _system_reset)(void); + void (* _mac_reset)(void); + void (* _assfail)(struct register_dump_s *); + void (* _misaligned_load_handler)(struct register_dump_s *); + + void (* _report_failure_to_host)(struct register_dump_s *, int); + int (* _target_id_get)(void); + A_HOSTIF (* _is_host_present)(void); + + uint8_t (*_kbhit)(uint8_t); + + uint16_t (* _rom_version_get)(void); +}; +#endif /* __MISC_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/opt_ah.h b/target_firmware/magpie_fw_dev/target/inc/magpie/opt_ah.h new file mode 100755 index 0000000..3509d18 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/opt_ah.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#define AH_SUPPORT_AR5416 1 +#define AH_SUPPORT_2133 1 +#define AH_SUPPORT_5413 1 +//#define AH_DEBUG 1 +//#define AR5416_EMULATION 1 +#define ATH_FORCE_PPM 1 +#define ATH_FORCE_BIAS 1 +#define AH_SUPPORT_DFS 1 diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/printf_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/printf_api.h new file mode 100755 index 0000000..00bae4a --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/printf_api.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __PRINTF_API_H__ +#define __PRINTF_API_H__ + +struct printf_api { + void (* _printf_init)(void); + int (* _printf)(const char * fmt, ...); +}; + +/* NB: The printf module requires the serial module. */ +void cmnos_printf_module_install(struct printf_api *tbl); +int cmnos_printf(const char *fmt, ...); + + + +#endif /* __PRINTF_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/regdump.h b/target_firmware/magpie_fw_dev/target/inc/magpie/regdump.h new file mode 100755 index 0000000..018638d --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/regdump.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __REGDUMP_H__ +#define __REGDUMP_H__ + +#include "magpie_regdump.h" + + +#if !defined(__ASSEMBLER__) + +/* + * XTensa CPU state + * This must match the state saved by the target exception handler. + */ + +#define RD_SIZE sizeof(CPU_exception_frame_t) + +/* + * Target CPU state at the time of failure is reflected + * in a register dump, which the Host can fetch through + * the diagnostic window. + */ +struct register_dump_s { + uint32_t target_id; /* Target ID */ + uint32_t assline; /* Line number (if assertion failure) */ + uint32_t pc; /* Program Counter at time of exception */ + uint32_t badvaddr; /* Virtual address causing exception */ + CPU_exception_frame_t exc_frame; /* CPU-specific exception info */ + + /* Could copy top of stack here, too.... */ +}; + + +#endif /* __ASSEMBLER__ */ +#endif /* __REGDUMP_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/romp_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/romp_api.h new file mode 100755 index 0000000..1a57c03 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/romp_api.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*************************************************************************/ +/* Copyright (c) 2008 Atheros Communications, Inc., All Rights Reserved */ +/* */ +/* Module Name : romp_api.h */ +/* */ +/* Abstract */ +/* This file contains definition of data structure and interface */ +/* */ +/* NOTES */ +/* None */ +/* */ +/*************************************************************************/ + +#ifndef _ROMP_API_H_ +#define _ROMP_API_H_ + +#include "dt_defs.h" + +/******** hardware API table structure (API descriptions below) *************/ +struct romp_api { + void (*_romp_init)(void); + BOOLEAN (*_romp_download)(uint16_t ); + BOOLEAN (*_romp_install)(void); + BOOLEAN (*_romp_decode)(uint32_t ); +}; + +#define _ROMP_MAGIC_ "[PaTcH]" + +struct rom_patch_st { + uint16_t crc16; // crc filed to maintain the integrity + uint16_t len; // length of the patch code + uint32_t ld_addr; // load address of the patch code + uint32_t fun_addr; // entry address of the patch code + uint8_t *pfun; // patch code +}; + + +struct eep_redir_addr { + uint16_t offset; + uint16_t size; +}; + + +/************************* EXPORT function ***************************/ +uint16_t cal_crc16(uint32_t sz, uint8_t *p); + +#endif // end of _UART_API_H_ + diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/string_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/string_api.h new file mode 100755 index 0000000..1a3fa82 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/string_api.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __STRING_API_H__ +#define __STRING_API_H__ +struct string_api { + void (* _string_init)(void); + char *(* _strcpy)(char *, const char *); + char *(* _strncpy)(char *, const char *, unsigned int); + int (* _strlen)(const char *); + int (* _strcmp)(const char *, const char *); + int (* _strncmp)(const char *, const char *, unsigned int); +}; +#endif /* __STRING_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/sys_cfg.h b/target_firmware/magpie_fw_dev/target/inc/magpie/sys_cfg.h new file mode 100755 index 0000000..15e22de --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/sys_cfg.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*************************************************************************/ +/* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */ +/* */ +/* Module Name : sys_cfg.h */ +/* */ +/* Abstract */ +/* This file contains definition of platform and sysmte config . */ +/* */ +/* NOTES */ +/* None */ +/* */ +/*************************************************************************/ + +#ifndef _SYS_CFG_H_ +#define _SYS_CFG_H_ + +/************************** FPGA version **************************/ +#define MAGPIE_FPGA_RAM_256K 1 + +/************************** ROM DEFINE ***************************/ + +#if defined(_ROM_) +#include "rom_cfg.h" + +#if MAGPIE_FPGA_RAM_256K == 1 +#undef MAX_BUF_NUM +#define MAX_BUF_NUM 100 +#endif + +#elif defined(_RAM_) + +#include "rom_cfg.h" +#include "magpie_mem.h" + +/************************* Resource DEFS ***********************/ +#define MAX_DESC_NUM 100 + +#ifdef RX_SCATTER +#define MAX_BUF_NUM 60 +#else +#define MAX_BUF_NUM 40 +#endif + +#if MAGPIE_FPGA_RAM_256K == 1 +#undef MAX_BUF_NUM +#define MAX_BUF_NUM 100 +#endif + +#undef SYSTEM_MODULE_DBG +#define SYSTEM_MODULE_DBG 1 + +/************************* WLAN DEFS ***************************/ +#define MAGPIE_ENABLE_WLAN 1 +#define MAGPIE_ENABLE_PCIE 1 +#define MAGPIE_ENABLE_WLAN_IN_TARGET 0 +#define MAGPIE_ENABLE_WLAN_SELF_TX 0 +#define MAGPIE_ENABLE_WLAN_RATE_CTRL 1 +#define WLAN_MAX_RXBUF 15 +#define WLAN_MAX_TXBUF 10 + +/****************************** WATCH DOG *******************************/ +#define WDT_DEFAULT_TIMEOUT_VALUE 3*ONE_MSEC*1000 // Initial value is 3 seconds, firmware changes it to 65 milliseconds + +#endif + + +#endif /* _SYS_CFG_H_ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/tasklet_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/tasklet_api.h new file mode 100755 index 0000000..3bd755f --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/tasklet_api.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __TASKLET_API_H__ +#define __TASKLET_API_H__ + +//typedef int A_tasklet_t; + +typedef void (*A_TASKLET_FUNC)(void *arg); + +#define A_TASKLET_STATE_DISABLE 0 +#define A_TASKLET_STATE_SCHEDULED 1 +#define A_TASKLET_STATE_RUNNING 2 + +struct _tasklet { + A_TASKLET_FUNC func; + void *arg; + int state; + struct _tasklet *next; +}; + +typedef struct _tasklet A_tasklet_t; + +struct tasklet_api { + void (* _tasklet_init)(void); + void (* _tasklet_init_task)(A_TASKLET_FUNC, void * arg, A_tasklet_t *); + void (* _tasklet_disable)(A_tasklet_t *); + void (* _tasklet_schedule)(A_tasklet_t *); + void (* _tasklet_run)(void); +}; +#endif /* __TASKLET_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/timer_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/timer_api.h new file mode 100755 index 0000000..4ba9faf --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/timer_api.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __TIMER_API_H__ +#define __TIMER_API_H__ +/* + * In order to remain completely independent of OS header files, + * "_SPACE" structures are declared with sufficient room to hold + * corresponding OS structures. + */ +typedef unsigned int _A_TIMER_SPACE[5]; +typedef _A_TIMER_SPACE A_timer_t; +#define A_TIMER A_timer_t /* historical */ + +typedef unsigned int A_HANDLE; /* historical */ +typedef void A_TIMER_FUNC(A_HANDLE timer_handle, void *arg); + +struct timer_api { + void (* _timer_init)(void); + void (* _timer_arm)(A_timer_t *, unsigned int); + void (* _timer_disarm)(A_timer_t *); + void (* _timer_setfn)(A_timer_t *, A_TIMER_FUNC, void *); + void (* _timer_run)(void); +}; +#endif /* __TIMER_API_H__ */ + diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/uart_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/uart_api.h new file mode 100755 index 0000000..b13f362 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/uart_api.h @@ -0,0 +1,343 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*************************************************************************/ +/* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */ +/* */ +/* Module Name : uart.h */ +/* */ +/* Abstract */ +/* This file contains definition of uart registers, marco and api. */ +/* */ +/* NOTES */ +/* None */ +/* */ +/*************************************************************************/ + +#ifndef _UART_API_H_ +#define _UART_API_H_ + +#include "reg_defs.h" + +/************************* Register Process marco ************************/ +#define UART_REG_WRITE(addr, val) HAL_WORD_REG_WRITE(UART_BASE_ADDRESS|(uint32_t)(addr), (val)) +#define UART_REG_READ(addr) HAL_WORD_REG_READ(UART_BASE_ADDRESS|(uint32_t)(addr)) + +/************************** Register deinition ***************************/ +#define RBR_ADDRESS 0x00051000 +#define RBR_OFFSET 0x00000000 +#define RBR_RBR_MSB 7 +#define RBR_RBR_LSB 0 +#define RBR_RBR_MASK 0x000000ff +#define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB) +#define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK) + +#define THR_ADDRESS 0x00051000 +#define THR_OFFSET 0x00000000 +#define THR_THR_MSB 7 +#define THR_THR_LSB 0 +#define THR_THR_MASK 0x000000ff +#define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB) +#define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK) + +#define DLL_ADDRESS 0x00051000 +#define DLL_OFFSET 0x00000000 +#define DLL_DLL_MSB 7 +#define DLL_DLL_LSB 0 +#define DLL_DLL_MASK 0x000000ff +#define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB) +#define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK) + +#define DLH_ADDRESS 0x00051004 +#define DLH_OFFSET 0x00000004 +#define DLH_DLH_MSB 7 +#define DLH_DLH_LSB 0 +#define DLH_DLH_MASK 0x000000ff +#define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB) +#define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK) + +#define IER_ADDRESS 0x00051004 +#define IER_OFFSET 0x00000004 +#define IER_EDDSI_MSB 3 +#define IER_EDDSI_LSB 3 +#define IER_EDDSI_MASK 0x00000008 +#define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB) +#define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK) +#define IER_ELSI_MSB 2 +#define IER_ELSI_LSB 2 +#define IER_ELSI_MASK 0x00000004 +#define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB) +#define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK) +#define IER_ETBEI_MSB 1 +#define IER_ETBEI_LSB 1 +#define IER_ETBEI_MASK 0x00000002 +#define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB) +#define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK) +#define IER_ERBFI_MSB 0 +#define IER_ERBFI_LSB 0 +#define IER_ERBFI_MASK 0x00000001 +#define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB) +#define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK) + +#define IIR_ADDRESS 0x00051008 +#define IIR_OFFSET 0x00000008 +#define IIR_FIFO_STATUS_MSB 7 +#define IIR_FIFO_STATUS_LSB 6 +#define IIR_FIFO_STATUS_MASK 0x000000c0 +#define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB) +#define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK) +#define IIR_IID_MSB 3 +#define IIR_IID_LSB 0 +#define IIR_IID_MASK 0x0000000f +#define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB) +#define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK) + +#define FCR_ADDRESS 0x00051008 +#define FCR_OFFSET 0x00000008 +#define FCR_RCVR_TRIG_MSB 7 +#define FCR_RCVR_TRIG_LSB 6 +#define FCR_RCVR_TRIG_MASK 0x000000c0 +#define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB) +#define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK) +#define FCR_DMA_MODE_MSB 3 +#define FCR_DMA_MODE_LSB 3 +#define FCR_DMA_MODE_MASK 0x00000008 +#define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB) +#define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK) +#define FCR_XMIT_FIFO_RST_MSB 2 +#define FCR_XMIT_FIFO_RST_LSB 2 +#define FCR_XMIT_FIFO_RST_MASK 0x00000004 +#define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB) +#define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK) +#define FCR_RCVR_FIFO_RST_MSB 1 +#define FCR_RCVR_FIFO_RST_LSB 1 +#define FCR_RCVR_FIFO_RST_MASK 0x00000002 +#define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB) +#define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK) +#define FCR_FIFO_EN_MSB 0 +#define FCR_FIFO_EN_LSB 0 +#define FCR_FIFO_EN_MASK 0x00000001 +#define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB) +#define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK) + +#define LCR_ADDRESS 0x0005100c +#define LCR_OFFSET 0x0000000c +#define LCR_DLAB_MSB 7 +#define LCR_DLAB_LSB 7 +#define LCR_DLAB_MASK 0x00000080 +#define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB) +#define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK) +#define LCR_BREAK_MSB 6 +#define LCR_BREAK_LSB 6 +#define LCR_BREAK_MASK 0x00000040 +#define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB) +#define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK) +#define LCR_EPS_MSB 4 +#define LCR_EPS_LSB 4 +#define LCR_EPS_MASK 0x00000010 +#define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB) +#define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK) +#define LCR_PEN_MSB 3 +#define LCR_PEN_LSB 3 +#define LCR_PEN_MASK 0x00000008 +#define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB) +#define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK) +#define LCR_STOP_MSB 2 +#define LCR_STOP_LSB 2 +#define LCR_STOP_MASK 0x00000004 +#define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB) +#define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK) +#define LCR_CLS_MSB 1 +#define LCR_CLS_LSB 0 +#define LCR_CLS_MASK 0x00000003 +#define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB) +#define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK) + +#define MCR_ADDRESS 0x00051010 +#define MCR_OFFSET 0x00000010 +#define MCR_LOOPBACK_MSB 5 +#define MCR_LOOPBACK_LSB 5 +#define MCR_LOOPBACK_MASK 0x00000020 +#define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB) +#define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK) +#define MCR_OUT2_MSB 3 +#define MCR_OUT2_LSB 3 +#define MCR_OUT2_MASK 0x00000008 +#define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB) +#define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK) +#define MCR_OUT1_MSB 2 +#define MCR_OUT1_LSB 2 +#define MCR_OUT1_MASK 0x00000004 +#define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB) +#define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK) +#define MCR_RTS_MSB 1 +#define MCR_RTS_LSB 1 +#define MCR_RTS_MASK 0x00000002 +#define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB) +#define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK) +#define MCR_DTR_MSB 0 +#define MCR_DTR_LSB 0 +#define MCR_DTR_MASK 0x00000001 +#define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB) +#define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK) + +#define LSR_ADDRESS 0x00051014 +#define LSR_OFFSET 0x00000014 +#define LSR_FERR_MSB 7 +#define LSR_FERR_LSB 7 +#define LSR_FERR_MASK 0x00000080 +#define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB) +#define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK) +#define LSR_TEMT_MSB 6 +#define LSR_TEMT_LSB 6 +#define LSR_TEMT_MASK 0x00000040 +#define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB) +#define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK) +#define LSR_THRE_MSB 5 +#define LSR_THRE_LSB 5 +#define LSR_THRE_MASK 0x00000020 +#define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB) +#define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK) +#define LSR_BI_MSB 4 +#define LSR_BI_LSB 4 +#define LSR_BI_MASK 0x00000010 +#define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB) +#define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK) +#define LSR_FE_MSB 3 +#define LSR_FE_LSB 3 +#define LSR_FE_MASK 0x00000008 +#define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB) +#define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK) +#define LSR_PE_MSB 2 +#define LSR_PE_LSB 2 +#define LSR_PE_MASK 0x00000004 +#define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB) +#define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK) +#define LSR_OE_MSB 1 +#define LSR_OE_LSB 1 +#define LSR_OE_MASK 0x00000002 +#define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB) +#define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK) +#define LSR_DR_MSB 0 +#define LSR_DR_LSB 0 +#define LSR_DR_MASK 0x00000001 +#define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB) +#define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK) + +#define MSR_ADDRESS 0x00051018 +#define MSR_OFFSET 0x00000018 +#define MSR_DCD_MSB 7 +#define MSR_DCD_LSB 7 +#define MSR_DCD_MASK 0x00000080 +#define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB) +#define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK) +#define MSR_RI_MSB 6 +#define MSR_RI_LSB 6 +#define MSR_RI_MASK 0x00000040 +#define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB) +#define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK) +#define MSR_DSR_MSB 5 +#define MSR_DSR_LSB 5 +#define MSR_DSR_MASK 0x00000020 +#define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB) +#define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK) +#define MSR_CTS_MSB 4 +#define MSR_CTS_LSB 4 +#define MSR_CTS_MASK 0x00000010 +#define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB) +#define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK) +#define MSR_DDCD_MSB 3 +#define MSR_DDCD_LSB 3 +#define MSR_DDCD_MASK 0x00000008 +#define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB) +#define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK) +#define MSR_TERI_MSB 2 +#define MSR_TERI_LSB 2 +#define MSR_TERI_MASK 0x00000004 +#define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB) +#define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK) +#define MSR_DDSR_MSB 1 +#define MSR_DDSR_LSB 1 +#define MSR_DDSR_MASK 0x00000002 +#define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB) +#define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK) +#define MSR_DCTS_MSB 0 +#define MSR_DCTS_LSB 0 +#define MSR_DCTS_MASK 0x00000001 +#define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB) +#define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK) + + +/************************** config definition ***************************/ +#define UART_FIFO_SIZE 512 //Must be 2^N + +#define USE_POST_BUFFER 0 // ENABLE a tx buffer for post processing, +/*********************** data struction definition ************************/ +// data struction definition +struct uart_fifo { +#if USE_POST_BUFFER + uint8_t buf[UART_FIFO_SIZE]; +#endif + uint16_t start_index; + uint16_t end_index; + uint32_t overrun_err; +}; + + +struct uart_blk { + uint16_t debug_mode; + uint16_t baud; + struct uart_api *_uart; + struct uart_fifo _tx; +}; + + +/******** hardware API table structure (API descriptions below) *************/ +struct uart_api { + uint32_t (*_uart_init)(void); + void (*_uart_char_put)(uint8_t ch); + uint16_t (*_uart_char_get)(uint8_t* ch); + void (*_uart_str_out)(uint8_t* str); + void (*_uart_task)(void); + uint32_t (*_uart_status)(void); + void (*_uart_config)(uint16_t flag); + void (*_uart_hwinit)(uint32_t freq, uint32_t baud); + //void (*_uart_config)(uint8_t cmd, void *pData); +}; + +/************************* EXPORT function ***************************/ + + +#endif // end of _UART_API_H_ + diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/usb_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/usb_api.h new file mode 100755 index 0000000..c3ca296 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/usb_api.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef USB_API_H +#define USB_API_H + +#include "dt_defs.h" + +/******** hardware API table structure (API descriptions below) *************/ +struct usb_api { + void (*_usb_init)(void); + void (*_usb_rom_task)(void); + void (*_usb_fw_task)(void); + void (*_usb_init_phy)(void); + + // ep0 operation + void (*_usb_ep0_setup)(void); + + void (*_usb_ep0_tx)(void); + void (*_usb_ep0_rx)(void); + + // get/set interface + BOOLEAN (*_usb_get_interface)(void); + BOOLEAN (*_usb_set_interface)(void); + + // get/set configuration + BOOLEAN (*_usb_get_configuration)(void); + BOOLEAN (*_usb_set_configuration)(void); + + // standard/vendor command + BOOLEAN (*_usb_standard_cmd)(void); + void (*_usb_vendor_cmd)(void); + + void (*_usb_power_off)(void); + void (*_usb_reset_fifo)(void); + void (*_usb_gen_wdt)(void); + void (*_usb_jump_boot)(void); + + BOOLEAN (*_usb_clr_feature)(void); + BOOLEAN (*_usb_set_feature)(void); + BOOLEAN (*_usb_set_address)(void); + BOOLEAN (*_usb_get_descriptor)(void); + + BOOLEAN (*_usb_get_status)(void); + void (*_usb_setup_desc)(void); + void (*_usb_reg_out)(void); + void (*_usb_status_in)(void); + + void (*_usb_ep0_tx_data)(void); + void (*_usb_ep0_rx_data)(void); + + void (*_usb_clk_init)(void); +}; + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/usb_extr.h b/target_firmware/magpie_fw_dev/target/inc/magpie/usb_extr.h new file mode 100755 index 0000000..aa12bcc --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/usb_extr.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef USB_EXTR_H +#define USB_EXTR_H + +#if 0 +#include "dt_defs.h" +#include "usb_type.h" + +/* Variable for USB EP0 pipe (USB.c) */ +uint16_t *pu8DescriptorEX; +uint16_t u16TxRxCounter; +uint16_t *u8ConfigDescriptorEX; +//extern BOOLEAN bUsbEP0HaltSt; +Action eUsbCxFinishAction; +CommandType eUsbCxCommand; +BOOLEAN UsbChirpFinish; +uint16_t u8UsbConfigValue; +uint16_t u8UsbInterfaceValue; +uint16_t u8UsbInterfaceAlternateSetting; +uint16_t u16FirmwareComplete; + +uint16_t *UsbDeviceDescriptor; +uint16_t *String00Descriptor; +uint16_t *String10Descriptor; +uint16_t *String20Descriptor; +uint16_t *String30Descriptor; +uint16_t *u8DeviceQualifierDescriptorEX; +uint16_t *u8OtherSpeedConfigDescriptorEX; +uint16_t *u8UsbDeviceDescriptor; +uint16_t *u8String00Descriptor; +uint16_t *u8String10Descriptor; +uint16_t *u8String20Descriptor; +uint16_t *u8String30Descriptor; +#endif +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/usb_pre.h b/target_firmware/magpie_fw_dev/target/inc/magpie/usb_pre.h new file mode 100755 index 0000000..d3ae42b --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/usb_pre.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __USB_USER_PRE_H +#define __USB_USER_PRE_H + +#define FUSB200_MAX_EP 10 // 1..10 +#define FUSB200_MAX_FIFO 10 // 0.. 9 +#define EP0MAXPACKETSIZE 0x40 +// #define EP0FIFOSIZE 64 // EP0_FIFO +//JWEI 2003/04/29 +//#define EP0MAXPACKETSIZE 0x08 + +// Max. Packet Size define +#define MX_PA_SZ_8 8 +#define MX_PA_SZ_16 16 +#define MX_PA_SZ_32 32 +#define MX_PA_SZ_64 64 +#define MX_PA_SZ_128 128 +#define MX_PA_SZ_256 256 +#define MX_PA_SZ_512 512 +#define MX_PA_SZ_1024 1024 + +#define MASK_F0 0xF0 + +// Block Size define +#define BLK512BYTE 1 +#define BLK1024BYTE 2 + +#define BLK64BYTE 1 +#define BLK128BYTE 2 + +// Block toggle number define +#define SINGLE_BLK 1 +#define DOUBLE_BLK 2 +#define TRIBLE_BLK 3 + +// Endpoint transfer type +#define TF_TYPE_ISOCHRONOUS 1 +#define TF_TYPE_BULK 2 +#define TF_TYPE_INTERRUPT 3 + +// Endpoint or FIFO direction define +#define DIRECTION_IN 0 +#define DIRECTION_OUT 1 + +// FIFO number define +#define FIFO0 0x0 +#define FIFO1 0x1 +#define FIFO2 0x2 +#define FIFO3 0x3 +#define FIFO4 0x4 +#define FIFO5 0x5 +#define FIFO6 0x6 +#define FIFO7 0x7 +#define FIFO8 0x8 +#define FIFO9 0x9 +#define FIFO10 10 +#define FIFO11 11 +#define FIFO12 12 +#define FIFO13 13 +#define FIFO14 14 +#define FIFO15 15 + +// Descriptor Table uses the following parameters : fixed +#define DEVICE_LENGTH 0x12 +#define CONFIG_LENGTH 0x09 +#define INTERFACE_LENGTH 0x09 +#define EP_LENGTH 0x07 +#define DEVICE_QUALIFIER_LENGTH 0x0A + +//JWEI 2003/04/29 +// Endpoint number define +#define EP0 0 +#define EP1 1 +#define EP2 2 +#define EP3 3 +#define EP4 4 +#define EP5 5 +#define EP6 6 +#define EP7 7 +#define EP8 8 +#define EP9 9 +#define EP10 10 +#define EP11 11 +#define EP12 12 +#define EP13 13 +#define EP14 14 +#define EP15 15 + +#define STRING_00_LENGTH 0x04 +#define STRING_10_LENGTH 0x0c +#define STRING_20_LENGTH 0x18 +#define STRING_30_LENGTH 0x18 +#define STRING_40_LENGTH 0x04 +#define STRING_50_LENGTH 0x04 +#define STRING_60_LENGTH 0x04 +#define STRING_70_LENGTH 0x04 +#define STRING_80_LENGTH 0x04 +#define STRING_90_LENGTH 0x00 + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/usb_std.h b/target_firmware/magpie_fw_dev/target/inc/magpie/usb_std.h new file mode 100755 index 0000000..06cc3f8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/usb_std.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef USB_STD_H +#define USB_STD_H + +#define mDEV_REQ_REQ_DIR() (ControlCmd.Direction) +#define mDEV_REQ_REQ_TYPE() (ControlCmd.Type) +#define mDEV_REQ_REQ_RECI() (ControlCmd.Object) +#define mDEV_REQ_REQ() (ControlCmd.Request) +#define mDEV_REQ_VALUE() (ControlCmd.Value) +#define mDEV_REQ_VALUE_LOW() (mLOW_BYTE(mDEV_REQ_VALUE())) +#define mDEV_REQ_VALUE_HIGH() (mHIGH_BYTE(mDEV_REQ_VALUE())) +#define mDEV_REQ_INDEX() (ControlCmd.Index) +#define mDEV_REQ_LENGTH() (ControlCmd.Length) + +/******************** USB Protocol Definition *************************/ +/* Standard Request Code (Table 9-4) */ +#define USB_GET_STATUS 0 +#define USB_CLEAR_FEATURE 1 +#define USB_SET_FEATURE 3 +#define USB_SET_ADDRESS 5 +#define USB_GET_DESCRIPTOR 6 +#define USB_SET_DESCRIPTOR 7 +#define USB_GET_CONFIGURATION 8 +#define USB_SET_CONFIGURATION 9 +#define USB_GET_INTERFACE 10 +#define USB_SET_INTERFACE 11 +#define USB_SYNCH_FRAME 12 + +/* Descriptor Type (Table 9-5) */ +#define USB_DESC_TYPE_DEVICE 1 +#define USB_DESC_TYPE_CONFIG 2 +#define USB_DESC_TYPE_STRING 3 +#define USB_DESC_TYPE_INTERFACE 4 +#define USB_DESC_TYPE_ENDPOINT 5 + +/* Endpoint Attribute (Table 9-10) */ +#define USB_EP_ATTR_CTRL 0 +#define USB_EP_ATTR_ISOCH 1 +#define USB_EP_ATTR_BULK 2 +#define USB_EP_ATTR_INTRPT 3 + +/*********************** for USB 2.0 **********************************/ +// Table 9-5. Descriptor Types +#define DT_DEVICE 1 +#define DT_CONFIGURATION 2 +#define DT_STRING 3 +#define DT_INTERFACE 4 +#define DT_ENDPOINT 5 +#define DT_DEVICE_QUALIFIER 6 +#define DT_OTHER_SPEED_CONFIGURATION 7 +#define DT_INTERFACE_POWER 8 + +/**********************************************************************/ +// Values for bmAttributes Field in USB_CONFIGURATION_DESCRIPTOR +#define USB_BUS_POWERED 0x80 +#define USB_SELF_POWERED 0x40 +#define USB_REMOTE_WAKEUP 0x20 + +#define cUSB_REQTYPE_DIR_POS 7 +#define cUSB_REQTYPE_DIR_LEN 1 +#define cUSB_REQTYPE_TYPE_POS 5 +#define cUSB_REQTYPE_TYPE_LEN 2 +#define cUSB_REQTYPE_RX_POS 0 +#define cUSB_REQTYPE_RX_LEN 5 + +/* for USB State */ +#define cUSB_DEFAULT_STATE 0 +#define cUSB_ADDRESS_STATE 1 +#define cUSB_CONFIG_STATE 2 + +/* for Data transfer direction */ +#define bmUSB_HOST_DIR 7 /* Bit 7 */ +#define cUSB_DIR_HOST_OUT 0 +#define cUSB_DIR_HOST_IN 1 + +/* for Type */ +#define cUSB_REQTYPE_STD 0 +#define cUSB_REQTYPE_CLASS 1 +#define cUSB_REQTYPE_VENDOR 2 + +/* for Recipient */ +#define cUSB_REQTYPE_DEVICE 0 +#define cUSB_REQTYPE_INTERFACE 1 +#define cUSB_REQTYPE_ENDPOINT 2 +#define cUSB_REQTYPE_OTHER 3 + +/* for Descriptor Type */ +#define cUSB_DESTYPE_DEVICE 1 +#define cUSB_DESTYPE_CONFIG 2 +#define cUSB_DESTYPE_STRING 3 +#define cUSB_DESTYPE_INTERFACE 4 +#define cUSB_DESTYPE_ENDPOINT 5 +#define cUSB_DESTYPE_END cUSB_DESTYPE_ENDPOINT // for range check + +/* for Feature selector */ +#define cUSB_FEATSEL_RMWAKEUP 0 +#define cUSB_FEATSEL_EPHAL 1 +#define cUSB_FEATSEL_END cUSB_FEATSEL_EPHAL // for range check + +#define bmREQ_RECI 0 +#define bmwREQ_RECI 5 // mMASKS(bmwREQ_RECI, bmREQ_RECI) +#define bmREQ_TYPE 5 +#define bmwREQ_TYPE 2 // mMASKS(bmwREQ_TYPE, bmREQ_TYPE) +#define bmREQ_DIR 7 +#define bmwREQ_DIR 1 + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/usb_table.h b/target_firmware/magpie_fw_dev/target/inc/magpie/usb_table.h new file mode 100755 index 0000000..4fe3b57 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/usb_table.h @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _USB_TABLE_H_ +#define _USB_TABLE_H_ + +// UsbDeviceDescriptor +#define USB_DEVICE_DESC_TYPE 0x01 +#define USB_DEVICE_DESC_LEN 0x12 +#define USB_SPEC_VERSION 0x0200 +#define USB_DEVICE_CLASS 0xFF +#define USB_DEVICE_SUB_CLASS 0xFF +#define USB_DEVICE_PROTOCOL 0xFF +#define USB_MAX_PKT_SIZE 0x40 +#define USB_VENDOR_ID 0x0CF3 +#define USB_PRODUCT_ID 0x7010 +#define USB_DEVICE_BCD BOOTROM_VER +#define USB_MANUFACTURER_INDEX 0x10 +#define USB_PRODUCT_INDEX 0x20 +#define USB_SERIAL_INDEX 0x30 +#define USB_CONFIGURATION_NUM 0x01 +// end UsbDeviceDescriptor + +#define USB_CONFIG_DESC_TYPE 0x02 +#define USB_CONFIG_DESC_LEN 0x09 +//#define USB_TOTAL_DESC_LEN 0x002E // 4 ep +//#define USB_TOTAL_DESC_LEN 0x0035 // 5 ep +#define USB_TOTAL_DESC_LEN 0x003C // 6 ep +#define USB_INTERFACE_NUM 0x01 +#define USB_CONFIG_NUM 0x01 +#define USB_STRING_INDEX 0x00 +#define USB_ATTRIBUTE 0x80 +#define USB_MAX_POWER 0xFA + +#define USB_INTERFACE_DESC_TYPE 0x04 +#define USB_INTERFACE_DESC_LEN 0x09 +#define USB_INTERFACE_INDEX_NUM 0x00 +#define USB_INTERFACE_ALT_SETTING 0x00 +//#define USB_INTERFACE_EP_NUM 0x04 +//#define USB_INTERFACE_EP_NUM 0x05 +#define USB_INTERFACE_EP_NUM 0x06 +#define USB_INTERFACE_CLASS 0xFF +#define USB_INTERFACE_SUB_CLASS 0x00 +#define USB_INTERFACE_PROTOCOL 0x00 +#define USB_INTERFACE_STRING_INDEX 0x00 + +#define USB_EP_DESC_TYPE 0x05 +#define USB_EP_DESC_LEN 0x07 + +/* USB Endpoint attribute */ +#define bUSB_EP1_NUM 0x01 +#define bUSB_EP2_NUM 0x02 +#define bUSB_EP3_NUM 0x03 +#define bUSB_EP4_NUM 0x04 +#define bUSB_EP5_NUM 0x05 +#define bUSB_EP6_NUM 0x06 + +#define bUSB_EP_DIRECTION_IN 0x80 +#define bUSB_EP_DIRECTION_OUT 0x00 + +#define bUSB_EP_TYPE_CONTROL 0x00 +#define bUSB_EP_TYPE_ISOCHRONOUS 0x01 +#define bUSB_EP_TYPE_BULK 0x02 +#define bUSB_EP_TYPE_INTERRUPT 0x03 + +#define bUSB_EP_MAX_PKT_SIZE_64 0x0040 +#define bUSB_EP_MAX_PKT_SIZE_512 0x0200 + +/* High Speed Endpoint */ +#define USB_HS_EP1_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP1_NUM) +#define USB_HS_EP1_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_HS_EP1_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 +#define USB_HS_EP1_INTERVAL 0x00 + +#define USB_HS_EP2_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP2_NUM) +#define USB_HS_EP2_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_HS_EP2_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 +#define USB_HS_EP2_INTERVAL 0x00 + +#define USB_HS_EP3_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP3_NUM) +#define USB_HS_EP3_ATTRIBUTE bUSB_EP_TYPE_INTERRUPT +#define USB_HS_EP3_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_HS_EP3_INTERVAL 0x01 + +#define USB_HS_EP4_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP4_NUM) +#define USB_HS_EP4_ATTRIBUTE bUSB_EP_TYPE_INTERRUPT //bUSB_EP_TYPE_BULK +#define USB_HS_EP4_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_HS_EP4_INTERVAL 0x01 //0x00 + +#define USB_HS_EP5_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP5_NUM) +#define USB_HS_EP5_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_HS_EP5_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 +#define USB_HS_EP5_INTERVAL 0x00 + +#define USB_HS_EP6_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP6_NUM) +#define USB_HS_EP6_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_HS_EP6_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 +#define USB_HS_EP6_INTERVAL 0x00 + +/* Full Speed Endpoint */ +#define USB_FS_EP1_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP1_NUM) +#define USB_FS_EP1_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP1_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP1_INTERVAL 0x00 + +#define USB_FS_EP2_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP2_NUM) +#define USB_FS_EP2_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP2_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP2_INTERVAL 0x00 + +#define USB_FS_EP3_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP3_NUM) +#define USB_FS_EP3_ATTRIBUTE bUSB_EP_TYPE_INTERRUPT +#define USB_FS_EP3_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP3_INTERVAL 0x01 + +#define USB_FS_EP4_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP4_NUM) +#define USB_FS_EP4_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP4_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP4_INTERVAL 0x00 + +#define USB_FS_EP5_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP5_NUM) +#define USB_FS_EP5_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP5_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP5_INTERVAL 0x00 + +#define USB_FS_EP6_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP6_NUM) +#define USB_FS_EP6_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP6_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP6_INTERVAL 0x00 + +//#define USB_QUALIFIER_DESC_ADDR 0x8cff00 +//#define USB_OTHER_SPEED_DESC_ADDR 0x8cffA + +#endif // end of _USB_TABLE_H_ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/usb_type.h b/target_firmware/magpie_fw_dev/target/inc/magpie/usb_type.h new file mode 100755 index 0000000..c1bee0e --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/usb_type.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef USB_TYPE_H +#define USB_TYPE_H + +#include "dt_defs.h" + +/*********************** for Faraday USB controller *******************/ +typedef enum +{ + CMD_VOID, // No command + CMD_GET_DESCRIPTOR, // Get_Descriptor command + CMD_SET_DESCRIPTOR // Set_Descriptor command +} CommandType; + +typedef enum +{ + ACT_IDLE, + ACT_DONE, + ACT_STALL +} Action; + +typedef struct Setup_Packet +{ + uint8_t Direction; /* Data transfer direction: IN, OUT */ + uint8_t Type; /* Request Type: Standard, Class, Vendor */ + uint8_t Object; /* Recipient: Device, Interface, Endpoint,other */ + uint16_t Request; /* Refer to Table 9-3 */ + uint16_t Value; + uint16_t Index; + uint16_t Length; +} SetupPacket; + +#define mBIT(b) (1 << (b)) +#define mMASK(w) (mBIT(w) - 1) + +#define mWORD_IDX(bsize) ((bsize) >> 1) +#define mWORD_SIZE(bsize) (((bsize) + 1) >> 1) + +#define mTABLE_WID mWORD_SIZE +#define mTABLE_IDX mWORD_IDX +#define mTABLE_LEN mLOW_BYTE + +#define mLOW_MASK(u16) ((uint8_t) ((u16) & mMASK(8))) +#define mHIGH_MASK(u16) ((uint8_t) ((u16) & ~mMASK(8))) +#define mLOW2HIGH(u16) (((uint8_t) (u16)) << 8) + +/* (1234) -> 0034 */ +//#define mLOW_BYTE(u16) ((U_8)(u16)) +#define mLOW_BYTE(u16) mLOW_MASK(u16) +/* (1234) -> 0012 */ +#define mHIGH_BYTE(u16) ((uint8_t) (((uint16_t) (u16)) >> 8)) + +#define mGET_REG1(var0, reg0) { var0 = reg0; } + +/* (1234, 5678) -> 7834 */ +#define m2BYTE(ch1L, ch2H) (mLOW_MASK(ch1L) | mLOW2HIGH(ch2H)) + +#define mREAD_WORD(var0, reg0, reg1) \ + { var0 = reg0; var0 += mLOW2HIGH(reg1); } + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/usbfifo_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/usbfifo_api.h new file mode 100755 index 0000000..9ec5398 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/usbfifo_api.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * @File: HIF_api.h + * + * @Abstract: Host Interface api + * + * @Notes: + */ + +#ifndef _USB_FIFO_API_H +#define _USB_FIFO_API_H + +#include "vbuf_api.h" + +typedef struct _USB_FIFO_CONFIG { + /* callback to get the buf for receiving commands from USB FIFO */ + VBUF* (*get_command_buf)(void); + /* callback when receiving a command */ + void (*recv_command)(VBUF *cmd); + /* callback to get the buf for event to send to the host */ + VBUF* (*get_event_buf)(void); + /* callback to indicate the event has been sent to the host */ + void (*send_event_done)(VBUF *buf); + + /* context used for all callbacks */ + //void *context; +} USB_FIFO_CONFIG; + +/* hardware API table structure (API descriptions below) */ +struct usbfifo_api { + void (*_init)(USB_FIFO_CONFIG *pConfig); + void (*_enable_event_isr)(void); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void usbfifo_module_install(struct usbfifo_api *apis); + +#endif /* #ifndef _USB_FIFO_API_H */ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/vbuf_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/vbuf_api.h new file mode 100755 index 0000000..efbdf9c --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/vbuf_api.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * @File: VBUF_api.h + * + * @Abstract: Host Interface api + * + * @Notes: + */ + +#ifndef _VBUF_API_H +#define _VBUF_API_H + +#include + +#define MAX_BUF_CTX_LEN 20 + +typedef struct _VBUF +{ + VDESC *desc_list; + struct _VBUF *next_buf; + A_UINT16 buf_length; + A_UINT8 reserved[2]; + A_UINT8 ctx[MAX_BUF_CTX_LEN]; + //A_UINT8 end_point; + //A_UINT8 reserved[1]; +} VBUF; + +#define VBUF_GET_DATA_ADDR(vbuf) (vbuf->desc_list->buf_addr + vbuf->desc_list->data_offset) + +/* hardware API table structure (API descriptions below) */ +struct vbuf_api { + void (*_init)(int nBuf); + VBUF* (*_alloc_vbuf)(void); + VBUF* (*_alloc_vbuf_with_size)(int size, int reserve); + void (*_free_vbuf)(VBUF *buf); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void vbuf_module_install(struct vbuf_api *apis); + +#endif /* #ifndef _HIF_API_H */ diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/vdesc_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/vdesc_api.h new file mode 100755 index 0000000..631f134 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/vdesc_api.h @@ -0,0 +1,46 @@ +/* + * @File: VBUF_api.h + * + * @Abstract: Host Interface api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _VDESC_API_H +#define _VDESC_API_H + +//#define VDESC_CONTROL_BUF_HDR (1 << 6) /* the buffer was manipulated and a header added */ + +#define MAX_HW_DESC_SIZE 20 + +typedef struct _VDESC +{ + struct _VDESC *next_desc; + A_UINT8 *buf_addr; + A_UINT16 buf_size; + A_UINT16 data_offset; + A_UINT16 data_size; + A_UINT16 control; + A_UINT8 hw_desc_buf[MAX_HW_DESC_SIZE]; +} VDESC; + +//#define VDESC_HW_TO_VDESC(hwdesc) ((VDESC *)(((A_UINT32 *)hwdesc - 4))) +#define VDESC_HW_TO_VDESC(hwdesc) ((VDESC *)(((A_UINT32 *)hwdesc - 4))) + +struct vdesc_api { + void (*_init)(int nDesc); + VDESC* (*_alloc_vdesc)(); + A_UINT8* (*_get_hw_desc)(VDESC *desc); + void (*_swap_vdesc)(VDESC *dest, VDESC *src); + //void (*_free_vdesc)(void); + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void vdesc_module_install(struct vdesc_api *apis); + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/magpie/wdt_api.h b/target_firmware/magpie_fw_dev/target/inc/magpie/wdt_api.h new file mode 100755 index 0000000..a7476f4 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/magpie/wdt_api.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __WDT_API_H__ +#define __WDT_API_H__ +/* + * + */ + +typedef enum { + WDT_ACTION_NO = 0, // bit1, bit0: 00 + WDT_ACTION_INTR, // bit1, bit0: 01 + WDT_ACTION_NMI, // bit1, bit0: 10 + WDT_ACTION_RESET, // bit1, bit0: 11 + + WDT_ACTION_UNKNOWN +}T_WDT_ACTION_TYPE; + + +typedef enum { + WDT_TIMEOUT = 1, + WDT_ACTION, + + WDT_UNKNOWN +}T_WDT_CMD_TYPE; + +typedef struct { + uint32_t cmd; + union { + uint32_t timeout; + uint32_t action; + }; +}T_WDT_CMD; + + +typedef enum{ + ENUM_WDT_BOOT = 1, + ENUM_COLD_BOOT, + ENUM_SUSP_BOOT, + + // add above here + ENUM_UNKNOWN_BOOT +}T_BOOT_TYPE; + + +/*!- interface of watchdog timer + * + */ +struct wdt_api { + void (* _wdt_init)(void); + void (* _wdt_enable)(void); + void (* _wdt_disable)(void); + void (* _wdt_set)(T_WDT_CMD); + void (* _wdt_task)(void); + void (* _wdt_reset)(void); + T_BOOT_TYPE (*_wdt_last_boot)(void); +}; +#endif /* __WDT_API_H__ */ + diff --git a/target_firmware/magpie_fw_dev/target/inc/xtensa-elf/xtensa/config/core.h b/target_firmware/magpie_fw_dev/target/inc/xtensa-elf/xtensa/config/core.h new file mode 100644 index 0000000..01bcfdd --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/xtensa-elf/xtensa/config/core.h @@ -0,0 +1,1222 @@ +/* + * xtensa/config/core.h -- HAL definitions dependent on CORE configuration + * + * This header file is sometimes referred to as the "compile-time HAL" or CHAL. + * It pulls definitions tailored for a specific Xtensa processor configuration. + * + * Sources for binaries meant to be configuration-independent generally avoid + * including this file (they may use the configuration-specific HAL library). + * It is normal for the HAL library source itself to include this file. + */ + +/* + * Copyright (c) 2005-2007 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + + +#ifndef XTENSA_CONFIG_CORE_H +#define XTENSA_CONFIG_CORE_H + +/* CONFIGURATION INDEPENDENT DEFINITIONS: */ +#ifdef __XTENSA__ +#include +#else +#include "../hal.h" +#endif + +/* CONFIGURATION SPECIFIC DEFINITIONS: */ +#ifdef __XTENSA__ +#include +#include +#include +#else +#include "core-isa.h" +#include "core-matmap.h" +#include "tie.h" +#endif + +#if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__) +#ifdef __XTENSA__ +#include +#else +#include "tie-asm.h" +#endif +#endif /*_ASMLANGUAGE or __ASSEMBLER__*/ + + +/*---------------------------------------------------------------------- + GENERAL + ----------------------------------------------------------------------*/ + +/* + * Separators for macros that expand into arrays. + * These can be predefined by files that #include this one, + * when different separators are required. + */ +/* Element separator for macros that expand into 1-dimensional arrays: */ +#ifndef XCHAL_SEP +#define XCHAL_SEP , +#endif +/* Array separator for macros that expand into 2-dimensional arrays: */ +#ifndef XCHAL_SEP2 +#define XCHAL_SEP2 },{ +#endif + + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#if XCHAL_HAVE_BE +# define XCHAL_HAVE_LE 0 +# define XCHAL_MEMORY_ORDER XTHAL_BIGENDIAN +#else +# define XCHAL_HAVE_LE 1 +# define XCHAL_MEMORY_ORDER XTHAL_LITTLEENDIAN +#endif + + + +/*---------------------------------------------------------------------- + INTERRUPTS + ----------------------------------------------------------------------*/ + +/* Indexing macros: */ +#define _XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK +#define XCHAL_INTLEVEL_MASK(n) _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */ +#define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK +#define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */ +#define _XCHAL_INTLEVEL_NUM(n) XCHAL_INTLEVEL ## n ## _NUM +#define XCHAL_INTLEVEL_NUM(n) _XCHAL_INTLEVEL_NUM(n) /* n = 0 .. 15 */ +#define _XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL +#define XCHAL_INT_LEVEL(n) _XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */ +#define _XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE +#define XCHAL_INT_TYPE(n) _XCHAL_INT_TYPE(n) /* n = 0 .. 31 */ +#define _XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT +#define XCHAL_TIMER_INTERRUPT(n) _XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */ + + +#define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS +#define XCHAL_NUM_LOWPRI_LEVELS 1 /* number of low-priority interrupt levels (always 1) */ +#define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) /* level of first high-priority interrupt (always 2) */ +/* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */ + +/* These values are constant for existing Xtensa processor implementations: */ +#define XCHAL_INTLEVEL0_MASK 0x00000000 +#define XCHAL_INTLEVEL8_MASK 0x00000000 +#define XCHAL_INTLEVEL9_MASK 0x00000000 +#define XCHAL_INTLEVEL10_MASK 0x00000000 +#define XCHAL_INTLEVEL11_MASK 0x00000000 +#define XCHAL_INTLEVEL12_MASK 0x00000000 +#define XCHAL_INTLEVEL13_MASK 0x00000000 +#define XCHAL_INTLEVEL14_MASK 0x00000000 +#define XCHAL_INTLEVEL15_MASK 0x00000000 + +/* Array of masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL_MASKS XCHAL_INTLEVEL0_MASK \ + XCHAL_SEP XCHAL_INTLEVEL1_MASK \ + XCHAL_SEP XCHAL_INTLEVEL2_MASK \ + XCHAL_SEP XCHAL_INTLEVEL3_MASK \ + XCHAL_SEP XCHAL_INTLEVEL4_MASK \ + XCHAL_SEP XCHAL_INTLEVEL5_MASK \ + XCHAL_SEP XCHAL_INTLEVEL6_MASK \ + XCHAL_SEP XCHAL_INTLEVEL7_MASK \ + XCHAL_SEP XCHAL_INTLEVEL8_MASK \ + XCHAL_SEP XCHAL_INTLEVEL9_MASK \ + XCHAL_SEP XCHAL_INTLEVEL10_MASK \ + XCHAL_SEP XCHAL_INTLEVEL11_MASK \ + XCHAL_SEP XCHAL_INTLEVEL12_MASK \ + XCHAL_SEP XCHAL_INTLEVEL13_MASK \ + XCHAL_SEP XCHAL_INTLEVEL14_MASK \ + XCHAL_SEP XCHAL_INTLEVEL15_MASK + +/* These values are constant for existing Xtensa processor implementations: */ +#define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000 +#define XCHAL_INTLEVEL8_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL9_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL10_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL11_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL12_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL13_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL14_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL15_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK + +/* Mask of all low-priority interrupts: */ +#define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK + +/* Mask of all interrupts masked by PS.EXCM (or CEXCM): */ +#define XCHAL_EXCM_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(XCHAL_EXCM_LEVEL) + +/* Array of masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL_ANDBELOW_MASKS XCHAL_INTLEVEL0_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL1_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL2_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL3_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL4_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL5_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL6_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL7_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL8_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL9_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL10_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL11_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL12_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL13_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL14_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL15_ANDBELOW_MASK + +#if 0 /*XCHAL_HAVE_NMI*/ +/* NMI "interrupt level" (for use with EXCSAVE_n, EPS_n, EPC_n, RFI n): */ +# define XCHAL_NMILEVEL (XCHAL_NUM_INTLEVELS+1) +#endif + +/* Array of levels of each possible interrupt: */ +#define XCHAL_INT_LEVELS XCHAL_INT0_LEVEL \ + XCHAL_SEP XCHAL_INT1_LEVEL \ + XCHAL_SEP XCHAL_INT2_LEVEL \ + XCHAL_SEP XCHAL_INT3_LEVEL \ + XCHAL_SEP XCHAL_INT4_LEVEL \ + XCHAL_SEP XCHAL_INT5_LEVEL \ + XCHAL_SEP XCHAL_INT6_LEVEL \ + XCHAL_SEP XCHAL_INT7_LEVEL \ + XCHAL_SEP XCHAL_INT8_LEVEL \ + XCHAL_SEP XCHAL_INT9_LEVEL \ + XCHAL_SEP XCHAL_INT10_LEVEL \ + XCHAL_SEP XCHAL_INT11_LEVEL \ + XCHAL_SEP XCHAL_INT12_LEVEL \ + XCHAL_SEP XCHAL_INT13_LEVEL \ + XCHAL_SEP XCHAL_INT14_LEVEL \ + XCHAL_SEP XCHAL_INT15_LEVEL \ + XCHAL_SEP XCHAL_INT16_LEVEL \ + XCHAL_SEP XCHAL_INT17_LEVEL \ + XCHAL_SEP XCHAL_INT18_LEVEL \ + XCHAL_SEP XCHAL_INT19_LEVEL \ + XCHAL_SEP XCHAL_INT20_LEVEL \ + XCHAL_SEP XCHAL_INT21_LEVEL \ + XCHAL_SEP XCHAL_INT22_LEVEL \ + XCHAL_SEP XCHAL_INT23_LEVEL \ + XCHAL_SEP XCHAL_INT24_LEVEL \ + XCHAL_SEP XCHAL_INT25_LEVEL \ + XCHAL_SEP XCHAL_INT26_LEVEL \ + XCHAL_SEP XCHAL_INT27_LEVEL \ + XCHAL_SEP XCHAL_INT28_LEVEL \ + XCHAL_SEP XCHAL_INT29_LEVEL \ + XCHAL_SEP XCHAL_INT30_LEVEL \ + XCHAL_SEP XCHAL_INT31_LEVEL + +/* Array of types of each possible interrupt: */ +#define XCHAL_INT_TYPES XCHAL_INT0_TYPE \ + XCHAL_SEP XCHAL_INT1_TYPE \ + XCHAL_SEP XCHAL_INT2_TYPE \ + XCHAL_SEP XCHAL_INT3_TYPE \ + XCHAL_SEP XCHAL_INT4_TYPE \ + XCHAL_SEP XCHAL_INT5_TYPE \ + XCHAL_SEP XCHAL_INT6_TYPE \ + XCHAL_SEP XCHAL_INT7_TYPE \ + XCHAL_SEP XCHAL_INT8_TYPE \ + XCHAL_SEP XCHAL_INT9_TYPE \ + XCHAL_SEP XCHAL_INT10_TYPE \ + XCHAL_SEP XCHAL_INT11_TYPE \ + XCHAL_SEP XCHAL_INT12_TYPE \ + XCHAL_SEP XCHAL_INT13_TYPE \ + XCHAL_SEP XCHAL_INT14_TYPE \ + XCHAL_SEP XCHAL_INT15_TYPE \ + XCHAL_SEP XCHAL_INT16_TYPE \ + XCHAL_SEP XCHAL_INT17_TYPE \ + XCHAL_SEP XCHAL_INT18_TYPE \ + XCHAL_SEP XCHAL_INT19_TYPE \ + XCHAL_SEP XCHAL_INT20_TYPE \ + XCHAL_SEP XCHAL_INT21_TYPE \ + XCHAL_SEP XCHAL_INT22_TYPE \ + XCHAL_SEP XCHAL_INT23_TYPE \ + XCHAL_SEP XCHAL_INT24_TYPE \ + XCHAL_SEP XCHAL_INT25_TYPE \ + XCHAL_SEP XCHAL_INT26_TYPE \ + XCHAL_SEP XCHAL_INT27_TYPE \ + XCHAL_SEP XCHAL_INT28_TYPE \ + XCHAL_SEP XCHAL_INT29_TYPE \ + XCHAL_SEP XCHAL_INT30_TYPE \ + XCHAL_SEP XCHAL_INT31_TYPE + +/* Array of masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASKS XCHAL_INTTYPE_MASK_UNCONFIGURED \ + XCHAL_SEP XCHAL_INTTYPE_MASK_SOFTWARE \ + XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_EDGE \ + XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_LEVEL \ + XCHAL_SEP XCHAL_INTTYPE_MASK_TIMER \ + XCHAL_SEP XCHAL_INTTYPE_MASK_NMI \ + XCHAL_SEP XCHAL_INTTYPE_MASK_WRITE_ERROR + +/* Interrupts that can be cleared using the INTCLEAR special register: */ +#define XCHAL_INTCLEARABLE_MASK (XCHAL_INTTYPE_MASK_SOFTWARE+XCHAL_INTTYPE_MASK_EXTERN_EDGE+XCHAL_INTTYPE_MASK_WRITE_ERROR) +/* Interrupts that can be triggered using the INTSET special register: */ +#define XCHAL_INTSETTABLE_MASK XCHAL_INTTYPE_MASK_SOFTWARE + +/* Array of interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3): */ +#define XCHAL_TIMER_INTERRUPTS XCHAL_TIMER0_INTERRUPT \ + XCHAL_SEP XCHAL_TIMER1_INTERRUPT \ + XCHAL_SEP XCHAL_TIMER2_INTERRUPT \ + XCHAL_SEP XCHAL_TIMER3_INTERRUPT + + + +/* For backward compatibility and for the array macros, define macros for + * each unconfigured interrupt number (unfortunately, the value of + * XTHAL_INTTYPE_UNCONFIGURED is not zero): */ +#if XCHAL_NUM_INTERRUPTS == 0 +# define XCHAL_INT0_LEVEL 0 +# define XCHAL_INT0_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 1 +# define XCHAL_INT1_LEVEL 0 +# define XCHAL_INT1_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 2 +# define XCHAL_INT2_LEVEL 0 +# define XCHAL_INT2_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 3 +# define XCHAL_INT3_LEVEL 0 +# define XCHAL_INT3_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 4 +# define XCHAL_INT4_LEVEL 0 +# define XCHAL_INT4_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 5 +# define XCHAL_INT5_LEVEL 0 +# define XCHAL_INT5_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 6 +# define XCHAL_INT6_LEVEL 0 +# define XCHAL_INT6_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 7 +# define XCHAL_INT7_LEVEL 0 +# define XCHAL_INT7_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 8 +# define XCHAL_INT8_LEVEL 0 +# define XCHAL_INT8_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 9 +# define XCHAL_INT9_LEVEL 0 +# define XCHAL_INT9_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 10 +# define XCHAL_INT10_LEVEL 0 +# define XCHAL_INT10_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 11 +# define XCHAL_INT11_LEVEL 0 +# define XCHAL_INT11_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 12 +# define XCHAL_INT12_LEVEL 0 +# define XCHAL_INT12_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 13 +# define XCHAL_INT13_LEVEL 0 +# define XCHAL_INT13_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 14 +# define XCHAL_INT14_LEVEL 0 +# define XCHAL_INT14_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 15 +# define XCHAL_INT15_LEVEL 0 +# define XCHAL_INT15_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 16 +# define XCHAL_INT16_LEVEL 0 +# define XCHAL_INT16_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 17 +# define XCHAL_INT17_LEVEL 0 +# define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 18 +# define XCHAL_INT18_LEVEL 0 +# define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 19 +# define XCHAL_INT19_LEVEL 0 +# define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 20 +# define XCHAL_INT20_LEVEL 0 +# define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 21 +# define XCHAL_INT21_LEVEL 0 +# define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 22 +# define XCHAL_INT22_LEVEL 0 +# define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 23 +# define XCHAL_INT23_LEVEL 0 +# define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 24 +# define XCHAL_INT24_LEVEL 0 +# define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 25 +# define XCHAL_INT25_LEVEL 0 +# define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 26 +# define XCHAL_INT26_LEVEL 0 +# define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 27 +# define XCHAL_INT27_LEVEL 0 +# define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 28 +# define XCHAL_INT28_LEVEL 0 +# define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 29 +# define XCHAL_INT29_LEVEL 0 +# define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 30 +# define XCHAL_INT30_LEVEL 0 +# define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 31 +# define XCHAL_INT31_LEVEL 0 +# define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif + + +/* + * Masks and levels corresponding to each *external* interrupt. + */ + +#define XCHAL_EXTINT0_MASK (1 << XCHAL_EXTINT0_NUM) +#define XCHAL_EXTINT0_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT0_NUM) +#define XCHAL_EXTINT1_MASK (1 << XCHAL_EXTINT1_NUM) +#define XCHAL_EXTINT1_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT1_NUM) +#define XCHAL_EXTINT2_MASK (1 << XCHAL_EXTINT2_NUM) +#define XCHAL_EXTINT2_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT2_NUM) +#define XCHAL_EXTINT3_MASK (1 << XCHAL_EXTINT3_NUM) +#define XCHAL_EXTINT3_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT3_NUM) +#define XCHAL_EXTINT4_MASK (1 << XCHAL_EXTINT4_NUM) +#define XCHAL_EXTINT4_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT4_NUM) +#define XCHAL_EXTINT5_MASK (1 << XCHAL_EXTINT5_NUM) +#define XCHAL_EXTINT5_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT5_NUM) +#define XCHAL_EXTINT6_MASK (1 << XCHAL_EXTINT6_NUM) +#define XCHAL_EXTINT6_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT6_NUM) +#define XCHAL_EXTINT7_MASK (1 << XCHAL_EXTINT7_NUM) +#define XCHAL_EXTINT7_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT7_NUM) +#define XCHAL_EXTINT8_MASK (1 << XCHAL_EXTINT8_NUM) +#define XCHAL_EXTINT8_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT8_NUM) +#define XCHAL_EXTINT9_MASK (1 << XCHAL_EXTINT9_NUM) +#define XCHAL_EXTINT9_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT9_NUM) +#define XCHAL_EXTINT10_MASK (1 << XCHAL_EXTINT10_NUM) +#define XCHAL_EXTINT10_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT10_NUM) +#define XCHAL_EXTINT11_MASK (1 << XCHAL_EXTINT11_NUM) +#define XCHAL_EXTINT11_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT11_NUM) +#define XCHAL_EXTINT12_MASK (1 << XCHAL_EXTINT12_NUM) +#define XCHAL_EXTINT12_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT12_NUM) +#define XCHAL_EXTINT13_MASK (1 << XCHAL_EXTINT13_NUM) +#define XCHAL_EXTINT13_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT13_NUM) +#define XCHAL_EXTINT14_MASK (1 << XCHAL_EXTINT14_NUM) +#define XCHAL_EXTINT14_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT14_NUM) +#define XCHAL_EXTINT15_MASK (1 << XCHAL_EXTINT15_NUM) +#define XCHAL_EXTINT15_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT15_NUM) +#define XCHAL_EXTINT16_MASK (1 << XCHAL_EXTINT16_NUM) +#define XCHAL_EXTINT16_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT16_NUM) +#define XCHAL_EXTINT17_MASK (1 << XCHAL_EXTINT17_NUM) +#define XCHAL_EXTINT17_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT17_NUM) +#define XCHAL_EXTINT18_MASK (1 << XCHAL_EXTINT18_NUM) +#define XCHAL_EXTINT18_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT18_NUM) +#define XCHAL_EXTINT19_MASK (1 << XCHAL_EXTINT19_NUM) +#define XCHAL_EXTINT19_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT19_NUM) +#define XCHAL_EXTINT20_MASK (1 << XCHAL_EXTINT20_NUM) +#define XCHAL_EXTINT20_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT20_NUM) +#define XCHAL_EXTINT21_MASK (1 << XCHAL_EXTINT21_NUM) +#define XCHAL_EXTINT21_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT21_NUM) +#define XCHAL_EXTINT22_MASK (1 << XCHAL_EXTINT22_NUM) +#define XCHAL_EXTINT22_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT22_NUM) +#define XCHAL_EXTINT23_MASK (1 << XCHAL_EXTINT23_NUM) +#define XCHAL_EXTINT23_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT23_NUM) +#define XCHAL_EXTINT24_MASK (1 << XCHAL_EXTINT24_NUM) +#define XCHAL_EXTINT24_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT24_NUM) +#define XCHAL_EXTINT25_MASK (1 << XCHAL_EXTINT25_NUM) +#define XCHAL_EXTINT25_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT25_NUM) +#define XCHAL_EXTINT26_MASK (1 << XCHAL_EXTINT26_NUM) +#define XCHAL_EXTINT26_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT26_NUM) +#define XCHAL_EXTINT27_MASK (1 << XCHAL_EXTINT27_NUM) +#define XCHAL_EXTINT27_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT27_NUM) +#define XCHAL_EXTINT28_MASK (1 << XCHAL_EXTINT28_NUM) +#define XCHAL_EXTINT28_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT28_NUM) +#define XCHAL_EXTINT29_MASK (1 << XCHAL_EXTINT29_NUM) +#define XCHAL_EXTINT29_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT29_NUM) +#define XCHAL_EXTINT30_MASK (1 << XCHAL_EXTINT30_NUM) +#define XCHAL_EXTINT30_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT30_NUM) +#define XCHAL_EXTINT31_MASK (1 << XCHAL_EXTINT31_NUM) +#define XCHAL_EXTINT31_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT31_NUM) + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +/* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */ +#define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */ +#define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */ +#ifdef XCHAL_USER_VECTOR_VADDR +#define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR +#define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR +#endif +#ifdef XCHAL_USER_VECTOR_PADDR +# define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR +# define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR +#endif +#ifdef XCHAL_KERNEL_VECTOR_VADDR +# define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR +# define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR +#endif +#ifdef XCHAL_KERNEL_VECTOR_PADDR +# define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR +# define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR +#endif + +#if 0 +#if XCHAL_HAVE_DEBUG +# define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL) +/* This one should only get defined if the corresponding intlevel paddr macro exists: */ +# define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL_VECTOR_PADDR(XCHAL_DEBUGLEVEL) +#endif +#endif + +/* Indexing macros: */ +#define _XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR +#define XCHAL_INTLEVEL_VECTOR_VADDR(n) _XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */ + +/* + * General Exception Causes + * (values of EXCCAUSE special register set by general exceptions, + * which vector to the user, kernel, or double-exception vectors). + * + * DEPRECATED. Please use the equivalent EXCCAUSE_xxx macros + * defined in . (Note that these have slightly + * different names, they don't just have the XCHAL_ prefix removed.) + */ +#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction */ +#define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call */ +#define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error */ +#define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */ +#define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */ +#define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist */ +#define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */ +#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation */ +#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */ +#define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store */ +/*10..15 reserved*/ +#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception */ +#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception */ +#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception */ +#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception */ +#define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception */ +/*21..23 reserved*/ +#define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception */ +#define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception */ +#define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception */ +#define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception */ +#define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception */ +#define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception */ +/*30..31 reserved*/ +#define XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED 32 /* Coprocessor 0 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED 33 /* Coprocessor 1 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED 34 /* Coprocessor 2 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED 35 /* Coprocessor 3 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED 36 /* Coprocessor 4 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED 37 /* Coprocessor 5 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED 38 /* Coprocessor 6 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED 39 /* Coprocessor 7 disabled */ +#define XCHAL_EXCCAUSE_FLOATING_POINT 40 /* Floating Point Exception */ +/*40..63 reserved*/ + + +/* + * Miscellaneous special register fields. + * + * For each special register, and each field within each register: + * XCHAL__VALIDMASK is the set of bits defined in the register. + * XCHAL___BITS is the number of bits in the field. + * XCHAL___NUM is 2^bits, the number of possible values + * of the field. + * XCHAL___SHIFT is the position of the field within + * the register, starting from the least significant bit. + * + * DEPRECATED. Please use the equivalent macros defined in + * . (Note that these have different names.) + */ + +/* DBREAKC (special register number 160): */ +#define XCHAL_DBREAKC_VALIDMASK 0xC000003F +#define XCHAL_DBREAKC_MASK_BITS 6 +#define XCHAL_DBREAKC_MASK_NUM 64 +#define XCHAL_DBREAKC_MASK_SHIFT 0 +#define XCHAL_DBREAKC_MASK_MASK 0x0000003F +#define XCHAL_DBREAKC_LOADBREAK_BITS 1 +#define XCHAL_DBREAKC_LOADBREAK_NUM 2 +#define XCHAL_DBREAKC_LOADBREAK_SHIFT 30 +#define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000 +#define XCHAL_DBREAKC_STOREBREAK_BITS 1 +#define XCHAL_DBREAKC_STOREBREAK_NUM 2 +#define XCHAL_DBREAKC_STOREBREAK_SHIFT 31 +#define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000 +/* PS (special register number 230): */ +#define XCHAL_PS_VALIDMASK 0x00070F3F +#define XCHAL_PS_INTLEVEL_BITS 4 +#define XCHAL_PS_INTLEVEL_NUM 16 +#define XCHAL_PS_INTLEVEL_SHIFT 0 +#define XCHAL_PS_INTLEVEL_MASK 0x0000000F +#define XCHAL_PS_EXCM_BITS 1 +#define XCHAL_PS_EXCM_NUM 2 +#define XCHAL_PS_EXCM_SHIFT 4 +#define XCHAL_PS_EXCM_MASK 0x00000010 +#define XCHAL_PS_UM_BITS 1 +#define XCHAL_PS_UM_NUM 2 +#define XCHAL_PS_UM_SHIFT 5 +#define XCHAL_PS_UM_MASK 0x00000020 +#define XCHAL_PS_RING_BITS 2 +#define XCHAL_PS_RING_NUM 4 +#define XCHAL_PS_RING_SHIFT 6 +#define XCHAL_PS_RING_MASK 0x000000C0 +#define XCHAL_PS_OWB_BITS 4 +#define XCHAL_PS_OWB_NUM 16 +#define XCHAL_PS_OWB_SHIFT 8 +#define XCHAL_PS_OWB_MASK 0x00000F00 +#define XCHAL_PS_CALLINC_BITS 2 +#define XCHAL_PS_CALLINC_NUM 4 +#define XCHAL_PS_CALLINC_SHIFT 16 +#define XCHAL_PS_CALLINC_MASK 0x00030000 +#define XCHAL_PS_WOE_BITS 1 +#define XCHAL_PS_WOE_NUM 2 +#define XCHAL_PS_WOE_SHIFT 18 +#define XCHAL_PS_WOE_MASK 0x00040000 +/* EXCCAUSE (special register number 232): */ +#define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F +#define XCHAL_EXCCAUSE_BITS 6 +#define XCHAL_EXCCAUSE_NUM 64 +#define XCHAL_EXCCAUSE_SHIFT 0 +#define XCHAL_EXCCAUSE_MASK 0x0000003F +/* DEBUGCAUSE (special register number 233): */ +#define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F +#define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1 +#define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2 +#define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0 +#define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001 +#define XCHAL_DEBUGCAUSE_IBREAK_BITS 1 +#define XCHAL_DEBUGCAUSE_IBREAK_NUM 2 +#define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1 +#define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002 +#define XCHAL_DEBUGCAUSE_DBREAK_BITS 1 +#define XCHAL_DEBUGCAUSE_DBREAK_NUM 2 +#define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2 +#define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004 +#define XCHAL_DEBUGCAUSE_BREAK_BITS 1 +#define XCHAL_DEBUGCAUSE_BREAK_NUM 2 +#define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3 +#define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008 +#define XCHAL_DEBUGCAUSE_BREAKN_BITS 1 +#define XCHAL_DEBUGCAUSE_BREAKN_NUM 2 +#define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4 +#define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010 +#define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1 +#define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2 +#define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5 +#define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020 + + + + +/*---------------------------------------------------------------------- + TIMERS + ----------------------------------------------------------------------*/ + +/*#define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT*/ + + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */ +#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */ +#define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */ +#define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */ + +#define XCHAL_IROM0_VADDR XCHAL_INSTROM0_VADDR /* (DEPRECATED) */ +#define XCHAL_IROM0_PADDR XCHAL_INSTROM0_PADDR /* (DEPRECATED) */ +#define XCHAL_IROM0_SIZE XCHAL_INSTROM0_SIZE /* (DEPRECATED) */ +#define XCHAL_IROM1_VADDR XCHAL_INSTROM1_VADDR /* (DEPRECATED) */ +#define XCHAL_IROM1_PADDR XCHAL_INSTROM1_PADDR /* (DEPRECATED) */ +#define XCHAL_IROM1_SIZE XCHAL_INSTROM1_SIZE /* (DEPRECATED) */ +#define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */ +#define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */ +#define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */ +#define XCHAL_IRAM1_VADDR XCHAL_INSTRAM1_VADDR /* (DEPRECATED) */ +#define XCHAL_IRAM1_PADDR XCHAL_INSTRAM1_PADDR /* (DEPRECATED) */ +#define XCHAL_IRAM1_SIZE XCHAL_INSTRAM1_SIZE /* (DEPRECATED) */ +#define XCHAL_DROM0_VADDR XCHAL_DATAROM0_VADDR /* (DEPRECATED) */ +#define XCHAL_DROM0_PADDR XCHAL_DATAROM0_PADDR /* (DEPRECATED) */ +#define XCHAL_DROM0_SIZE XCHAL_DATAROM0_SIZE /* (DEPRECATED) */ +#define XCHAL_DROM1_VADDR XCHAL_DATAROM1_VADDR /* (DEPRECATED) */ +#define XCHAL_DROM1_PADDR XCHAL_DATAROM1_PADDR /* (DEPRECATED) */ +#define XCHAL_DROM1_SIZE XCHAL_DATAROM1_SIZE /* (DEPRECATED) */ +#define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */ +#define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */ +#define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */ +#define XCHAL_DRAM1_VADDR XCHAL_DATARAM1_VADDR /* (DEPRECATED) */ +#define XCHAL_DRAM1_PADDR XCHAL_DATARAM1_PADDR /* (DEPRECATED) */ +#define XCHAL_DRAM1_SIZE XCHAL_DATARAM1_SIZE /* (DEPRECATED) */ + + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + + +/* Max for both I-cache and D-cache (used for general alignment): */ +#if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE +# define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_ICACHE_LINEWIDTH +# define XCHAL_CACHE_LINESIZE_MAX XCHAL_ICACHE_LINESIZE +#else +# define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_DCACHE_LINEWIDTH +# define XCHAL_CACHE_LINESIZE_MAX XCHAL_DCACHE_LINESIZE +#endif + +#define XCHAL_ICACHE_SETSIZE (1< XCHAL_DCACHE_SETWIDTH +# define XCHAL_CACHE_SETWIDTH_MAX XCHAL_ICACHE_SETWIDTH +# define XCHAL_CACHE_SETSIZE_MAX XCHAL_ICACHE_SETSIZE +#else +# define XCHAL_CACHE_SETWIDTH_MAX XCHAL_DCACHE_SETWIDTH +# define XCHAL_CACHE_SETSIZE_MAX XCHAL_DCACHE_SETSIZE +#endif + +/* Instruction cache tag bits: */ +#define XCHAL_ICACHE_TAG_V_SHIFT 0 +#define XCHAL_ICACHE_TAG_V 0x1 /* valid bit */ +#if XCHAL_ICACHE_WAYS > 1 +# define XCHAL_ICACHE_TAG_F_SHIFT 1 +# define XCHAL_ICACHE_TAG_F 0x2 /* fill (LRU) bit */ +#else +# define XCHAL_ICACHE_TAG_F_SHIFT 0 +# define XCHAL_ICACHE_TAG_F 0 /* no fill (LRU) bit */ +#endif +#if XCHAL_ICACHE_LINE_LOCKABLE +# define XCHAL_ICACHE_TAG_L_SHIFT (XCHAL_ICACHE_TAG_F_SHIFT+1) +# define XCHAL_ICACHE_TAG_L (1 << XCHAL_ICACHE_TAG_L_SHIFT) /* lock bit */ +#else +# define XCHAL_ICACHE_TAG_L_SHIFT XCHAL_ICACHE_TAG_F_SHIFT +# define XCHAL_ICACHE_TAG_L 0 /* no lock bit */ +#endif +/* Data cache tag bits: */ +#define XCHAL_DCACHE_TAG_V_SHIFT 0 +#define XCHAL_DCACHE_TAG_V 0x1 /* valid bit */ +#if XCHAL_DCACHE_WAYS > 1 +# define XCHAL_DCACHE_TAG_F_SHIFT 1 +# define XCHAL_DCACHE_TAG_F 0x2 /* fill (LRU) bit */ +#else +# define XCHAL_DCACHE_TAG_F_SHIFT 0 +# define XCHAL_DCACHE_TAG_F 0 /* no fill (LRU) bit */ +#endif +#if XCHAL_DCACHE_IS_WRITEBACK +# define XCHAL_DCACHE_TAG_D_SHIFT (XCHAL_DCACHE_TAG_F_SHIFT+1) +# define XCHAL_DCACHE_TAG_D (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* dirty bit */ +#else +# define XCHAL_DCACHE_TAG_D_SHIFT XCHAL_DCACHE_TAG_F_SHIFT +# define XCHAL_DCACHE_TAG_D 0 /* no dirty bit */ +#endif +#if XCHAL_DCACHE_LINE_LOCKABLE +# define XCHAL_DCACHE_TAG_L_SHIFT (XCHAL_DCACHE_TAG_D_SHIFT+1) +# define XCHAL_DCACHE_TAG_L (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* lock bit */ +#else +# define XCHAL_DCACHE_TAG_L_SHIFT XCHAL_DCACHE_TAG_D_SHIFT +# define XCHAL_DCACHE_TAG_L 0 /* no lock bit */ +#endif + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See for more details. */ + +#define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS /* (DEPRECATED; use XCHAL_HAVE_TLBS instead; will be removed in future release) */ + +/* Indexing macros: */ +#define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what +#define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what ) +#define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what +#define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what ) +#define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what +#define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what ) +#define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what +#define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what ) +/* + * Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES) + * to get the value of XCHAL_ITLB_SET_ENTRIES where is the first auto-refill set. + */ + +/* Number of entries per autorefill way: */ +#define XCHAL_ITLB_ARF_ENTRIES (1< 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2 +# define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */ +#else +# define XCHAL_HAVE_PTP_MMU 0 /* don't have full MMU */ +#endif +#endif + +/* + * For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings: + */ +#if XCHAL_HAVE_PTP_MMU +#define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */ +#define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */ +#define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */ +#define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel RAM bypass (uncached) static map */ +#define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of kseg_bypass */ +#define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of kseg_bypass (assumed power of 2!!!) */ + +#define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel I/O cached static map */ +#define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of kio_cached */ +#define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached (assumed power of 2!!!) */ +#define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel I/O bypass (uncached) static map */ +#define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of kio_bypass */ +#define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass (assumed power of 2!!!) */ + +#define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */ +#define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */ +/* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */ +#endif + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +/* Data alignment required if used for instructions: */ +#if XCHAL_INST_FETCH_WIDTH > XCHAL_DATA_WIDTH +# define XCHAL_ALIGN_MAX XCHAL_INST_FETCH_WIDTH +#else +# define XCHAL_ALIGN_MAX XCHAL_DATA_WIDTH +#endif + +/* + * Names kept for backward compatibility. + * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases + * under which they are released. In the T10##.# era there was no distinction.) + */ +#define XCHAL_HW_RELEASE_MAJOR XCHAL_HW_VERSION_MAJOR +#define XCHAL_HW_RELEASE_MINOR XCHAL_HW_VERSION_MINOR +#define XCHAL_HW_RELEASE_NAME XCHAL_HW_VERSION_NAME + + + + +/*---------------------------------------------------------------------- + COPROCESSORS and EXTRA STATE + ----------------------------------------------------------------------*/ + +#define XCHAL_EXTRA_SA_SIZE XCHAL_NCP_SA_SIZE +#define XCHAL_EXTRA_SA_ALIGN XCHAL_NCP_SA_ALIGN +#define XCHAL_CPEXTRA_SA_SIZE XCHAL_TOTAL_SA_SIZE +#define XCHAL_CPEXTRA_SA_ALIGN XCHAL_TOTAL_SA_ALIGN + +#if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__) + +#define xchal_extratie_load xchal_ncptie_load +#define xchal_extratie_store xchal_ncptie_store +#define xchal_extratie_load_a2 xchal_ncptie_load_a2 +#define xchal_extratie_store_a2 xchal_ncptie_store_a2 +#define xchal_extra_load xchal_ncp_load +#define xchal_extra_store xchal_ncp_store +#define xchal_extra_load_a2 xchal_ncp_load_a2 +#define xchal_extra_store_a2 xchal_ncp_store_a2 +#define xchal_extra_load_funcbody xchal_ncp_load_a2 +#define xchal_extra_store_funcbody xchal_ncp_store_a2 + +/* Empty placeholder macros for undefined coprocessors: */ +# ifndef XCHAL_CP0_NAME +# define xchal_cp0_store_a2 xchal_cp0_store a2, a3 +# define xchal_cp0_load_a2 xchal_cp0_load a2, a3 + .macro xchal_cp0_store ptr tmp + .endm + .macro xchal_cp0_load ptr tmp + .endm +# endif +# ifndef XCHAL_CP1_NAME +# define xchal_cp1_store_a2 xchal_cp1_store a2, a3 +# define xchal_cp1_load_a2 xchal_cp1_load a2, a3 + .macro xchal_cp1_store ptr tmp + .endm + .macro xchal_cp1_load ptr tmp + .endm +# endif +# ifndef XCHAL_CP2_NAME +# define xchal_cp2_store_a2 xchal_cp2_store a2, a3 +# define xchal_cp2_load_a2 xchal_cp2_load a2, a3 + .macro xchal_cp2_store ptr tmp + .endm + .macro xchal_cp2_load ptr tmp + .endm +# endif +# ifndef XCHAL_CP3_NAME +# define xchal_cp3_store_a2 xchal_cp3_store a2, a3 +# define xchal_cp3_load_a2 xchal_cp3_load a2, a3 + .macro xchal_cp3_store ptr tmp + .endm + .macro xchal_cp3_load ptr tmp + .endm +# endif +# ifndef XCHAL_CP4_NAME +# define xchal_cp4_store_a2 xchal_cp4_store a2, a3 +# define xchal_cp4_load_a2 xchal_cp4_load a2, a3 + .macro xchal_cp4_store ptr tmp + .endm + .macro xchal_cp4_load ptr tmp + .endm +# endif +# ifndef XCHAL_CP5_NAME +# define xchal_cp5_store_a2 xchal_cp5_store a2, a3 +# define xchal_cp5_load_a2 xchal_cp5_load a2, a3 + .macro xchal_cp5_store ptr tmp + .endm + .macro xchal_cp5_load ptr tmp + .endm +# endif +# ifndef XCHAL_CP6_NAME +# define xchal_cp6_store_a2 xchal_cp6_store a2, a3 +# define xchal_cp6_load_a2 xchal_cp6_load a2, a3 + .macro xchal_cp6_store ptr tmp + .endm + .macro xchal_cp6_load ptr tmp + .endm +# endif +# ifndef XCHAL_CP7_NAME +# define xchal_cp7_store_a2 xchal_cp7_store a2, a3 +# define xchal_cp7_load_a2 xchal_cp7_load a2, a3 + .macro xchal_cp7_store ptr tmp + .endm + .macro xchal_cp7_load ptr tmp + .endm +# endif + + /******************** + * Macros to create functions that save and restore the state of *any* TIE + * coprocessor (by dynamic index). + */ + + /* + * Macro that expands to the body of a function + * that stores the selected coprocessor's state (registers etc). + * Entry: a2 = ptr to save area in which to save cp state + * a3 = coprocessor number + * Exit: any register a2-a15 (?) may have been clobbered. + */ + .macro xchal_cpi_store_funcbody +# ifdef XCHAL_CP0_NAME + bnez a3, 99f + xchal_cp0_store_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP1_NAME + bnei a3, 1, 99f + xchal_cp1_store_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP2_NAME + bnei a3, 2, 99f + xchal_cp2_store_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP3_NAME + bnei a3, 3, 99f + xchal_cp3_store_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP4_NAME + bnei a3, 4, 99f + xchal_cp4_store_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP5_NAME + bnei a3, 5, 99f + xchal_cp5_store_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP6_NAME + bnei a3, 6, 99f + xchal_cp6_store_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP7_NAME + bnei a3, 7, 99f + xchal_cp7_store_a2 + j 90f +99: +# endif +90: + .endm + + /* + * Macro that expands to the body of a function + * that loads the selected coprocessor's state (registers etc). + * Entry: a2 = ptr to save area from which to restore cp state + * a3 = coprocessor number + * Exit: any register a2-a15 (?) may have been clobbered. + */ + .macro xchal_cpi_load_funcbody +# ifdef XCHAL_CP0_NAME + bnez a3, 99f + xchal_cp0_load_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP1_NAME + bnei a3, 1, 99f + xchal_cp1_load_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP2_NAME + bnei a3, 2, 99f + xchal_cp2_load_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP3_NAME + bnei a3, 3, 99f + xchal_cp3_load_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP4_NAME + bnei a3, 4, 99f + xchal_cp4_load_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP5_NAME + bnei a3, 5, 99f + xchal_cp5_load_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP6_NAME + bnei a3, 6, 99f + xchal_cp6_load_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP7_NAME + bnei a3, 7, 99f + xchal_cp7_load_a2 + j 90f +99: +# endif +90: + .endm + +#endif /*_ASMLANGUAGE or __ASSEMBLER__*/ + + +/* Other default macros for undefined coprocessors: */ +#ifndef XCHAL_CP0_NAME +# define XCHAL_CP0_SA_SIZE 0 +# define XCHAL_CP0_SA_ALIGN 1 +# define XCHAL_CP0_NAME 0 +# define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP1_NAME +# define XCHAL_CP1_SA_SIZE 0 +# define XCHAL_CP1_SA_ALIGN 1 +# define XCHAL_CP1_NAME 0 +# define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP2_NAME +# define XCHAL_CP2_SA_SIZE 0 +# define XCHAL_CP2_SA_ALIGN 1 +# define XCHAL_CP2_NAME 0 +# define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP3_NAME +# define XCHAL_CP3_SA_SIZE 0 +# define XCHAL_CP3_SA_ALIGN 1 +# define XCHAL_CP3_NAME 0 +# define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP4_NAME +# define XCHAL_CP4_SA_SIZE 0 +# define XCHAL_CP4_SA_ALIGN 1 +# define XCHAL_CP4_NAME 0 +# define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP5_NAME +# define XCHAL_CP5_SA_SIZE 0 +# define XCHAL_CP5_SA_ALIGN 1 +# define XCHAL_CP5_NAME 0 +# define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP6_NAME +# define XCHAL_CP6_SA_SIZE 0 +# define XCHAL_CP6_SA_ALIGN 1 +# define XCHAL_CP6_NAME 0 +# define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP7_NAME +# define XCHAL_CP7_SA_SIZE 0 +# define XCHAL_CP7_SA_ALIGN 1 +# define XCHAL_CP7_NAME 0 +# define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */ +#endif + +/* Indexing macros: */ +#define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE +#define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */ +#define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN +#define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */ + +#define XCHAL_CPEXTRA_SA_SIZE_TOR2 XCHAL_CPEXTRA_SA_SIZE /* Tor2Beta only - do not use */ + +/* Link-time HAL global variables that report coprocessor numbers by name + (names are case-preserved from the original TIE): */ +#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) +# define _XCJOIN(a,b) a ## b +# define XCJOIN(a,b) _XCJOIN(a,b) +# ifdef XCHAL_CP0_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP0_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP0_IDENT); +# endif +# ifdef XCHAL_CP1_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP1_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP1_IDENT); +# endif +# ifdef XCHAL_CP2_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP2_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP2_IDENT); +# endif +# ifdef XCHAL_CP3_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP3_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP3_IDENT); +# endif +# ifdef XCHAL_CP4_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP4_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP4_IDENT); +# endif +# ifdef XCHAL_CP5_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP5_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP5_IDENT); +# endif +# ifdef XCHAL_CP6_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP6_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP6_IDENT); +# endif +# ifdef XCHAL_CP7_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP7_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT); +# endif +#endif + + + + +/*---------------------------------------------------------------------- + DERIVED + ----------------------------------------------------------------------*/ + +#if XCHAL_HAVE_BE +#define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */ +#define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */ +#define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */ +#else +#define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */ +#define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */ +#define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */ +#endif +/* Belongs in xtensa/hal.h: */ +#define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */ + + +/* + * Because information as to exactly which hardware version is targeted + * by a given software build is not always available, compile-time HAL + * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE): + * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases + * under which they are released. In the T10##.# era there was no distinction.) + */ +#if XCHAL_HW_CONFIGID_RELIABLE +# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) +# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) +# define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) +# define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0) +#else +# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \ + : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \ + : XTHAL_MAYBE ) +# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \ + : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \ + : XTHAL_MAYBE ) +# define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \ + ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE) +# define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0) +#endif + +/* + * Specific errata: + */ + +/* + * Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1; + * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled): + */ +#define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN (XCHAL_HAVE_XEA1 && \ + (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \ + || XCHAL_HW_RELEASE_AT(1050,0))) + + + +#endif /*XTENSA_CONFIG_CORE_H*/ diff --git a/target_firmware/magpie_fw_dev/target/inc/xtensa-elf/xtensa/corebits.h b/target_firmware/magpie_fw_dev/target/inc/xtensa-elf/xtensa/corebits.h new file mode 100644 index 0000000..9fbb994 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/xtensa-elf/xtensa/corebits.h @@ -0,0 +1,149 @@ +/* + * xtensa/corebits.h - Xtensa Special Register field positions, masks, values. + * + * (In previous releases, these were defined in specreg.h, a generated file. + * This file is not generated, ie. it is processor configuration independent.) + */ + +/* $Id: //depot/rel/BadgerPass/Xtensa/OS/include/xtensa/corebits.h#3 $ */ + +/* + * Copyright (c) 2005-2007 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +#ifndef XTENSA_COREBITS_H +#define XTENSA_COREBITS_H + +/* EXCCAUSE register fields: */ +#define EXCCAUSE_EXCCAUSE_SHIFT 0 +#define EXCCAUSE_EXCCAUSE_MASK 0x3F +/* EXCCAUSE register values: */ +/* + * General Exception Causes + * (values of EXCCAUSE special register set by general exceptions, + * which vector to the user, kernel, or double-exception vectors). + */ +#define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */ +#define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */ +#define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */ +# define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */ +#define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */ +# define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */ +#define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */ +# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */ +#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */ +#define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */ +#define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */ +#define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */ +#define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */ +/* Reserved 10..11 */ +#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */ +#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */ +#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */ +#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */ +#define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */ +#define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */ +#define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */ +/* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */ +#define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */ +/* Reserved 21..23 */ +#define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */ +#define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */ +#define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */ +/* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */ +#define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */ +#define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */ +/* Reserved 30..31 */ +#define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */ +#define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */ +#define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */ +#define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */ +#define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */ +#define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */ +#define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */ +#define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */ +#define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */ +/*#define EXCCAUSE_FLOATING_POINT 40*/ /* Floating Point Exception (not implemented) */ +/* Reserved 40..63 */ + +/* PS register fields: */ +#define PS_WOE_SHIFT 18 +#define PS_WOE_MASK 0x00040000 +#define PS_WOE PS_WOE_MASK +#define PS_CALLINC_SHIFT 16 +#define PS_CALLINC_MASK 0x00030000 +#define PS_CALLINC(n) (((n)&3)<4) 0 2 or >3 (TBD) + * T1030.0 0 1 (HAL beta) + * T1030.{1,2} 0 3 Equivalent to first release. + * T1030.n (n>=3) 0 >= 3 (TBD) + * T1040.n 1040 n Full CHAL available from T1040.2 + * T1050.n 1050 n . + * 6.0.n 6000 n Xtensa Tools v6 (RA-200x.n) + * 7.0.n 7000 n Xtensa Tools v7 (RB-200x.n) + * 7.1.n 7010 n Xtensa Tools v7.1 (RB-200x.(n+2)) + * + * + * Note: there is a distinction between the software version with + * which something is compiled (accessible using XTHAL_RELEASE_* macros) + * and the software version with which the HAL library was compiled + * (accessible using Xthal_release_* global variables). This + * distinction is particularly relevant for vendors that distribute + * configuration-independent binaries (eg. an OS), where their customer + * might link it with a HAL of a different Xtensa software version. + * In this case, it may be appropriate for the OS to verify at run-time + * whether XTHAL_RELEASE_* and Xthal_release_* are compatible. + * [Guidelines as to which version is compatible with which are not + * currently provided explicitly, but might be inferred from reading + * OSKit documentation for all releases -- compatibility is also highly + * dependent on which HAL features are used. Each version is usually + * backward compatible, with very few exceptions if any.] + * + * Notes: + * Tornado 2.0 supported in T1020.3+, T1030.1+, and T1040.{0,1} only. + * Tornado 2.0.2 supported in T1040.2+, T1050, and 6.0. + * Compile-time HAL port of NucleusPlus supported by T1040.2 and later. + */ + +/* Version comparison operators (among major/minor pairs): */ +#define XTHAL_REL_GE(maja,mina, majb,minb) ((maja) > (majb) || \ + ((maja) == (majb) && (mina) >= (minb))) +#define XTHAL_REL_GT(maja,mina, majb,minb) ((maja) > (majb) || \ + ((maja) == (majb) && (mina) > (minb))) +#define XTHAL_REL_LE(maja,mina, majb,minb) ((maja) < (majb) || \ + ((maja) == (majb) && (mina) <= (minb))) +#define XTHAL_REL_LT(maja,mina, majb,minb) ((maja) < (majb) || \ + ((maja) == (majb) && (mina) < (minb))) +#define XTHAL_REL_EQ(maja,mina, majb,minb) ((maja) == (majb) && (mina) == (minb)) + +/* Fuzzy (3-way) logic operators: */ +#define XTHAL_MAYBE -1 /* 0=NO, 1=YES, -1=MAYBE */ +#define XTHAL_FUZZY_AND(a,b) (((a)==0 || (b)==0) ? 0 : ((a)==1 && (b)==1) ? 1 : XTHAL_MAYBE) +#define XTHAL_FUZZY_OR(a,b) (((a)==1 || (b)==1) ? 1 : ((a)==0 && (b)==0) ? 0 : XTHAL_MAYBE) +#define XTHAL_FUZZY_NOT(a) (((a)==0 || (a)==1) ? (1-(a)) : XTHAL_MAYBE) + + +/* + * Architectural limit, independent of configuration: + */ +#define XTHAL_MAX_CPS 8 /* max number of coprocessors (0..7) */ + +/* Misc: */ +#define XTHAL_LITTLEENDIAN 0 +#define XTHAL_BIGENDIAN 1 + + + +#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------- + HAL + ----------------------------------------------------------------------*/ + +/* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */ +extern const unsigned int Xthal_rev_no; + + +/*---------------------------------------------------------------------- + Optional/Custom Processor State + ----------------------------------------------------------------------*/ + +/* save & restore the extra processor state */ +extern void xthal_save_extra(void *base); +extern void xthal_restore_extra(void *base); + +extern void xthal_save_cpregs(void *base, int); +extern void xthal_restore_cpregs(void *base, int); +/* versions specific to each coprocessor id */ +extern void xthal_save_cp0(void *base); +extern void xthal_save_cp1(void *base); +extern void xthal_save_cp2(void *base); +extern void xthal_save_cp3(void *base); +extern void xthal_save_cp4(void *base); +extern void xthal_save_cp5(void *base); +extern void xthal_save_cp6(void *base); +extern void xthal_save_cp7(void *base); +extern void xthal_restore_cp0(void *base); +extern void xthal_restore_cp1(void *base); +extern void xthal_restore_cp2(void *base); +extern void xthal_restore_cp3(void *base); +extern void xthal_restore_cp4(void *base); +extern void xthal_restore_cp5(void *base); +extern void xthal_restore_cp6(void *base); +extern void xthal_restore_cp7(void *base); +/* pointers to each of the functions above */ +extern void* Xthal_cpregs_save_fn[XTHAL_MAX_CPS]; +extern void* Xthal_cpregs_restore_fn[XTHAL_MAX_CPS]; +/* similarly for non-windowed ABI (may be same or different) */ +extern void* Xthal_cpregs_save_nw_fn[XTHAL_MAX_CPS]; +extern void* Xthal_cpregs_restore_nw_fn[XTHAL_MAX_CPS]; + +/*extern void xthal_save_all_extra(void *base);*/ +/*extern void xthal_restore_all_extra(void *base);*/ + +/* space for processor state */ +extern const unsigned int Xthal_extra_size; +extern const unsigned int Xthal_extra_align; +extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS]; +extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS]; +extern const unsigned int Xthal_all_extra_size; +extern const unsigned int Xthal_all_extra_align; +/* coprocessor names */ +extern const char * const Xthal_cp_names[XTHAL_MAX_CPS]; + +/* initialize the extra processor */ +/*extern void xthal_init_extra(void);*/ +/* initialize the TIE coprocessor */ +/*extern void xthal_init_cp(int);*/ + +/* initialize the extra processor */ +extern void xthal_init_mem_extra(void *); +/* initialize the TIE coprocessor */ +extern void xthal_init_mem_cp(void *, int); + +/* the number of TIE coprocessors contiguous from zero (for Tor2) */ +extern const unsigned int Xthal_num_coprocessors; + +/* actual number of coprocessors */ +extern const unsigned char Xthal_cp_num; +/* index of highest numbered coprocessor, plus one */ +extern const unsigned char Xthal_cp_max; +/* index of highest allowed coprocessor number, per cfg, plus one */ +/*extern const unsigned char Xthal_cp_maxcfg;*/ +/* bitmask of which coprocessors are present */ +extern const unsigned int Xthal_cp_mask; + +/* read & write extra state register */ +/*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*/ +/*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*/ + +/* read & write a TIE coprocessor register */ +/*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*/ +/*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*/ + +/* return coprocessor number based on register */ +/*extern int xthal_which_cp(unsigned reg);*/ + + +/*---------------------------------------------------------------------- + Register Windows + ----------------------------------------------------------------------*/ + +/* number of registers in register window */ +extern const unsigned int Xthal_num_aregs; +extern const unsigned char Xthal_num_aregs_log2; + + +/*---------------------------------------------------------------------- + Cache + ----------------------------------------------------------------------*/ + +/* size of the cache lines in log2(bytes) */ +extern const unsigned char Xthal_icache_linewidth; +extern const unsigned char Xthal_dcache_linewidth; +/* size of the cache lines in bytes (2^linewidth) */ +extern const unsigned short Xthal_icache_linesize; +extern const unsigned short Xthal_dcache_linesize; + +/* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */ +extern const unsigned int Xthal_icache_size; +extern const unsigned int Xthal_dcache_size; +/* cache features */ +extern const unsigned char Xthal_dcache_is_writeback; + +/* invalidate the caches */ +extern void xthal_icache_region_invalidate( void *addr, unsigned size ); +extern void xthal_dcache_region_invalidate( void *addr, unsigned size ); +extern void xthal_icache_line_invalidate(void *addr); +extern void xthal_dcache_line_invalidate(void *addr); +/* write dirty data back */ +extern void xthal_dcache_region_writeback( void *addr, unsigned size ); +extern void xthal_dcache_line_writeback(void *addr); +/* write dirty data back and invalidate */ +extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size ); +extern void xthal_dcache_line_writeback_inv(void *addr); + +/* sync icache and memory */ +extern void xthal_icache_sync( void ); +/* sync dcache and memory */ +extern void xthal_dcache_sync( void ); + + +/*---------------------------------------------------------------------- + Debug + ----------------------------------------------------------------------*/ + +/* 1 if debug option configured, 0 if not: */ +extern const int Xthal_debug_configured; + +/* Set (plant) and remove software breakpoint, both synchronizing cache: */ +extern unsigned int xthal_set_soft_break(void *addr); +extern void xthal_remove_soft_break(void *addr, unsigned int); + + +/*---------------------------------------------------------------------- + Disassembler + ----------------------------------------------------------------------*/ + +/* Max expected size of the return buffer for a disassembled instruction (hint only): */ +#define XTHAL_DISASM_BUFSIZE 80 + +/* Disassembly option bits for selecting what to return: */ +#define XTHAL_DISASM_OPT_ADDR 0x0001 /* display address */ +#define XTHAL_DISASM_OPT_OPHEX 0x0002 /* display opcode bytes in hex */ +#define XTHAL_DISASM_OPT_OPCODE 0x0004 /* display opcode name (mnemonic) */ +#define XTHAL_DISASM_OPT_PARMS 0x0008 /* display parameters */ +#define XTHAL_DISASM_OPT_ALL 0x0FFF /* display everything */ + +/* routine to get a string for the disassembled instruction */ +extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr, + char *buffer, unsigned buflen, unsigned options ); + +/* routine to get the size of the next instruction. Returns 0 for + illegal instruction */ +extern int xthal_disassemble_size( unsigned char *instr_buf ); + + +/*---------------------------------------------------------------------- + Instruction/Data RAM/ROM Access + ----------------------------------------------------------------------*/ + +extern void* xthal_memcpy(void *dst, const void *src, unsigned len); +extern void* xthal_bcopy(const void *src, void *dst, unsigned len); + + +/*---------------------------------------------------------------------- + MP Synchronization + ----------------------------------------------------------------------*/ + +extern int xthal_compare_and_set( int *addr, int test_val, int compare_val ); + +/*extern const char Xthal_have_s32c1i;*/ + + +/*---------------------------------------------------------------------- + Miscellaneous + ----------------------------------------------------------------------*/ + +extern const unsigned int Xthal_release_major; +extern const unsigned int Xthal_release_minor; +extern const char * const Xthal_release_name; +extern const char * const Xthal_release_internal; + +extern const unsigned char Xthal_memory_order; +extern const unsigned char Xthal_have_windowed; +extern const unsigned char Xthal_have_density; +extern const unsigned char Xthal_have_booleans; +extern const unsigned char Xthal_have_loops; +extern const unsigned char Xthal_have_nsa; +extern const unsigned char Xthal_have_minmax; +extern const unsigned char Xthal_have_sext; +extern const unsigned char Xthal_have_clamps; +extern const unsigned char Xthal_have_mac16; +extern const unsigned char Xthal_have_mul16; +extern const unsigned char Xthal_have_fp; +extern const unsigned char Xthal_have_speculation; +extern const unsigned char Xthal_have_threadptr; + +extern const unsigned char Xthal_have_pif; +extern const unsigned short Xthal_num_writebuffer_entries; + +extern const unsigned int Xthal_build_unique_id; +/* Version info for hardware targeted by software upgrades: */ +extern const unsigned int Xthal_hw_configid0; +extern const unsigned int Xthal_hw_configid1; +extern const unsigned int Xthal_hw_release_major; +extern const unsigned int Xthal_hw_release_minor; +extern const char * const Xthal_hw_release_name; +extern const char * const Xthal_hw_release_internal; + +#ifdef __cplusplus +} +#endif +#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */ + + + + + +/**************************************************************************** + Definitions Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + Constant Definitions (shared with assembly) + ----------------------------------------------------------------------*/ + +/* + * Architectural limits, independent of configuration. + * Note that these are ISA-defined limits, not micro-architecture implementation + * limits enforced by the Xtensa Processor Generator (which may be stricter than + * these below). + */ +#define XTHAL_MAX_INTERRUPTS 32 /* max number of interrupts (0..31) */ +#define XTHAL_MAX_INTLEVELS 16 /* max number of interrupt levels (0..15) */ + /* (as of T1040, implementation limit is 7: 0..6) */ +#define XTHAL_MAX_TIMERS 4 /* max number of timers (CCOMPARE0..CCOMPARE3) */ + /* (as of T1040, implementation limit is 3: 0..2) */ + +/* Interrupt types: */ +#define XTHAL_INTTYPE_UNCONFIGURED 0 +#define XTHAL_INTTYPE_SOFTWARE 1 +#define XTHAL_INTTYPE_EXTERN_EDGE 2 +#define XTHAL_INTTYPE_EXTERN_LEVEL 3 +#define XTHAL_INTTYPE_TIMER 4 +#define XTHAL_INTTYPE_NMI 5 +#define XTHAL_INTTYPE_WRITE_ERROR 6 +#define XTHAL_MAX_INTTYPES 7 /* number of interrupt types */ + +/* Timer related: */ +#define XTHAL_TIMER_UNCONFIGURED -1 /* Xthal_timer_interrupt[] value for non-existent timers */ +#define XTHAL_TIMER_UNASSIGNED XTHAL_TIMER_UNCONFIGURED /* (for backwards compatibility only) */ + +/* Local Memory ECC/Parity: */ +#define XTHAL_MEMEP_PARITY 1 +#define XTHAL_MEMEP_ECC 2 +/* Flags parameter to xthal_memep_inject_error(): */ +#define XTHAL_MEMEP_F_LOCAL 0 /* local memory (default) */ +#define XTHAL_MEMEP_F_DCACHE_DATA 4 /* data cache data */ +#define XTHAL_MEMEP_F_DCACHE_TAG 5 /* data cache tag */ +#define XTHAL_MEMEP_F_ICACHE_DATA 6 /* instruction cache data */ +#define XTHAL_MEMEP_F_ICACHE_TAG 7 /* instruction cache tag */ +#define XTHAL_MEMEP_F_CORRECTABLE 16 /* inject correctable error + (default is non-corr.) */ + + +/* Access Mode bits (tentative): */ /* bit abbr unit short_name PPC equ - Description */ +#define XTHAL_AMB_EXCEPTION 0 /* 001 E EX fls: EXception none + exception on any access (aka "illegal") */ +#define XTHAL_AMB_HITCACHE 1 /* 002 C CH fls: use Cache on Hit ~(I CI) + [or H HC] way from tag match; + [or U UC] (ISA: same except Isolate case) */ +#define XTHAL_AMB_ALLOCATE 2 /* 004 A AL fl?: ALlocate none + [or F FI fill] refill cache on miss, way from LRU + (ISA: Read/Write Miss Refill) */ +#define XTHAL_AMB_WRITETHRU 3 /* 008 W WT --s: WriteThrough W WT + store immediately to memory (ISA: same) */ +#define XTHAL_AMB_ISOLATE 4 /* 010 I IS fls: ISolate none + use cache regardless of hit-vs-miss, + way from vaddr (ISA: use-cache-on-miss+hit) */ +#define XTHAL_AMB_GUARD 5 /* 020 G GU ?l?: GUard G * + non-speculative; spec/replay refs not permitted */ +#if 0 +#define XTHAL_AMB_COHERENT 6 /* 040 M MC ?ls: Mem/MP Coherent M + on read, other CPU/bus-master may need to supply data; + on write, maybe redirect to or flush other CPU dirty line; etc */ +#define XTHAL_AMB_ORDERED x /* 000 O OR fls: ORdered G * + mem accesses cannot be out of order */ +#define XTHAL_AMB_FUSEWRITES x /* 000 F FW --s: FuseWrites none + allow combining/merging multiple writes + (to same datapath data unit) into one + (implied by writeback) */ +#define XTHAL_AMB_TRUSTED x /* 000 T TR ?l?: TRusted none + memory will not bus error (if it does, + handle as fatal imprecise interrupt) */ +#define XTHAL_AMB_PREFETCH x /* 000 P PR fl?: PRefetch none + on refill, read line+1 into prefetch buffers */ +#define XTHAL_AMB_STREAM x /* 000 S ST ???: STreaming none + access one of N stream buffers */ +#endif /*0*/ + +#define XTHAL_AM_EXCEPTION (1< = bit is set + * '-' = bit is clear + * '.' = bit is irrelevant / don't care, as follows: + * E=1 makes all others irrelevant + * W,F relevant only for stores + * "2345" + * Indicates which Xtensa releases support the corresponding + * access mode. Releases for each character column are: + * 2 = prior to T1020.2: T1015 (V1.5), T1020.0, T1020.1 + * 3 = T1020.2 and later: T1020.2+, T1030 + * 4 = T1040 + * 5 = T1050 (maybe), LX1, LX2, LX2.1 + * 7 = LX2.2 + * And the character column contents are: + * = support by release(s) + * "." = unsupported by release(s) + * "?" = support unknown + */ + /* FOMGIWACE 23457 */ +/* For instruction fetch: */ +#define XTHAL_FAM_EXCEPTION 0x001 /* ........E 23457 exception */ +#define XTHAL_FAM_ISOLATE 0x012 /* .---I.-C- ..... isolate */ +#define XTHAL_FAM_BYPASS 0x000 /* .----.--- 23457 bypass */ +#define XTHAL_FAM_NACACHED 0x002 /* .----.-C- ..... cached no-allocate (frozen) */ +#define XTHAL_FAM_CACHED 0x006 /* .----.AC- 23457 cached */ +/* For data load: */ +#define XTHAL_LAM_EXCEPTION 0x001 /* ........E 23457 exception */ +#define XTHAL_LAM_ISOLATE 0x012 /* .---I.-C- 23457 isolate */ +#define XTHAL_LAM_BYPASS 0x000 /* .O---.--- 2.... bypass speculative */ +#define XTHAL_LAM_BYPASSG 0x020 /* .O-G-.--- .3457 bypass guarded */ +#define XTHAL_LAM_NACACHED 0x002 /* .O---.-C- 2.... cached no-allocate speculative */ +#define XTHAL_LAM_NACACHEDG 0x022 /* .O-G-.-C- .3457 cached no-allocate guarded */ +#define XTHAL_LAM_CACHED 0x006 /* .----.AC- 23457 cached speculative */ +#define XTHAL_LAM_CACHEDG 0x026 /* .?-G-.AC- ..... cached guarded */ +#define XTHAL_LAM_CACHEDM 0x046 /* .-M--.AC- ....7 cached MP-coherent (experimental) */ +/* For data store: */ +#define XTHAL_SAM_EXCEPTION 0x001 /* ........E 23457 exception */ +#define XTHAL_SAM_ISOLATE 0x032 /* .--GI--C- 23457 isolate */ +#define XTHAL_SAM_BYPASS 0x028 /* -O-G-W--- 23457 bypass */ +/*efine XTHAL_SAM_BYPASSF 0x028*/ /* F--G-W--- ..... bypass write-combined */ +#define XTHAL_SAM_WRITETHRU 0x02A /* -O-G-W-C- 23457 writethrough */ +/*efine XTHAL_SAM_WRITETHRUF 0x02A*/ /* F--G-W-C- ..... writethrough write-combined */ +#define XTHAL_SAM_WRITEALLOC 0x02E /* -O-G-WAC- ..... writethrough-allocate */ +/*efine XTHAL_SAM_WRITEALLOCF 0x02E*/ /* F--G-WAC- ..... writethrough-allocate write-combined */ +#define XTHAL_SAM_WRITEBACK 0x066 /* F-MG--AC- ...57 writeback (MP-coherent if configured) */ + +#if 0 +/* + Cache attribute encoding for CACHEATTR (per ISA): + (Note: if this differs from ISA Ref Manual, ISA has precedence) + + Inst-fetches Loads Stores + ------------- ------------ ------------- +0x0 FCA_EXCEPTION ?LCA_NACACHED_G* SCA_WRITETHRU "uncached" (cached no-allocate) +0x1 FCA_CACHED LCA_CACHED SCA_WRITETHRU cached +0x2 FCA_BYPASS LCA_BYPASS_G* SCA_BYPASS bypass +0x3 FCA_CACHED LCA_CACHED SCA_WRITEALLOCF write-allocate + or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented) +0x4 FCA_CACHED LCA_CACHED SCA_WRITEBACK write-back + or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented) +0x5..D FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION (reserved) +0xE FCA_EXCEPTION LCA_ISOLATE SCA_ISOLATE isolate +0xF FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION illegal + * Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G) +*/ +#endif /*0*/ + + +#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) +#ifdef __cplusplus +extern "C" { +#endif + + +/*---------------------------------------------------------------------- + Register Windows + ----------------------------------------------------------------------*/ + +/* This spill any live register windows (other than the caller's): + * (NOTE: current implementation require privileged code, but + * a user-callable implementation is possible.) */ +extern void xthal_window_spill( void ); + + +/*---------------------------------------------------------------------- + Optional/Custom Processor State + ----------------------------------------------------------------------*/ + +/* validate & invalidate the TIE register file */ +extern void xthal_validate_cp(int); +extern void xthal_invalidate_cp(int); + +/* read and write cpenable register */ +extern void xthal_set_cpenable(unsigned); +extern unsigned xthal_get_cpenable(void); + + +/*---------------------------------------------------------------------- + Interrupts + ----------------------------------------------------------------------*/ + +/* the number of interrupt levels */ +extern const unsigned char Xthal_num_intlevels; +/* the number of interrupts */ +extern const unsigned char Xthal_num_interrupts; + +/* mask for level of interrupts */ +extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS]; +/* mask for level 0 to N interrupts */ +extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS]; + +/* level of each interrupt */ +extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS]; + +/* type per interrupt */ +extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS]; + +/* masks of each type of interrupt */ +extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES]; + +/* interrupt numbers assigned to each timer interrupt */ +extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS]; + +/* INTENABLE,INTERRUPT,INTSET,INTCLEAR register access functions: */ +extern unsigned xthal_get_intenable( void ); +extern void xthal_set_intenable( unsigned ); +extern unsigned xthal_get_interrupt( void ); +#define xthal_get_intread xthal_get_interrupt /* backward compatibility */ +extern void xthal_set_intset( unsigned ); +extern void xthal_set_intclear( unsigned ); + + +/*---------------------------------------------------------------------- + Debug + ----------------------------------------------------------------------*/ + +/* Number of instruction and data break registers: */ +extern const int Xthal_num_ibreak; +extern const int Xthal_num_dbreak; + + +/*---------------------------------------------------------------------- + Core Counter + ----------------------------------------------------------------------*/ + +/* counter info */ +extern const unsigned char Xthal_have_ccount; /* set if CCOUNT register present */ +extern const unsigned char Xthal_num_ccompare; /* number of CCOMPAREn registers */ + +/* get CCOUNT register (if not present return 0) */ +extern unsigned xthal_get_ccount(void); + +/* set and get CCOMPAREn registers (if not present, get returns 0) */ +extern void xthal_set_ccompare(int, unsigned); +extern unsigned xthal_get_ccompare(int); + + +/*---------------------------------------------------------------------- + Miscellaneous + ----------------------------------------------------------------------*/ + +extern const unsigned char Xthal_have_prid; +extern const unsigned char Xthal_have_exceptions; +extern const unsigned char Xthal_xea_version; +extern const unsigned char Xthal_have_interrupts; +extern const unsigned char Xthal_have_highlevel_interrupts; +extern const unsigned char Xthal_have_nmi; + +extern unsigned xthal_get_prid( void ); + + +/*---------------------------------------------------------------------- + Virtual interrupt prioritization (DEPRECATED) + ----------------------------------------------------------------------*/ + +/* Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities: */ +extern unsigned xthal_vpri_to_intlevel(unsigned vpri); +extern unsigned xthal_intlevel_to_vpri(unsigned intlevel); + +/* Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints: */ +extern unsigned xthal_int_enable(unsigned); +extern unsigned xthal_int_disable(unsigned); + +/* Set/get virtual priority of an interrupt: */ +extern int xthal_set_int_vpri(int intnum, int vpri); +extern int xthal_get_int_vpri(int intnum); + +/* Set/get interrupt lockout level for exclusive access to virtual priority data structures: */ +extern void xthal_set_vpri_locklevel(unsigned intlevel); +extern unsigned xthal_get_vpri_locklevel(void); + +/* Set/get current virtual interrupt priority: */ +extern unsigned xthal_set_vpri(unsigned vpri); +extern unsigned xthal_get_vpri(void); +extern unsigned xthal_set_vpri_intlevel(unsigned intlevel); +extern unsigned xthal_set_vpri_lock(void); + + +/*---------------------------------------------------------------------- + Generic Interrupt Trampolining Support (DEPRECATED) + ----------------------------------------------------------------------*/ + +typedef void (XtHalVoidFunc)(void); + +/* Bitmask of interrupts currently trampolining down: */ +extern unsigned Xthal_tram_pending; + +/* + * Bitmask of which interrupts currently trampolining down synchronously are + * actually enabled; this bitmask is necessary because INTENABLE cannot hold + * that state (sync-trampolining interrupts must be kept disabled while + * trampolining); in the current implementation, any bit set here is not set + * in INTENABLE, and vice-versa; once a sync-trampoline is handled (at level + * one), its enable bit must be moved from here to INTENABLE: + */ +extern unsigned Xthal_tram_enabled; + +/* Bitmask of interrupts configured for sync trampolining: */ +extern unsigned Xthal_tram_sync; + +/* Trampoline support functions: */ +extern unsigned xthal_tram_pending_to_service( void ); +extern void xthal_tram_done( unsigned serviced_mask ); +extern int xthal_tram_set_sync( int intnum, int sync ); +extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn ); + + +/*---------------------------------------------------------------------- + Internal Memories + ----------------------------------------------------------------------*/ + +extern const unsigned char Xthal_num_instrom; +extern const unsigned char Xthal_num_instram; +extern const unsigned char Xthal_num_datarom; +extern const unsigned char Xthal_num_dataram; +extern const unsigned char Xthal_num_xlmi; + +/* Each of the following arrays contains at least one entry, + * or as many entries as needed if more than one: */ +extern const unsigned int Xthal_instrom_vaddr[]; +extern const unsigned int Xthal_instrom_paddr[]; +extern const unsigned int Xthal_instrom_size []; +extern const unsigned int Xthal_instram_vaddr[]; +extern const unsigned int Xthal_instram_paddr[]; +extern const unsigned int Xthal_instram_size []; +extern const unsigned int Xthal_datarom_vaddr[]; +extern const unsigned int Xthal_datarom_paddr[]; +extern const unsigned int Xthal_datarom_size []; +extern const unsigned int Xthal_dataram_vaddr[]; +extern const unsigned int Xthal_dataram_paddr[]; +extern const unsigned int Xthal_dataram_size []; +extern const unsigned int Xthal_xlmi_vaddr[]; +extern const unsigned int Xthal_xlmi_paddr[]; +extern const unsigned int Xthal_xlmi_size []; + + +/*---------------------------------------------------------------------- + Cache + ----------------------------------------------------------------------*/ + +/* number of cache sets in log2(lines per way) */ +extern const unsigned char Xthal_icache_setwidth; +extern const unsigned char Xthal_dcache_setwidth; +/* cache set associativity (number of ways) */ +extern const unsigned int Xthal_icache_ways; +extern const unsigned int Xthal_dcache_ways; +/* cache features */ +extern const unsigned char Xthal_icache_line_lockable; +extern const unsigned char Xthal_dcache_line_lockable; + +/* cache attribute register control (used by other HAL routines) */ +extern unsigned xthal_get_cacheattr( void ); +extern unsigned xthal_get_icacheattr( void ); +extern unsigned xthal_get_dcacheattr( void ); +extern void xthal_set_cacheattr( unsigned ); +extern void xthal_set_icacheattr( unsigned ); +extern void xthal_set_dcacheattr( unsigned ); +/* set cache attribute (access modes) for a range of memory */ +extern int xthal_set_region_attribute( void *addr, unsigned size, + unsigned cattr, unsigned flags ); +/* Bits of flags parameter to xthal_set_region_attribute(): */ +#define XTHAL_CAFLAG_EXPAND 0x000100 /* only expand allowed access to range, don't reduce it */ +#define XTHAL_CAFLAG_EXACT 0x000200 /* return error if can't apply change to exact range specified */ +#define XTHAL_CAFLAG_NO_PARTIAL 0x000400 /* don't apply change to regions partially covered by range */ +#define XTHAL_CAFLAG_NO_AUTO_WB 0x000800 /* don't writeback data after leaving writeback attribute */ +#define XTHAL_CAFLAG_NO_AUTO_INV 0x001000 /* don't invalidate after disabling cache (entering bypass) */ + +/* enable caches */ +extern void xthal_icache_enable( void ); /* DEPRECATED */ +extern void xthal_dcache_enable( void ); /* DEPRECATED */ +/* disable caches */ +extern void xthal_icache_disable( void ); /* DEPRECATED */ +extern void xthal_dcache_disable( void ); /* DEPRECATED */ + +/* invalidate the caches */ +extern void xthal_icache_all_invalidate( void ); +extern void xthal_dcache_all_invalidate( void ); +/* write dirty data back */ +extern void xthal_dcache_all_writeback( void ); +/* write dirty data back and invalidate */ +extern void xthal_dcache_all_writeback_inv( void ); +/* prefetch and lock specified memory range into cache */ +extern void xthal_icache_region_lock( void *addr, unsigned size ); +extern void xthal_dcache_region_lock( void *addr, unsigned size ); +extern void xthal_icache_line_lock(void *addr); +extern void xthal_dcache_line_lock(void *addr); +/* unlock from cache */ +extern void xthal_icache_all_unlock( void ); +extern void xthal_dcache_all_unlock( void ); +extern void xthal_icache_region_unlock( void *addr, unsigned size ); +extern void xthal_dcache_region_unlock( void *addr, unsigned size ); +extern void xthal_icache_line_unlock(void *addr); +extern void xthal_dcache_line_unlock(void *addr); + + + +/*---------------------------------------------------------------------- + Local Memory ECC/Parity + ----------------------------------------------------------------------*/ + +/* Inject memory errors; flags is bit combination of XTHAL_MEMEP_F_xxx: */ +extern void xthal_memep_inject_error(void *addr, int size, int flags); + + + +/*---------------------------------------------------------------------- + Memory Management Unit + ----------------------------------------------------------------------*/ + +extern const unsigned char Xthal_have_spanning_way; +extern const unsigned char Xthal_have_identity_map; +extern const unsigned char Xthal_have_mimic_cacheattr; +extern const unsigned char Xthal_have_xlt_cacheattr; +extern const unsigned char Xthal_have_cacheattr; +extern const unsigned char Xthal_have_tlbs; + +extern const unsigned char Xthal_mmu_asid_bits; /* 0 .. 8 */ +extern const unsigned char Xthal_mmu_asid_kernel; +extern const unsigned char Xthal_mmu_rings; /* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */ +extern const unsigned char Xthal_mmu_ring_bits; +extern const unsigned char Xthal_mmu_sr_bits; +extern const unsigned char Xthal_mmu_ca_bits; +extern const unsigned int Xthal_mmu_max_pte_page_size; +extern const unsigned int Xthal_mmu_min_pte_page_size; + +extern const unsigned char Xthal_itlb_way_bits; +extern const unsigned char Xthal_itlb_ways; +extern const unsigned char Xthal_itlb_arf_ways; +extern const unsigned char Xthal_dtlb_way_bits; +extern const unsigned char Xthal_dtlb_ways; +extern const unsigned char Xthal_dtlb_arf_ways; + +/* Convert between virtual and physical addresses (through static maps only): */ +/*** WARNING: these two functions may go away in a future release; don't depend on them! ***/ +extern int xthal_static_v2p( unsigned vaddr, unsigned *paddrp ); +extern int xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached ); + + +#ifdef __cplusplus +} +#endif +#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */ + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + + + +/**************************************************************************** + EXPERIMENTAL and DEPRECATED Definitions + ****************************************************************************/ + + +#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef INCLUDE_DEPRECATED_HAL_CODE +extern const unsigned char Xthal_have_old_exc_arch; +extern const unsigned char Xthal_have_mmu; +extern const unsigned int Xthal_num_regs; +extern const unsigned char Xthal_num_iroms; +extern const unsigned char Xthal_num_irams; +extern const unsigned char Xthal_num_droms; +extern const unsigned char Xthal_num_drams; +extern const unsigned int Xthal_configid0; +extern const unsigned int Xthal_configid1; +#endif + +#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE +#define XTHAL_24_BIT_BREAK 0x80000000 +#define XTHAL_16_BIT_BREAK 0x40000000 +extern const unsigned short Xthal_ill_inst_16[16]; +#define XTHAL_DEST_REG 0xf0000000 /* Mask for destination register */ +#define XTHAL_DEST_REG_INST 0x08000000 /* Branch address is in register */ +#define XTHAL_DEST_REL_INST 0x04000000 /* Branch address is relative */ +#define XTHAL_RFW_INST 0x00000800 +#define XTHAL_RFUE_INST 0x00000400 +#define XTHAL_RFI_INST 0x00000200 +#define XTHAL_RFE_INST 0x00000100 +#define XTHAL_RET_INST 0x00000080 +#define XTHAL_BREAK_INST 0x00000040 +#define XTHAL_SYSCALL_INST 0x00000020 +#define XTHAL_LOOP_END 0x00000010 /* Not set by xthal_inst_type */ +#define XTHAL_JUMP_INST 0x00000008 /* Call or jump instruction */ +#define XTHAL_BRANCH_INST 0x00000004 /* Branch instruction */ +#define XTHAL_24_BIT_INST 0x00000002 +#define XTHAL_16_BIT_INST 0x00000001 +typedef struct xthal_state { + unsigned pc; + unsigned ar[16]; + unsigned lbeg; + unsigned lend; + unsigned lcount; + unsigned extra_ptr; + unsigned cpregs_ptr[XTHAL_MAX_CPS]; +} XTHAL_STATE; +extern unsigned int xthal_inst_type(void *addr); +extern unsigned int xthal_branch_addr(void *addr); +extern unsigned int xthal_get_npc(XTHAL_STATE *user_state); +#endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */ + +#ifdef __cplusplus +} +#endif +#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */ + +#endif /*XTENSA_HAL_H*/ diff --git a/target_firmware/magpie_fw_dev/target/inc/xtensa-elf/xtensa/xtruntime.h b/target_firmware/magpie_fw_dev/target/inc/xtensa-elf/xtensa/xtruntime.h new file mode 100644 index 0000000..1c9173b --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/xtensa-elf/xtensa/xtruntime.h @@ -0,0 +1,169 @@ +/* + * xtruntime.h -- general C definitions for single-threaded run-time + * + * Copyright (c) 2002-2006 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +#ifndef XTRUNTIME_H +#define XTRUNTIME_H + +#include +#include + +#ifndef XTSTR +#define _XTSTR(x) # x +#define XTSTR(x) _XTSTR(x) +#endif + +#define _xtos_set_execption_handler _xtos_set_exception_handler /* backward compatibility */ +#define _xtos_set_saved_intenable _xtos_ints_on /* backward compatibility */ +#define _xtos_clear_saved_intenable _xtos_ints_off /* backward compatibility */ + +#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__) + +#ifdef __cplusplus +extern "C" { +#endif + +/*typedef void (_xtos_timerdelta_func)(int);*/ +#ifdef __cplusplus +typedef void (_xtos_handler_func)(...); +#else +typedef void (_xtos_handler_func)(); +#endif +typedef _xtos_handler_func *_xtos_handler; + +/* + * unsigned XTOS_SET_INTLEVEL(int intlevel); + * This macro sets the current interrupt level. + * The 'intlevel' parameter must be a constant. + * This macro returns a 32-bit value that must be passed to + * XTOS_RESTORE_INTLEVEL() to restore the previous interrupt level. + * XTOS_RESTORE_JUST_INTLEVEL() also does this, but in XEA2 configs + * it restores only PS.INTLEVEL rather than the entire PS register + * and thus is slower. + */ +#if !XCHAL_HAVE_INTERRUPTS +# define XTOS_SET_INTLEVEL(intlevel) +# define XTOS_SET_MIN_INTLEVEL(intlevel) +# define XTOS_RESTORE_INTLEVEL(restoreval) +# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) +#elif XCHAL_HAVE_XEA2 +/* In XEA2, we can simply safely set PS.INTLEVEL directly: */ +/* NOTE: these asm macros don't modify memory, but they are marked + * as such to act as memory access barriers to the compiler because + * these macros are sometimes used to delineate critical sections; + * function calls are natural barriers (the compiler does not know + * whether a function modifies memory) unless declared to be inlined. */ +# define XTOS_SET_INTLEVEL(intlevel) ({ unsigned __tmp; \ + __asm__ __volatile__( "rsil %0, " XTSTR(intlevel) "\n" \ + : "=a" (__tmp) : : "memory" ); \ + __tmp;}) +# define XTOS_SET_MIN_INTLEVEL(intlevel) ({ unsigned __tmp, __tmp2, __tmp3; \ + __asm__ __volatile__( "rsr %0, " XTSTR(PS) "\n" /* get old (current) PS.INTLEVEL */ \ + "movi %2, " XTSTR(intlevel) "\n" \ + "extui %1, %0, 0, 4\n" /* keep only INTLEVEL bits of parameter */ \ + "blt %2, %1, 1f\n" \ + "rsil %0, " XTSTR(intlevel) "\n" \ + "1:\n" \ + : "=a" (__tmp), "=&a" (__tmp2), "=&a" (__tmp3) : : "memory" ); \ + __tmp;}) +# define XTOS_RESTORE_INTLEVEL(restoreval) do{ unsigned __tmp = (restoreval); \ + __asm__ __volatile__( "wsr %0, " XTSTR(PS) " ; rsync\n" \ + : : "a" (__tmp) : "memory" ); \ + }while(0) +# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_intlevel(restoreval) +#else +/* In XEA1, we have to rely on INTENABLE register virtualization: */ +extern unsigned _xtos_set_vpri( unsigned vpri ); +extern unsigned _xtos_vpri_enabled; /* current virtual priority */ +# define XTOS_SET_INTLEVEL(intlevel) _xtos_set_vpri(~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel)) +# define XTOS_SET_MIN_INTLEVEL(intlevel) _xtos_set_vpri(_xtos_vpri_enabled & ~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel)) +# define XTOS_RESTORE_INTLEVEL(restoreval) _xtos_set_vpri(restoreval) +# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_vpri(restoreval) +#endif + +/* + * The following macros build upon the above. They are generally used + * instead of invoking the SET_INTLEVEL and SET_MIN_INTLEVEL macros directly. + * They all return a value that can be used with XTOS_RESTORE_INTLEVEL() + * or _xtos_restore_intlevel() or _xtos_restore_just_intlevel() to restore + * the effective interrupt level to what it was before the macro was invoked. + * In XEA2, the DISABLE macros are much faster than the MASK macros + * (in all configs, DISABLE sets the effective interrupt level, whereas MASK + * makes ensures the effective interrupt level is at least the level given + * without lowering it; in XEA2 with INTENABLE virtualization, these macros + * affect PS.INTLEVEL only, not the virtual priority, so DISABLE has partial + * MASK semantics). + * + * A typical critical section sequence might be: + * unsigned rval = XTOS_DISABLE_EXCM_INTERRUPTS; + * ... critical section ... + * XTOS_RESTORE_INTLEVEL(rval); + */ +/* Enable all interrupts (those activated with _xtos_ints_on()): */ +#define XTOS_ENABLE_INTERRUPTS XTOS_SET_INTLEVEL(0) +/* Disable low priority level interrupts (they can interact with the OS): */ +#define XTOS_DISABLE_LOWPRI_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS) +#define XTOS_MASK_LOWPRI_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS) +/* Disable interrupts that can interact with the OS: */ +#define XTOS_DISABLE_EXCM_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL) +#define XTOS_MASK_EXCM_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_EXCM_LEVEL) +#if 0 /* XTOS_LOCK_LEVEL is not exported to applications */ +/* Disable interrupts that can interact with the OS, or manipulate virtual INTENABLE: */ +#define XTOS_DISABLE_LOCK_INTERRUPTS XTOS_SET_INTLEVEL(XTOS_LOCK_LEVEL) +#define XTOS_MASK_LOCK_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XTOS_LOCK_LEVEL) +#endif +/* Disable ALL interrupts (not for common use, particularly if one's processor + * configuration has high-level interrupts and one cares about their latency): */ +#define XTOS_DISABLE_ALL_INTERRUPTS XTOS_SET_INTLEVEL(15) + + +extern unsigned int _xtos_ints_off( unsigned int mask ); +extern unsigned int _xtos_ints_on( unsigned int mask ); +extern unsigned _xtos_set_intlevel( int intlevel ); +extern unsigned _xtos_set_min_intlevel( int intlevel ); +extern unsigned _xtos_restore_intlevel( unsigned restoreval ); +extern unsigned _xtos_restore_just_intlevel( unsigned restoreval ); +extern _xtos_handler _xtos_set_interrupt_handler( int n, _xtos_handler f ); +extern _xtos_handler _xtos_set_interrupt_handler_arg( int n, _xtos_handler f, void *arg ); +extern _xtos_handler _xtos_set_exception_handler( int n, _xtos_handler f ); + +extern void _xtos_memep_initrams( void ); +extern void _xtos_memep_enable( int flags ); + +/* Deprecated (but kept because they were documented): */ +extern unsigned int _xtos_read_ints( void ); /* use xthal_get_interrupt() instead */ +extern void _xtos_clear_ints( unsigned int mask ); /* use xthal_set_intclear() instead */ + +#if XCHAL_NUM_CONTEXTS > 1 +extern unsigned _xtos_init_context(int context_num, int stack_size, + _xtos_handler_func *start_func, int arg1); +#endif + +/* Deprecated: */ +#if XCHAL_NUM_TIMERS > 0 +extern void _xtos_timer_0_delta( int cycles ); +#endif +#if XCHAL_NUM_TIMERS > 1 +extern void _xtos_timer_1_delta( int cycles ); +#endif +#if XCHAL_NUM_TIMERS > 2 +extern void _xtos_timer_2_delta( int cycles ); +#endif +#if XCHAL_NUM_TIMERS > 3 +extern void _xtos_timer_3_delta( int cycles ); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* !_ASMLANGUAGE && !__ASSEMBLER__ */ + +#endif /* XTRUNTIME_H */ diff --git a/target_firmware/magpie_fw_dev/target/inc/xtensa/config/core-isa.h b/target_firmware/magpie_fw_dev/target/inc/xtensa/config/core-isa.h new file mode 100644 index 0000000..ccf9b2d --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/xtensa/config/core-isa.h @@ -0,0 +1,424 @@ +/* + * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa + * processor CORE configuration + * + * See , which includes this file, for more details. + */ + +/* + * Xtensa processor core configuration information. + * + * Customer ID=4748; Build=0x2230f; Copyright (c) 1999-2008 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +#ifndef _XTENSA_CORE_CONFIGURATION_H +#define _XTENSA_CORE_CONFIGURATION_H + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 1 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_CLAMPS 0 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ +#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_FP 0 /* floating point pkg */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 4 /* data width in bytes */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ + +#define XCHAL_CORE_ID "Magpie_P0" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x0002230F /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC280DBFF /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x0D02230F /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX2.1.0" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2210 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 0 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 221000 /* major*100+minor */ +#define XCHAL_HW_REL_LX2 1 +#define XCHAL_HW_REL_LX2_1 1 +#define XCHAL_HW_REL_LX2_1_0 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2210 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 0 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 221000 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2210 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 0 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 221000 /* latest targeted hw */ + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 16 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 0 +#define XCHAL_DCACHE_SETWIDTH 0 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 1 +#define XCHAL_DCACHE_WAYS 1 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 0 +#define XCHAL_DCACHE_LINE_LOCKABLE 0 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 + +/* Number of encoded cache attr bits (see for decoded bits): */ +#define XCHAL_CA_BITS 4 + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ + +/* Instruction RAM 0: */ +#define XCHAL_INSTRAM0_VADDR 0x00800000 +#define XCHAL_INSTRAM0_PADDR 0x00800000 +#define XCHAL_INSTRAM0_SIZE 4194304 +#define XCHAL_INSTRAM0_ECC_PARITY 0 + +/* Data RAM 0: */ +#define XCHAL_DATARAM0_VADDR 0x00400000 +#define XCHAL_DATARAM0_PADDR 0x00400000 +#define XCHAL_DATARAM0_SIZE 4194304 +#define XCHAL_DATARAM0_ECC_PARITY 0 + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 1 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 19 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x00000001 +#define XCHAL_INTLEVEL2_MASK 0x00007FFE +#define XCHAL_INTLEVEL3_MASK 0x00038000 +#define XCHAL_INTLEVEL4_MASK 0x00000000 +#define XCHAL_INTLEVEL5_MASK 0x00040000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00000000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00000001 +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00007FFF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x0003FFFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x0003FFFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x0007FFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x0007FFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x0007FFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 2 +#define XCHAL_INT2_LEVEL 2 +#define XCHAL_INT3_LEVEL 2 +#define XCHAL_INT4_LEVEL 2 +#define XCHAL_INT5_LEVEL 2 +#define XCHAL_INT6_LEVEL 2 +#define XCHAL_INT7_LEVEL 2 +#define XCHAL_INT8_LEVEL 2 +#define XCHAL_INT9_LEVEL 2 +#define XCHAL_INT10_LEVEL 2 +#define XCHAL_INT11_LEVEL 2 +#define XCHAL_INT12_LEVEL 2 +#define XCHAL_INT13_LEVEL 2 +#define XCHAL_INT14_LEVEL 2 +#define XCHAL_INT15_LEVEL 3 +#define XCHAL_INT16_LEVEL 3 +#define XCHAL_INT17_LEVEL 3 +#define XCHAL_INT18_LEVEL 5 +#define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 5 /* NMI "level" (for use with + EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_NMI + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFF80000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000001 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0003FFFC +#define XCHAL_INTTYPE_MASK_TIMER 0x00000002 +#define XCHAL_INTTYPE_MASK_NMI 0x00040000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 18 /* non-maskable interrupt */ + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL1_NUM 0 +#define XCHAL_INTLEVEL5_NUM 18 +/* (There are many interrupts each at level(s) 2, 3.) */ + + +/* + * External interrupt vectors/levels. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */ +#define XCHAL_EXTINT0_NUM 2 /* (intlevel 2) */ +#define XCHAL_EXTINT1_NUM 3 /* (intlevel 2) */ +#define XCHAL_EXTINT2_NUM 4 /* (intlevel 2) */ +#define XCHAL_EXTINT3_NUM 5 /* (intlevel 2) */ +#define XCHAL_EXTINT4_NUM 6 /* (intlevel 2) */ +#define XCHAL_EXTINT5_NUM 7 /* (intlevel 2) */ +#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ +#define XCHAL_EXTINT7_NUM 9 /* (intlevel 2) */ +#define XCHAL_EXTINT8_NUM 10 /* (intlevel 2) */ +#define XCHAL_EXTINT9_NUM 11 /* (intlevel 2) */ +#define XCHAL_EXTINT10_NUM 12 /* (intlevel 2) */ +#define XCHAL_EXTINT11_NUM 13 /* (intlevel 2) */ +#define XCHAL_EXTINT12_NUM 14 /* (intlevel 2) */ +#define XCHAL_EXTINT13_NUM 15 /* (intlevel 3) */ +#define XCHAL_EXTINT14_NUM 16 /* (intlevel 3) */ +#define XCHAL_EXTINT15_NUM 17 /* (intlevel 3) */ +#define XCHAL_EXTINT16_NUM 18 /* (intlevel 5) */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (old) + 2 == XEA2 (new) + 0 == XEAX (extern) */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x008E0800 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x008E0800 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0x008E0000 +#define XCHAL_RESET_VECTOR0_PADDR 0x008E0000 +#define XCHAL_RESET_VECTOR1_VADDR 0x0F000000 +#define XCHAL_RESET_VECTOR1_PADDR 0x0F000000 +#define XCHAL_RESET_VECTOR_VADDR 0x008E0000 +#define XCHAL_RESET_VECTOR_PADDR 0x008E0000 +#define XCHAL_USER_VECOFS 0x00000620 +#define XCHAL_USER_VECTOR_VADDR 0x008E0E20 +#define XCHAL_USER_VECTOR_PADDR 0x008E0E20 +#define XCHAL_KERNEL_VECOFS 0x00000540 +#define XCHAL_KERNEL_VECTOR_VADDR 0x008E0D40 +#define XCHAL_KERNEL_VECTOR_PADDR 0x008E0D40 +#define XCHAL_DOUBLEEXC_VECOFS 0x00000720 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x008E0F20 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x008E0F20 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x008E0800 +#define XCHAL_WINDOW_VECTORS_PADDR 0x008E0800 +#define XCHAL_INTLEVEL2_VECOFS 0x00000220 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x008E0A20 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x008E0A20 +#define XCHAL_INTLEVEL3_VECOFS 0x00000320 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x008E0B20 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x008E0B20 +#define XCHAL_INTLEVEL4_VECOFS 0x00000420 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x008E0C20 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x008E0C20 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL4_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x000004E4 +#define XCHAL_NMI_VECTOR_VADDR 0x008E0CE4 +#define XCHAL_NMI_VECTOR_PADDR 0x008E0CE4 +#define XCHAL_INTLEVEL5_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL5_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL5_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ +#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ +/* If none of the above last 4 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* _XTENSA_CORE_CONFIGURATION_H */ diff --git a/target_firmware/magpie_fw_dev/target/inc/xtensa/config/core-matmap.h b/target_firmware/magpie_fw_dev/target/inc/xtensa/config/core-matmap.h new file mode 100644 index 0000000..f0acaca --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/xtensa/config/core-matmap.h @@ -0,0 +1,301 @@ +/* + * xtensa/config/core-matmap.h -- Memory access and translation mapping + * parameters (CHAL) of the Xtensa processor core configuration. + * + * If you are using Xtensa Tools, see (which includes + * this file) for more details. + * + * In the Xtensa processor products released to date, all parameters + * defined in this file are derivable (at least in theory) from + * information contained in the core-isa.h header file. + * In particular, the following core configuration parameters are relevant: + * XCHAL_HAVE_CACHEATTR + * XCHAL_HAVE_MIMIC_CACHEATTR + * XCHAL_HAVE_XLT_CACHEATTR + * XCHAL_HAVE_PTP_MMU + * XCHAL_ITLB_ARF_ENTRIES_LOG2 + * XCHAL_DTLB_ARF_ENTRIES_LOG2 + * XCHAL_DCACHE_IS_WRITEBACK + * XCHAL_ICACHE_SIZE (presence of I-cache) + * XCHAL_DCACHE_SIZE (presence of D-cache) + * XCHAL_HW_VERSION_MAJOR + * XCHAL_HW_VERSION_MINOR + */ + +/* + * Customer ID=4748; Build=0x2230f; Copyright (c) 1999-2008 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + + +#ifndef XTENSA_CONFIG_CORE_MATMAP_H +#define XTENSA_CONFIG_CORE_MATMAP_H + + +/*---------------------------------------------------------------------- + CACHE (MEMORY ACCESS) ATTRIBUTES + ----------------------------------------------------------------------*/ + + +/* Cache Attribute encodings -- lists of access modes for each cache attribute: */ +#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION +#define XCHAL_LCA_LIST XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_EXCEPTION +#define XCHAL_SCA_LIST XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_EXCEPTION + + +/* + * Specific encoded cache attribute values of general interest. + * If a specific cache mode is not available, the closest available + * one is returned instead (eg. writethru instead of writeback, + * bypass instead of writethru). + */ +#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */ +#define XCHAL_CA_WRITETHRU 2 /* cache enabled (write-through) mode */ +#define XCHAL_CA_WRITEBACK 2 /* cache enabled (write-back) mode */ +#define XCHAL_CA_BYPASS_RW 0 /* cache disabled (bypassed) mode (no exec) */ +#define XCHAL_CA_WRITETHRU_RW 0 /* cache enabled (write-through) mode (no exec) */ +#define XCHAL_CA_WRITEBACK_RW 0 /* cache enabled (write-back) mode (no exec) */ +#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */ +#define XCHAL_CA_ISOLATE 0 /* cache isolate (accesses go to cache not memory) mode */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* + * General notes on MMU parameters. + * + * Terminology: + * ASID = address-space ID (acts as an "extension" of virtual addresses) + * VPN = virtual page number + * PPN = physical page number + * CA = encoded cache attribute (access modes) + * TLB = translation look-aside buffer (term is stretched somewhat here) + * I = instruction (fetch accesses) + * D = data (load and store accesses) + * way = each TLB (ITLB and DTLB) consists of a number of "ways" + * that simultaneously match the virtual address of an access; + * a TLB successfully translates a virtual address if exactly + * one way matches the vaddr; if none match, it is a miss; + * if multiple match, one gets a "multihit" exception; + * each way can be independently configured in terms of number of + * entries, page sizes, which fields are writable or constant, etc. + * set = group of contiguous ways with exactly identical parameters + * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE + * from the page table and storing it in one of the auto-refill ways; + * if this PTE load also misses, a miss exception is posted for s/w. + * min-wired = a "min-wired" way can be used to map a single (minimum-sized) + * page arbitrarily under program control; it has a single entry, + * is non-auto-refill (some other way(s) must be auto-refill), + * all its fields (VPN, PPN, ASID, CA) are all writable, and it + * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current + * restriction is that this be the only page size it supports). + * + * TLB way entries are virtually indexed. + * TLB ways that support multiple page sizes: + * - must have all writable VPN and PPN fields; + * - can only use one page size at any given time (eg. setup at startup), + * selected by the respective ITLBCFG or DTLBCFG special register, + * whose bits n*4+3 .. n*4 index the list of page sizes for way n + * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n); + * this list may be sparse for auto-refill ways because auto-refill + * ways have independent lists of supported page sizes sharing a + * common encoding with PTE entries; the encoding is the index into + * this list; unsupported sizes for a given way are zero in the list; + * selecting unsupported sizes results in undefined hardware behaviour; + * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition). + */ + +#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */ +#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */ +#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */ +#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */ +#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */ +#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */ + + +/*** Instruction TLB: ***/ + +#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */ +#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ +#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */ +#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */ + +/* Way set to which each way belongs: */ +#define XCHAL_ITLB_WAY0_SET 0 + +/* Ways sets that are used by hardware auto-refill (ARF): */ +#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */ + +/* Way sets that are "min-wired" (see terminology comment above): */ +#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ + + +/* ITLB way set 0 (group of ways 0 thru 0): */ +#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */ +#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ +#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ +#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ +/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */ +#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000 +#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000 +#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000 +#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000 +#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000 +#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000 +#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000 +#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000 +/* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */ +#define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000 +#define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000 +#define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000 +#define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000 +#define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000 +#define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000 +#define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000 +#define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000 +/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */ +#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02 + + +/*** Data TLB: ***/ + +#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */ +#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ +#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */ +#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */ + +/* Way set to which each way belongs: */ +#define XCHAL_DTLB_WAY0_SET 0 + +/* Ways sets that are used by hardware auto-refill (ARF): */ +#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */ + +/* Way sets that are "min-wired" (see terminology comment above): */ +#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ + + +/* DTLB way set 0 (group of ways 0 thru 0): */ +#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */ +#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ +#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ +#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ +/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */ +#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000 +#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000 +#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000 +#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000 +#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000 +#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000 +#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000 +#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000 +/* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */ +#define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000 +#define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000 +#define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000 +#define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000 +#define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000 +#define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000 +#define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000 +#define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000 +/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */ +#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02 + + + + +#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ diff --git a/target_firmware/magpie_fw_dev/target/inc/xtensa/config/specreg.h b/target_firmware/magpie_fw_dev/target/inc/xtensa/config/specreg.h new file mode 100644 index 0000000..f342a9d --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/xtensa/config/specreg.h @@ -0,0 +1,84 @@ +/* + * Xtensa Special Register symbolic names + */ + +/* $Id: //depot/rel/BadgerPass/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ + +/* + * Customer ID=4748; Build=0x2230f; Copyright (c) 1998-2002 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +#ifndef XTENSA_SPECREG_H +#define XTENSA_SPECREG_H + +/* Include these special register bitfield definitions, for historical reasons: */ +#include + + +/* Special registers: */ +#define LBEG 0 +#define LEND 1 +#define LCOUNT 2 +#define SAR 3 +#define LITBASE 5 +#define SCOMPARE1 12 +#define WINDOWBASE 72 +#define WINDOWSTART 73 +#define IBREAKENABLE 96 +#define DDR 104 +#define IBREAKA_0 128 +#define IBREAKA_1 129 +#define DBREAKA_0 144 +#define DBREAKA_1 145 +#define DBREAKC_0 160 +#define DBREAKC_1 161 +#define EPC_1 177 +#define EPC_2 178 +#define EPC_3 179 +#define EPC_4 180 +#define EPC_5 181 +#define DEPC 192 +#define EPS_2 194 +#define EPS_3 195 +#define EPS_4 196 +#define EPS_5 197 +#define EXCSAVE_1 209 +#define EXCSAVE_2 210 +#define EXCSAVE_3 211 +#define EXCSAVE_4 212 +#define EXCSAVE_5 213 +#define INTERRUPT 226 +#define INTENABLE 228 +#define PS 230 +#define VECBASE 231 +#define EXCCAUSE 232 +#define DEBUGCAUSE 233 +#define CCOUNT 234 +#define PRID 235 +#define ICOUNT 236 +#define ICOUNTLEVEL 237 +#define EXCVADDR 238 +#define CCOMPARE_0 240 +#define MISC_REG_0 244 +#define MISC_REG_1 245 + +/* Special cases (bases of special register series): */ +#define IBREAKA 128 +#define DBREAKA 144 +#define DBREAKC 160 +#define EPC 176 +#define EPS 192 +#define EXCSAVE 208 +#define CCOMPARE 240 + +/* Special names for read-only and write-only interrupt registers: */ +#define INTREAD 226 +#define INTSET 226 +#define INTCLEAR 227 + +#endif /* XTENSA_SPECREG_H */ diff --git a/target_firmware/magpie_fw_dev/target/inc/xtensa/config/tie.h b/target_firmware/magpie_fw_dev/target/inc/xtensa/config/tie.h new file mode 100644 index 0000000..b53910c --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/xtensa/config/tie.h @@ -0,0 +1,54 @@ +/* + * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration + * + * NOTE: This header file is not meant to be included directly. + */ + +/* + * This header file describes this specific Xtensa processor's TIE extensions + * that extend basic Xtensa core functionality. It is customized to this + * Xtensa processor configuration. + * + * Customer ID=4748; Build=0x2230f; Copyright (C) 1999-2008 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +#ifndef _XTENSA_CORE_TIE_H +#define _XTENSA_CORE_TIE_H + +#define XCHAL_CP_NUM 0 /* number of coprocessors */ +#define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */ +#define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */ +#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ + +/* Save area for non-coprocessor optional and custom (TIE) state: */ +#define XCHAL_NCP_SA_SIZE 4 +#define XCHAL_NCP_SA_ALIGN 4 + +/* Total save area for optional and custom state (NCP + CPn): */ +#define XCHAL_TOTAL_SA_SIZE 16 /* with 16-byte align padding */ +#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */ + +/* + * Detailed contents of save areas. + * NOTE: caller must define the XCHAL_SA_{UREG,SREG,REGF} macros (they + * are not defined here) before expanding the XCHAL_SA_xxx_LIST macros. + * + * XCHAL_SA_SREG(dbnum,offset,size,contentsz,align,name,sregnum,bitmask,x,x) + * XCHAL_SA_UREG(dbnum,offset,size,contentsz,align,name,uregnum,bitmask,x,x) + * XCHAL_SA_REGF(dbnum,offset,size,contentsz,align,name,index,span,x,x, + * basename,regf_name,regf_numentries) + */ + +#define XCHAL_SA_NCP_NUM 1 +#define XCHAL_SA_NCP_LIST \ + XCHAL_SA_SREG(0x020C, 0, 4, 4, 4, scompare1, 12,0xFFFFFFFF,0,0) + +/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ +#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 + +#endif /*_XTENSA_CORE_TIE_H*/