From: Christian Lamparter <chunkeey@googlemail.com>
Date: Fri, 13 Aug 2010 18:56:37 +0000 (+0200)
Subject: carl9170 firmware: put power management definitions into the correct place
X-Git-Tag: 1.8.5~9
X-Git-Url: https://jxself.org/git/?a=commitdiff_plain;h=b43f7cee6be2d4bab9345e24b80eeedf6b727c79;p=carl9170fw.git

carl9170 firmware: put power management definitions into the correct place

Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
---

diff --git a/include/shared/hw.h b/include/shared/hw.h
index fa40ebd..33e856b 100644
--- a/include/shared/hw.h
+++ b/include/shared/hw.h
@@ -387,26 +387,6 @@
 
 #define	AR9170_MAC_REG_DMA_TXQX_ADDR_CURR	(AR9170_MAC_REG_BASE + 0xdc0)
 
-#define	AR9170_PWR_REG_BASE			0x1d4000
-
-#define AR9170_PWR_REG_POWER_STATE		(AR9170_PWR_REG_BASE + 0x000)
-
-#define	AR9170_PWR_REG_ADDA_BB			(AR9170_PWR_REG_BASE + 0x004)
-#define		AR9170_PWR_ADDA_BB_USB_FIFO_RESET	0x00000005
-#define		AR9170_PWR_ADDA_BB_COLD_RESET		0x00000800
-#define		AR9170_PWR_ADDA_BB_WARM_RESET		0x00000400
-
-#define	AR9170_PWR_REG_CLOCK_SEL		(AR9170_PWR_REG_BASE + 0x008)
-#define		AR9170_PWR_CLK_AHB_40MHZ		0
-#define		AR9170_PWR_CLK_AHB_20_22MHZ		1
-#define		AR9170_PWR_CLK_AHB_40_44MHZ		2
-#define		AR9170_PWR_CLK_AHB_80_88MHZ		3
-#define		AR9170_PWR_CLK_DAC_160_INV_DLY		0x70
-
-#define	AR9170_PWR_REG_CHIP_REVISION		(AR9170_PWR_REG_BASE + 0x010)
-#define AR9170_PWR_REG_PLL_ADDAC		(AR9170_PWR_REG_BASE + 0x014)
-#define	AR9170_PWR_REG_WATCH_DOG_MAGIC		(AR9170_PWR_REG_BASE + 0x020)
-
 /* Random number generator */
 #define	AR9170_RAND_REG_BASE			0x1d0000
 
@@ -460,6 +440,27 @@
 #define	AR9170_INT_REG_FIQ_ENCODE		(AR9170_INT_REG_BASE + 0x020)
 #define	AR9170_INT_INT_IRQ_ENCODE		(AR9170_INT_REG_BASE + 0x024)
 
+/* Power Management */
+#define	AR9170_PWR_REG_BASE			0x1d4000
+
+#define AR9170_PWR_REG_POWER_STATE		(AR9170_PWR_REG_BASE + 0x000)
+
+#define	AR9170_PWR_REG_ADDA_BB			(AR9170_PWR_REG_BASE + 0x004)
+#define		AR9170_PWR_ADDA_BB_USB_FIFO_RESET	0x00000005
+#define		AR9170_PWR_ADDA_BB_COLD_RESET		0x00000800
+#define		AR9170_PWR_ADDA_BB_WARM_RESET		0x00000400
+
+#define	AR9170_PWR_REG_CLOCK_SEL		(AR9170_PWR_REG_BASE + 0x008)
+#define		AR9170_PWR_CLK_AHB_40MHZ		0
+#define		AR9170_PWR_CLK_AHB_20_22MHZ		1
+#define		AR9170_PWR_CLK_AHB_40_44MHZ		2
+#define		AR9170_PWR_CLK_AHB_80_88MHZ		3
+#define		AR9170_PWR_CLK_DAC_160_INV_DLY		0x70
+
+#define	AR9170_PWR_REG_CHIP_REVISION		(AR9170_PWR_REG_BASE + 0x010)
+#define AR9170_PWR_REG_PLL_ADDAC		(AR9170_PWR_REG_BASE + 0x014)
+#define	AR9170_PWR_REG_WATCH_DOG_MAGIC		(AR9170_PWR_REG_BASE + 0x020)
+
 /* Faraday USB Controller */
 #define	AR9170_USB_REG_BASE			0x1e1000