From: Oleksij Rempel Date: Sun, 27 Apr 2014 08:49:35 +0000 (+0200) Subject: remove ath_hal_reg_write_target and OS_REG_WRITE X-Git-Tag: 1.4.0~6^2~9 X-Git-Url: https://jxself.org/git/?a=commitdiff_plain;h=9eb079a1801b89fec0578831c95c0fb1f1383158;p=open-ath9k-htc-firmware.git remove ath_hal_reg_write_target and OS_REG_WRITE instead use iowrite32_mac Signed-off-by: Oleksij Rempel --- diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_io_pvt.h b/target_firmware/magpie_fw_dev/target/adf/adf_os_io_pvt.h index fd5659a..105216f 100755 --- a/target_firmware/magpie_fw_dev/target/adf/adf_os_io_pvt.h +++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_io_pvt.h @@ -47,8 +47,6 @@ (((x) & 0x0000ff00) << 8) | \ (((x) & 0x000000ff) << 24)) -#define __adf_os_reg_write32(_dev, _addr, _val) *((a_uint32_t *)(WLAN_BASE_ADDRESS + _addr)) = _val; - #define __adf_os_ntohs(x) x #define __adf_os_ntohl(x) x diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_os_io.h b/target_firmware/magpie_fw_dev/target/inc/adf_os_io.h index 018206f..7924288 100755 --- a/target_firmware/magpie_fw_dev/target/inc/adf_os_io.h +++ b/target_firmware/magpie_fw_dev/target/inc/adf_os_io.h @@ -60,11 +60,16 @@ static inline a_uint32_t ioread32(a_uint32_t addr) /** * @brief Write a 32-bit value into register * - * @param[in] osdev platform device object * @param[in] addr register addr - * @param[in] l the 32-bit value to be written + * @param[in] b the 32-bit value to be written */ -#define adf_os_reg_write32(osdev, addr, l) __adf_os_reg_write32(osdev, addr, l) + +static inline void iowrite32(volatile a_uint32_t addr, a_uint32_t b) +{ + *(volatile a_uint32_t *) addr = b; +} + +#define iowrite32_mac(addr, b) iowrite32(WLAN_BASE_ADDRESS + (addr), (b)) /** * @brief Convert a 16-bit value from network byte order to host byte order diff --git a/target_firmware/wlan/ah_internal.h b/target_firmware/wlan/ah_internal.h index 242ac7f..0004a1c 100755 --- a/target_firmware/wlan/ah_internal.h +++ b/target_firmware/wlan/ah_internal.h @@ -237,16 +237,16 @@ struct ath_hal_private { #define SM(_v, _f) (((_v) << _f##_S) & _f) #define MS(_v, _f) (((_v) & _f) >> _f##_S) #define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ - OS_REG_WRITE(_a, _r, \ + iowrite32_mac(_r, \ (ioread32_mac(_r) & ~_f) \ | (((_v) << _f##_S) & _f)) #define OS_REG_RMW(_a, _r, _set, _clr) \ - OS_REG_WRITE(_a, _r, \ + iowrite32_mac(_r, \ (ioread32_mac(_r) & ~(_clr)) | (_set)) #define OS_REG_SET_BIT(_a, _r, _f) \ - OS_REG_WRITE(_a, _r, ioread32_mac(_r) | _f) + iowrite32_mac(_r, ioread32_mac(_r) | _f) #define OS_REG_CLR_BIT(_a, _r, _f) \ - OS_REG_WRITE(_a, _r, ioread32_mac(_r) & ~_f) + iowrite32_mac(_r, ioread32_mac(_r) & ~_f) /* wait for the register contents to have the specified value */ diff --git a/target_firmware/wlan/ah_osdep.c b/target_firmware/wlan/ah_osdep.c index 92e8d6b..a984be7 100755 --- a/target_firmware/wlan/ah_osdep.c +++ b/target_firmware/wlan/ah_osdep.c @@ -72,22 +72,6 @@ _ath_hal_attach_tgt(a_uint32_t devid, HAL_SOFTC sc, extern void *global_hdl; -/* - * Memory-mapped device register read/write. These are here - * as routines when debugging support is enabled and/or when - * explicitly configured to use function calls. The latter is - * for architectures that might need to do something before - * referencing memory (e.g. remap an i/o window). - * - * NB: see the comments in ah_osdep.h about byte-swapping register - * reads and writes to understand what's going on below. - */ -void __ahdecl -ath_hal_reg_write_target(struct ath_hal *ah, a_uint32_t reg, a_uint32_t val) -{ - adf_os_reg_write32(ah->ah_dev, reg, val); -} - /* * Delay n microseconds. */ diff --git a/target_firmware/wlan/ah_osdep.h b/target_firmware/wlan/ah_osdep.h index 322148f..0b3a99f 100755 --- a/target_firmware/wlan/ah_osdep.h +++ b/target_firmware/wlan/ah_osdep.h @@ -146,11 +146,6 @@ extern a_uint32_t __ahdecl ath_hal_getuptime(struct ath_hal *); #define __bswap16(_x) (_x) #endif -#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write_target(_ah, _reg, _val) - -extern void __ahdecl ath_hal_reg_write_target(struct ath_hal *ah, - a_uint32_t reg, a_uint32_t val); - #define AH_USE_EEPROM 0x00000001 extern struct ath_hal *_ath_hal_attach_tgt( a_uint32_t, HAL_SOFTC, adf_os_device_t, a_uint32_t flags, void* status); diff --git a/target_firmware/wlan/ar5416_hw.c b/target_firmware/wlan/ar5416_hw.c index 5d0d121..3f3c4bc 100644 --- a/target_firmware/wlan/ar5416_hw.c +++ b/target_firmware/wlan/ar5416_hw.c @@ -210,7 +210,7 @@ HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) | AR_INTR_SYNC_HOST1_PERR))) ? AH_TRUE : AH_FALSE; if (AH_TRUE == fatal_int) { - OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); + iowrite32_mac(AR_INTR_SYNC_CAUSE_CLR, sync_cause); (void) ioread32_mac(AR_INTR_SYNC_CAUSE_CLR); } #endif @@ -225,7 +225,7 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) a_uint32_t mask; if (omask & HAL_INT_GLOBAL) { - OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); + iowrite32_mac(AR_IER, AR_IER_DISABLE); (void) ioread32_mac(AR_IER); } @@ -253,20 +253,20 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) mask |= AR_IMR_BCNMISC; } - OS_REG_WRITE(ah, AR_IMR, mask); + iowrite32_mac(AR_IMR, mask); (void) ioread32_mac(AR_IMR); ahp->ah_maskReg = ints; /* Re-enable interrupts if they were enabled before. */ if (ints & HAL_INT_GLOBAL) { - OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); + iowrite32_mac(AR_IER, AR_IER_ENABLE); /* See explanation above... */ (void) ioread32_mac(AR_IER); } - OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); - OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); - OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL); + iowrite32_mac(AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); + iowrite32_mac(AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); + iowrite32_mac(AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL); return omask; } @@ -290,13 +290,13 @@ u_int64_t ar5416GetTsf64(struct ath_hal *ah) /******/ void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp) { - OS_REG_WRITE(ah, AR_RXDP, rxdp); + iowrite32_mac(AR_RXDP, rxdp); HALASSERT(ioread32_mac(AR_RXDP) == rxdp); } HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah) { - OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ + iowrite32_mac(AR_CR, AR_CR_RXD); /* Set receive disable bit */ if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) { return AH_FALSE; } else { @@ -308,19 +308,19 @@ void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits) { a_uint32_t phybits; - OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR); + iowrite32_mac(AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR); phybits = 0; if (bits & HAL_RX_FILTER_PHYRADAR) phybits |= AR_PHY_ERR_RADAR; if (bits & HAL_RX_FILTER_PHYERR) phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; - OS_REG_WRITE(ah, AR_PHY_ERR, phybits); + iowrite32_mac(AR_PHY_ERR, phybits); if (phybits) { - OS_REG_WRITE(ah, AR_RXCFG, + iowrite32_mac(AR_RXCFG, ioread32_mac(AR_RXCFG) | AR_RXCFG_ZLFDMA); } else { - OS_REG_WRITE(ah, AR_RXCFG, + iowrite32_mac(AR_RXCFG, ioread32_mac(AR_RXCFG) & ~AR_RXCFG_ZLFDMA); } @@ -328,7 +328,7 @@ void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits) void ar5416EnableReceive(struct ath_hal *ah) { - OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); + iowrite32_mac(AR_CR, AR_CR_RXE); } void ar5416StopPcuReceive(struct ath_hal *ah) @@ -474,8 +474,8 @@ HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel) } else if (curLevel > MIN_TX_FIFO_THRESHOLD) newLevel--; if (newLevel != curLevel) - OS_REG_WRITE(ah, AR_TXCFG, - (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG)); + iowrite32_mac(AR_TXCFG, + (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG)); /* re-enable chip interrupts */ ar5416SetInterrupts(ah, omask); @@ -494,7 +494,7 @@ HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp) */ HALASSERT((ioread32_mac(AR_Q_TXE) & (1 << q)) == 0); - OS_REG_WRITE(ah, AR_QTXDP(q), txdp); + iowrite32_mac(AR_QTXDP(q), txdp); return AH_TRUE; } @@ -507,7 +507,7 @@ HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q) /* Check to be sure we're not enabling a q that has its TXD bit set. */ HALASSERT((ioread32_mac(AR_Q_TXD) & (1 << q)) == 0); - OS_REG_WRITE(ah, AR_Q_TXE, 1 << q); + iowrite32_mac(AR_Q_TXE, 1 << q); return AH_TRUE; } @@ -536,7 +536,7 @@ a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q) & (1 << q)) { isrPrintf("RTSD on CAB queue\n"); /* Clear the ReadyTime shutdown status bits */ - OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q); + iowrite32_mac(AR_Q_RDYTIMESHDN, 1 << q); } } #endif @@ -550,7 +550,7 @@ HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah) /* * set txd on all queues */ - OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); + iowrite32_mac(AR_Q_TXD, AR_Q_TXD_M); /* * set tx abort bits @@ -584,7 +584,7 @@ HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah) /* * clear txd */ - OS_REG_WRITE(ah, AR_Q_TXD, 0); + iowrite32_mac(AR_Q_TXD, 0); return AH_TRUE; } @@ -597,14 +597,14 @@ HAL_BOOL ar5416StopTxDma(struct ath_hal*ah, a_uint32_t q) HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); - OS_REG_WRITE(ah, AR_Q_TXD, 1 << q); + iowrite32_mac(AR_Q_TXD, 1 << q); for (i = 1000; i != 0; i--) { if (ar5416NumTxPending(ah, q) == 0) break; OS_DELAY(100); /* XXX get actual value */ } - OS_REG_WRITE(ah, AR_Q_TXD, 0); + iowrite32_mac(AR_Q_TXD, 0); return (i != 0); } diff --git a/target_firmware/wlan/if_ath.c b/target_firmware/wlan/if_ath.c index 6a88712..864f48f 100755 --- a/target_firmware/wlan/if_ath.c +++ b/target_firmware/wlan/if_ath.c @@ -1391,7 +1391,7 @@ static a_int32_t ath_reg_read_filter(struct ath_hal *ah, a_int32_t addr) return ioread32_mac(0x407c) & 0x0000ffff; } else if (addr > 0xffff) /* SoC registers */ - return HAL_WORD_REG_READ(addr); + return ioread32(addr); else /* MAC registers */ return ioread32_mac(addr); @@ -1424,19 +1424,19 @@ static void ath_pll_reset_ones(struct ath_hal *ah) if(reset_pll == 0) { #if defined(PROJECT_K2) /* here we write to core register */ - HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0); + iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0); /* and here to mac register */ - ath_hal_reg_write_target(ah, 0x786c, + iowrite32_mac(0x786c, ioread32_mac(0x786c) | 0x6000000); - ath_hal_reg_write_target(ah, 0x786c, + iowrite32_mac(0x786c, ioread32_mac(0x786c) & (~0x6000000)); - HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20); + iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20); #elif defined(PROJECT_MAGPIE) && !defined (FPGA) - ath_hal_reg_write_target(ah, 0x7890, + iowrite32_mac(0x7890, ioread32_mac(0x7890) | 0x1800000); - ath_hal_reg_write_target(ah, 0x7890, + iowrite32_mac(0x7890, ioread32_mac(0x7890) & (~0x1800000)); #endif reset_pll = 1; @@ -1447,7 +1447,7 @@ static void ath_hal_reg_write_filter(struct ath_hal *ah, a_uint32_t reg, a_uint32_t val) { if(reg > 0xffff) { - HAL_WORD_REG_WRITE(reg, val); + iowrite32(reg, val); #if defined(PROJECT_K2) if(reg == 0x50040) { static uint8_t flg=0; @@ -1466,7 +1466,7 @@ static void ath_hal_reg_write_filter(struct ath_hal *ah, if(reg == 0x7014) ath_pll_reset_ones(ah); - ath_hal_reg_write_target(ah, reg, val); + iowrite32_mac(reg, val); } }