From: Oleksij Rempel Date: Mon, 30 Sep 2013 14:10:33 +0000 (+0200) Subject: hif/usb_api: unify platform specific patch file names X-Git-Tag: 1.4.0~10^2~2^2~4 X-Git-Url: https://jxself.org/git/?a=commitdiff_plain;h=08b259da5e8adb35a43983d9c73bdda4df07bc3d;p=open-ath9k-htc-firmware.git hif/usb_api: unify platform specific patch file names Signed-off-by: Oleksij Rempel --- diff --git a/target_firmware/CMakeLists.txt b/target_firmware/CMakeLists.txt index 7d26640..fc74434 100644 --- a/target_firmware/CMakeLists.txt +++ b/target_firmware/CMakeLists.txt @@ -46,7 +46,7 @@ SET(SOURCES IF(TARGET_K2) SET(SOURCES ${SOURCES} magpie_fw_dev/target/hif/k2_HIF_usb_patch.c - magpie_fw_dev/target/hif/k2_fw_usb_api.c + magpie_fw_dev/target/hif/usb_api_k2_patch.c ) SET(LIBS ${LIBS} hif) ADD_DEFINITIONS(-DPROJECT_K2) @@ -63,8 +63,8 @@ ELSEIF(TARGET_MAGPIE) -DMAGPIE_MERLIN ) SET(SOURCES ${SOURCES} + magpie_fw_dev/target/hif/usb_api_magpie_patch.c magpie_fw_dev/target/rompatch/cmnos_clock_patch.c - magpie_fw_dev/target/rompatch/usb_api_patch.c magpie_fw_dev/target/rompatch/HIF_usb_patch.c ) INCLUDE_DIRECTORIES( diff --git a/target_firmware/magpie_fw_dev/target/hif/k2_fw_usb_api.c b/target_firmware/magpie_fw_dev/target/hif/k2_fw_usb_api.c deleted file mode 100755 index bc6948d..0000000 --- a/target_firmware/magpie_fw_dev/target/hif/k2_fw_usb_api.c +++ /dev/null @@ -1,377 +0,0 @@ -/* - * Copyright (c) 2013 Qualcomm Atheros, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of Qualcomm Atheros nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "usb_defs.h" -#include "usb_type.h" -#include "usb_pre.h" -#include "usb_extr.h" -#include "usb_std.h" -#include "reg_defs.h" -#include "athos_api.h" -#include "usbfifo_api.h" - - -#include "sys_cfg.h" - -void _fw_usb_suspend_reboot(); - -extern Action eUsbCxFinishAction; -extern CommandType eUsbCxCommand; -extern BOOLEAN UsbChirpFinish; -extern USB_FIFO_CONFIG usbFifoConf; - -#if SYSTEM_MODULE_USB -#define vUsb_ep0end(void) \ -{ \ - eUsbCxCommand = CMD_VOID; \ - USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01); \ -} - -#define vUsb_ep0fail(void) USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04) - -#define vUsb_rst() \ -{ \ - USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \ - (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT1)); \ - UsbChirpFinish = FALSE; \ -} - -#define vUsb_suspend() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \ - (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT2)) - -#define vUsb_resm() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \ - (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT3)) - -#define CHECK_SOF_LOOP_CNT 50 - -void _fw_usb_suspend_reboot() -{ - volatile uint32_t gpio_in = 0; - volatile uint32_t pupd = 0; - volatile uint32_t t = 0; - volatile uint32_t sof_no=0,sof_no_new=0; - /* Set GO_TO_SUSPEND bit to USB main control register */ - vUsb_suspend(); - A_PRINTF("!USB suspend\n\r"); - - // keep the record of suspend -#if defined(PROJECT_MAGPIE) - *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) = SUS_MAGIC_PATTERN; -#elif defined(PROJECT_K2) - HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN); -#endif /* #if defined(PROJECT_MAGPIE) */ - - /* Reset USB FIFO */ - A_USB_RESET_FIFO(); - - /* Turn off power */ - A_USB_POWER_OFF(); - - DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1000; - - // reset ep3/ep4 fifo in case there is data which might affect resuming -// HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10)); -// HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100af)|0x10)); - - { - // config gpio to input before goto suspend - - //disable JTAG/ICE - //jtag = HAL_WORD_REG_READ(0x10004054); - //HAL_WORD_REG_WRITE(0x10004054, (jtag|BIT17)); - - //disable SPI - //spi = HAL_WORD_REG_READ(0x50040); - //HAL_WORD_REG_WRITE(0x50040, (spi&~(BIT8))); - - //set all GPIO to input - gpio_in = HAL_WORD_REG_READ(0x1000404c); - HAL_WORD_REG_WRITE(0x1000404c, 0x0); - - //set PU/PD for all GPIO except two UART pins - pupd = HAL_WORD_REG_READ(0x10004088); - HAL_WORD_REG_WRITE(0x10004088, 0xA982AA6A); - } - - sof_no= HAL_WORD_REG_READ(0x10004); - for (t = 0; t < CHECK_SOF_LOOP_CNT; t++) - { - A_DELAY_USECS(1000); //delay 1ms - sof_no_new = HAL_WORD_REG_READ(0x10004); - - if(sof_no_new == sof_no) - break; - - sof_no = sof_no_new; - } - - /* - * Reset "printf" module patch point(RAM to ROM) when K2 warm start or suspend, - * which fixed the error issue cause by redownload another different firmware. - */ - _indir_tbl.cmnos.printf._printf = save_cmnos_printf; - - /////////////////////////////////////////////////////////////// - // setting the go suspend here, power down right away... - if (t != CHECK_SOF_LOOP_CNT) // not time out - HAL_WORD_REG_WRITE(0x10000, HAL_WORD_REG_READ(0x10000)|(0x8)); - /////////////////////////////////////////////////////////////// - - DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1100; - -#if 0 // pll unstable, h/w bug? - HAL_WORD_REG_WRITE(0x50040, (0x300|6|(1>>1)<<12)); - A_UART_HWINIT((40*1000*1000)/1, 19200); -#endif - { - // restore gpio setting - //HAL_WORD_REG_WRITE(0x10004054, jtag); - //HAL_WORD_REG_WRITE(0x50040, spi); - HAL_WORD_REG_WRITE(0x1000404c, gpio_in); - HAL_WORD_REG_WRITE(0x10004088, pupd); - } - DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1200; - - { - // since we still need to touch mac_base address after resuming back, so that - // reset mac can't be done in ResetFifo function, move to here... - // whole mac control reset.... (bit1) - HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (BIT1) ); - HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT0)); - HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 ); - A_DELAY_USECS(1000); - } - - //A_PRINTF("reg(0x10020)=(%x)\n", HAL_WORD_REG_READ(0x10020)); - // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!! - mUSB_STATUS_IN_INT_DISABLE(); - - MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1; - MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1; - MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1; - MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1; - - if (((DEBUG_SYSTEM_STATE&~(0x0000ffff))>>16 == 0x5342)) { - /* UART_SEL and SPI_SEL */ - HAL_WORD_REG_WRITE(0x50040, (0x300|0|(1>>1)<<12)); - } - - /* Jump to boot code */ - A_USB_JUMP_BOOT(); - -} - -/* - * -- patch usb_fw_task -- - * . usb zero length interrupt should not clear by s/w, h/w will handle that - * . complete suspend handle, configure gpio, turn off related function, - * slow down the pll for stable issue - */ -void _fw_usb_fw_task(void) -{ - register uint8_t usb_interrupt_level1; - register uint8_t usb_interrupt_level2; - - usb_interrupt_level1 = USB_BYTE_REG_READ(ZM_INTR_GROUP_OFFSET); -#if 0 // these endpoints are handled by DMA - if (usb_interrupt_level1 & BIT5) //Group Byte 5 - { - vUsb_Data_In(); - } -#endif - if (usb_interrupt_level1 & BIT4) - { - usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_4_OFFSET); - if( usb_interrupt_level2 & BIT6) - A_USB_REG_OUT();//vUsb_Reg_Out(); - } - - if (usb_interrupt_level1 & BIT6) - { - //zfGenWatchDogEvent(); - usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_6_OFFSET); - if( usb_interrupt_level2 & BIT6) - A_USB_STATUS_IN();//vUsb_Status_In(); - } - - if (usb_interrupt_level1 & BIT0) //Group Byte 0 - { - //usb_interrupt_level2 = ZM_INTR_SOURCE_0_REG; - usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET); - - // refer to FUSB200, p 48, offset:21H, bit7 description, should clear the command abort interrupt first!? - if (usb_interrupt_level2 & BIT7) - { - //ZM_INTR_SOURCE_0_REG &= 0x7f; // Handle command abort - USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_0_OFFSET, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET)& ~BIT7)); - A_PRINTF("![SOURCE_0] bit7 on\n\r"); - } - - if (usb_interrupt_level2 & BIT1) - { - //A_PRINTF("![USB] ep0 IN in \n\r"); - A_USB_EP0_TX(); // USB EP0 tx interrupt - } - if (usb_interrupt_level2 & BIT2) - { - //A_PRINTF("![USB] ep0 OUT in\n\r"); - A_USB_EP0_RX(); // USB EP0 rx interrupt - } - if (usb_interrupt_level2 & BIT0) - { - //A_PRINTF("![USB] ep0 SETUP in\n\r"); - A_USB_EP0_SETUP(); - //vWriteUSBFakeData(); - } -// else if (usb_interrupt_level2 & BIT3) - if (usb_interrupt_level2 & BIT3) - { - vUsb_ep0end(); -// A_PRINTF("![SOURCE_0] ep0 CMD_END\n\r"); - } - if (usb_interrupt_level2 & BIT4) - { - vUsb_ep0fail(); -// A_PRINTF("![SOURCE_0] ep0 CMD_FAIL\n\r"); - } - if (eUsbCxFinishAction == ACT_STALL) - { - // set CX_STL to stall Endpoint0 & will also clear FIFO0 - USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04); -// A_PRINTF("![USB] ZM_CX_CONFIG_STATUS_REG = 0x04\n\r"); - } - else if (eUsbCxFinishAction == ACT_DONE) - { - // set CX_DONE to indicate the transmistion of control frame - USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01); - } - eUsbCxFinishAction = ACT_IDLE; - } - - if (usb_interrupt_level1 & BIT7) //Group Byte 7 - { - //usb_interrupt_level2 = ZM_INTR_SOURCE_7_REG; - usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET); - -#if 0 - if (usb_interrupt_level2 & BIT7) - { - vUsb_Data_Out0Byte(); -// A_PRINTF("![SOURCE_7] bit7 on, clear it\n\r"); - } - if (usb_interrupt_level2 & BIT6) - { - vUsb_Data_In0Byte(); -// A_PRINTF("![SOURCE_7] bit6 on, clear it\n\r"); - } -#endif - - if (usb_interrupt_level2 & BIT1) - { - vUsb_rst(); - //USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~0x2)); - A_PRINTF("!USB reset\n\r"); -// A_PRINTF("![0x1012c]: %\n\r", USB_WORD_REG_READ(0x12c)); - } - if (usb_interrupt_level2 & BIT2) - { - // TBD: the suspend resume code should put here, Ryan, 07/18 - // - // issue, jump back to rom code and what peripherals should we reset here? - // - _fw_usb_suspend_reboot(); - } - if (usb_interrupt_level2 & BIT3) - { - vUsb_resm(); - A_PRINTF("!USB resume\n\r"); - } - } - -} - - -void _fw_usb_reset_fifo(void) -{ - volatile uint32_t *reg_data; - - HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10)); - HAL_BYTE_REG_WRITE(0x100af, (HAL_BYTE_REG_READ(0x100af)|0x10)); - - // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!! - mUSB_STATUS_IN_INT_DISABLE(); - - // update magic pattern to indicate this is a suspend - // k2: MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR - // magpie: MAGPIE_REG_RST_STATUS_ADDR - HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN); - - /* - * Before USB suspend, USB DMA must be reset(refer to Otus) - * Otus runs the following statements only - * HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, BIT0|BIT2 ); - * HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 ); - * K2 must run the following statements additionally - * reg_data = (A_UINT32 *)(USB_CTRL_BASE_ADDRESS + 0x118); - * *reg_data = 0x00000000; - * *reg_data = 0x00000001; - * because of Hardware bug in K2 - */ - reg_data = (uint32_t *)(USB_CTRL_BASE_ADDRESS + 0x118); - *reg_data = 0x00000000; - - // reset both usb(bit2)/wlan(bit1) dma - HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (BIT2) ); - HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT0)); - HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 ); - - *reg_data = 0x00000001; - - /* MAC warem reset */ - //reg_data = (uint32_t *)(K2_REG_MAC_BASE_ADDR + 0x7000); - //*reg_data = 0x00000001; - - //A_DELAY_USECS(1); - - //*reg_data = 0x00000000; - - //while (*reg_data) ; - - A_PRINTF("\n change clock to 22 and go to suspend now!"); - - /* UART_SEL */ - HAL_WORD_REG_WRITE(0x50040, (0x200|0|(1>>1)<<12)); - A_UART_HWINIT((22*1000*1000), 19200); -} -#endif diff --git a/target_firmware/magpie_fw_dev/target/hif/usb_api_k2_patch.c b/target_firmware/magpie_fw_dev/target/hif/usb_api_k2_patch.c new file mode 100755 index 0000000..bc6948d --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/hif/usb_api_k2_patch.c @@ -0,0 +1,377 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "usb_defs.h" +#include "usb_type.h" +#include "usb_pre.h" +#include "usb_extr.h" +#include "usb_std.h" +#include "reg_defs.h" +#include "athos_api.h" +#include "usbfifo_api.h" + + +#include "sys_cfg.h" + +void _fw_usb_suspend_reboot(); + +extern Action eUsbCxFinishAction; +extern CommandType eUsbCxCommand; +extern BOOLEAN UsbChirpFinish; +extern USB_FIFO_CONFIG usbFifoConf; + +#if SYSTEM_MODULE_USB +#define vUsb_ep0end(void) \ +{ \ + eUsbCxCommand = CMD_VOID; \ + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01); \ +} + +#define vUsb_ep0fail(void) USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04) + +#define vUsb_rst() \ +{ \ + USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \ + (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT1)); \ + UsbChirpFinish = FALSE; \ +} + +#define vUsb_suspend() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \ + (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT2)) + +#define vUsb_resm() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \ + (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT3)) + +#define CHECK_SOF_LOOP_CNT 50 + +void _fw_usb_suspend_reboot() +{ + volatile uint32_t gpio_in = 0; + volatile uint32_t pupd = 0; + volatile uint32_t t = 0; + volatile uint32_t sof_no=0,sof_no_new=0; + /* Set GO_TO_SUSPEND bit to USB main control register */ + vUsb_suspend(); + A_PRINTF("!USB suspend\n\r"); + + // keep the record of suspend +#if defined(PROJECT_MAGPIE) + *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) = SUS_MAGIC_PATTERN; +#elif defined(PROJECT_K2) + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN); +#endif /* #if defined(PROJECT_MAGPIE) */ + + /* Reset USB FIFO */ + A_USB_RESET_FIFO(); + + /* Turn off power */ + A_USB_POWER_OFF(); + + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1000; + + // reset ep3/ep4 fifo in case there is data which might affect resuming +// HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10)); +// HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100af)|0x10)); + + { + // config gpio to input before goto suspend + + //disable JTAG/ICE + //jtag = HAL_WORD_REG_READ(0x10004054); + //HAL_WORD_REG_WRITE(0x10004054, (jtag|BIT17)); + + //disable SPI + //spi = HAL_WORD_REG_READ(0x50040); + //HAL_WORD_REG_WRITE(0x50040, (spi&~(BIT8))); + + //set all GPIO to input + gpio_in = HAL_WORD_REG_READ(0x1000404c); + HAL_WORD_REG_WRITE(0x1000404c, 0x0); + + //set PU/PD for all GPIO except two UART pins + pupd = HAL_WORD_REG_READ(0x10004088); + HAL_WORD_REG_WRITE(0x10004088, 0xA982AA6A); + } + + sof_no= HAL_WORD_REG_READ(0x10004); + for (t = 0; t < CHECK_SOF_LOOP_CNT; t++) + { + A_DELAY_USECS(1000); //delay 1ms + sof_no_new = HAL_WORD_REG_READ(0x10004); + + if(sof_no_new == sof_no) + break; + + sof_no = sof_no_new; + } + + /* + * Reset "printf" module patch point(RAM to ROM) when K2 warm start or suspend, + * which fixed the error issue cause by redownload another different firmware. + */ + _indir_tbl.cmnos.printf._printf = save_cmnos_printf; + + /////////////////////////////////////////////////////////////// + // setting the go suspend here, power down right away... + if (t != CHECK_SOF_LOOP_CNT) // not time out + HAL_WORD_REG_WRITE(0x10000, HAL_WORD_REG_READ(0x10000)|(0x8)); + /////////////////////////////////////////////////////////////// + + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1100; + +#if 0 // pll unstable, h/w bug? + HAL_WORD_REG_WRITE(0x50040, (0x300|6|(1>>1)<<12)); + A_UART_HWINIT((40*1000*1000)/1, 19200); +#endif + { + // restore gpio setting + //HAL_WORD_REG_WRITE(0x10004054, jtag); + //HAL_WORD_REG_WRITE(0x50040, spi); + HAL_WORD_REG_WRITE(0x1000404c, gpio_in); + HAL_WORD_REG_WRITE(0x10004088, pupd); + } + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1200; + + { + // since we still need to touch mac_base address after resuming back, so that + // reset mac can't be done in ResetFifo function, move to here... + // whole mac control reset.... (bit1) + HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (BIT1) ); + HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT0)); + HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 ); + A_DELAY_USECS(1000); + } + + //A_PRINTF("reg(0x10020)=(%x)\n", HAL_WORD_REG_READ(0x10020)); + // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!! + mUSB_STATUS_IN_INT_DISABLE(); + + MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1; + MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1; + MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1; + MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1; + + if (((DEBUG_SYSTEM_STATE&~(0x0000ffff))>>16 == 0x5342)) { + /* UART_SEL and SPI_SEL */ + HAL_WORD_REG_WRITE(0x50040, (0x300|0|(1>>1)<<12)); + } + + /* Jump to boot code */ + A_USB_JUMP_BOOT(); + +} + +/* + * -- patch usb_fw_task -- + * . usb zero length interrupt should not clear by s/w, h/w will handle that + * . complete suspend handle, configure gpio, turn off related function, + * slow down the pll for stable issue + */ +void _fw_usb_fw_task(void) +{ + register uint8_t usb_interrupt_level1; + register uint8_t usb_interrupt_level2; + + usb_interrupt_level1 = USB_BYTE_REG_READ(ZM_INTR_GROUP_OFFSET); +#if 0 // these endpoints are handled by DMA + if (usb_interrupt_level1 & BIT5) //Group Byte 5 + { + vUsb_Data_In(); + } +#endif + if (usb_interrupt_level1 & BIT4) + { + usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_4_OFFSET); + if( usb_interrupt_level2 & BIT6) + A_USB_REG_OUT();//vUsb_Reg_Out(); + } + + if (usb_interrupt_level1 & BIT6) + { + //zfGenWatchDogEvent(); + usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_6_OFFSET); + if( usb_interrupt_level2 & BIT6) + A_USB_STATUS_IN();//vUsb_Status_In(); + } + + if (usb_interrupt_level1 & BIT0) //Group Byte 0 + { + //usb_interrupt_level2 = ZM_INTR_SOURCE_0_REG; + usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET); + + // refer to FUSB200, p 48, offset:21H, bit7 description, should clear the command abort interrupt first!? + if (usb_interrupt_level2 & BIT7) + { + //ZM_INTR_SOURCE_0_REG &= 0x7f; // Handle command abort + USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_0_OFFSET, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET)& ~BIT7)); + A_PRINTF("![SOURCE_0] bit7 on\n\r"); + } + + if (usb_interrupt_level2 & BIT1) + { + //A_PRINTF("![USB] ep0 IN in \n\r"); + A_USB_EP0_TX(); // USB EP0 tx interrupt + } + if (usb_interrupt_level2 & BIT2) + { + //A_PRINTF("![USB] ep0 OUT in\n\r"); + A_USB_EP0_RX(); // USB EP0 rx interrupt + } + if (usb_interrupt_level2 & BIT0) + { + //A_PRINTF("![USB] ep0 SETUP in\n\r"); + A_USB_EP0_SETUP(); + //vWriteUSBFakeData(); + } +// else if (usb_interrupt_level2 & BIT3) + if (usb_interrupt_level2 & BIT3) + { + vUsb_ep0end(); +// A_PRINTF("![SOURCE_0] ep0 CMD_END\n\r"); + } + if (usb_interrupt_level2 & BIT4) + { + vUsb_ep0fail(); +// A_PRINTF("![SOURCE_0] ep0 CMD_FAIL\n\r"); + } + if (eUsbCxFinishAction == ACT_STALL) + { + // set CX_STL to stall Endpoint0 & will also clear FIFO0 + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04); +// A_PRINTF("![USB] ZM_CX_CONFIG_STATUS_REG = 0x04\n\r"); + } + else if (eUsbCxFinishAction == ACT_DONE) + { + // set CX_DONE to indicate the transmistion of control frame + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01); + } + eUsbCxFinishAction = ACT_IDLE; + } + + if (usb_interrupt_level1 & BIT7) //Group Byte 7 + { + //usb_interrupt_level2 = ZM_INTR_SOURCE_7_REG; + usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET); + +#if 0 + if (usb_interrupt_level2 & BIT7) + { + vUsb_Data_Out0Byte(); +// A_PRINTF("![SOURCE_7] bit7 on, clear it\n\r"); + } + if (usb_interrupt_level2 & BIT6) + { + vUsb_Data_In0Byte(); +// A_PRINTF("![SOURCE_7] bit6 on, clear it\n\r"); + } +#endif + + if (usb_interrupt_level2 & BIT1) + { + vUsb_rst(); + //USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~0x2)); + A_PRINTF("!USB reset\n\r"); +// A_PRINTF("![0x1012c]: %\n\r", USB_WORD_REG_READ(0x12c)); + } + if (usb_interrupt_level2 & BIT2) + { + // TBD: the suspend resume code should put here, Ryan, 07/18 + // + // issue, jump back to rom code and what peripherals should we reset here? + // + _fw_usb_suspend_reboot(); + } + if (usb_interrupt_level2 & BIT3) + { + vUsb_resm(); + A_PRINTF("!USB resume\n\r"); + } + } + +} + + +void _fw_usb_reset_fifo(void) +{ + volatile uint32_t *reg_data; + + HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10)); + HAL_BYTE_REG_WRITE(0x100af, (HAL_BYTE_REG_READ(0x100af)|0x10)); + + // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!! + mUSB_STATUS_IN_INT_DISABLE(); + + // update magic pattern to indicate this is a suspend + // k2: MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR + // magpie: MAGPIE_REG_RST_STATUS_ADDR + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN); + + /* + * Before USB suspend, USB DMA must be reset(refer to Otus) + * Otus runs the following statements only + * HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, BIT0|BIT2 ); + * HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 ); + * K2 must run the following statements additionally + * reg_data = (A_UINT32 *)(USB_CTRL_BASE_ADDRESS + 0x118); + * *reg_data = 0x00000000; + * *reg_data = 0x00000001; + * because of Hardware bug in K2 + */ + reg_data = (uint32_t *)(USB_CTRL_BASE_ADDRESS + 0x118); + *reg_data = 0x00000000; + + // reset both usb(bit2)/wlan(bit1) dma + HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (BIT2) ); + HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT0)); + HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 ); + + *reg_data = 0x00000001; + + /* MAC warem reset */ + //reg_data = (uint32_t *)(K2_REG_MAC_BASE_ADDR + 0x7000); + //*reg_data = 0x00000001; + + //A_DELAY_USECS(1); + + //*reg_data = 0x00000000; + + //while (*reg_data) ; + + A_PRINTF("\n change clock to 22 and go to suspend now!"); + + /* UART_SEL */ + HAL_WORD_REG_WRITE(0x50040, (0x200|0|(1>>1)<<12)); + A_UART_HWINIT((22*1000*1000), 19200); +} +#endif diff --git a/target_firmware/magpie_fw_dev/target/hif/usb_api_magpie_patch.c b/target_firmware/magpie_fw_dev/target/hif/usb_api_magpie_patch.c new file mode 100755 index 0000000..52c692e --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/hif/usb_api_magpie_patch.c @@ -0,0 +1,418 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "usb_defs.h" +#include "usb_type.h" +#include "usb_pre.h" +#include "usb_extr.h" +#include "usb_std.h" +#include "reg_defs.h" +#include "athos_api.h" +#include "usbfifo_api.h" + +#include "sys_cfg.h" + +#define measure_time 0 +#define measure_time_pll 10000000 + +extern Action eUsbCxFinishAction; +extern CommandType eUsbCxCommand; +extern BOOLEAN UsbChirpFinish; +extern USB_FIFO_CONFIG usbFifoConf; +extern uint16_t *pu8DescriptorEX; +extern uint16_t u16TxRxCounter; + +void zfTurnOffPower_patch(void); + +static void _fw_reset_dma_fifo(); +static void _fw_restore_dma_fifo(); +static void _fw_power_on(); +static void _fw_power_off(); + +BOOLEAN bEepromExist = TRUE; +BOOLEAN bJumptoFlash = FALSE; + +void _fw_usb_suspend_reboot() +{ + /* reset usb/wlan dma */ + _fw_reset_dma_fifo(); + + /* restore gpio setting and usb/wlan dma state */ + _fw_restore_dma_fifo(); + + /* set clock to bypass mode - 40Mhz from XTAL */ + HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4)); + + A_DELAY_USECS(100); /* wait for stable */ + + HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, (BIT16)); + + A_DELAY_USECS(100); /* wait for stable */ + A_UART_HWINIT((40*1000*1000), 19200); + + A_CLOCK_INIT(40); + + if (!bEepromExist) { /* jump to flash boot (eeprom data in flash) */ + bJumptoFlash = TRUE; + A_PRINTF("Jump to Flash BOOT\n"); + app_start(); + } else { + A_PRINTF("receive the suspend command...\n"); + /* reboot..... */ + A_USB_JUMP_BOOT(); + } + +} + +#define PCI_RC_RESET_BIT BIT6 +#define PCI_RC_PHY_RESET_BIT BIT7 +#define PCI_RC_PLL_RESET_BIT BIT8 +#define PCI_RC_PHY_SHIFT_RESET_BIT BIT10 + +/* + * -- urn_off_merlin -- + * . values suggested from Lalit + * + */ +static void turn_off_merlin() +{ + volatile uint32_t default_data[9]; + uint32_t i=0; + + if(1) + { + A_PRINTF("turn_off_merlin_ep_start ......\n"); + A_DELAY_USECS(measure_time); + default_data[0] = 0x9248fd00; + default_data[1] = 0x24924924; + default_data[2] = 0xa8000019; + default_data[3] = 0x17160820; + default_data[4] = 0x25980560; + default_data[5] = 0xc1c00000; + default_data[6] = 0x1aaabe40; + default_data[7] = 0xbe105554; + default_data[8] = 0x00043007; + + for(i=0; i<9; i++) + { + A_DELAY_USECS(10); + + HAL_WORD_REG_WRITE( 0x10ff4040, default_data[i]); + } + A_DELAY_USECS(10); + HAL_WORD_REG_WRITE(0x10ff4044, BIT0); + A_PRINTF("turn_off_merlin_ep_end ......\n"); + } +} + +/* + * -- turn_off_phy -- + * + * . write shift register to both pcie ep and rc + * . + */ + +static void turn_off_phy() +{ + + volatile uint32_t default_data[9]; + volatile uint32_t read_data = 0; + uint32_t i=0; + + default_data[0] = 0x9248fd00; + default_data[1] = 0x24924924; + default_data[2] = 0xa8000019; + default_data[3] = 0x17160820; + default_data[4] = 0x25980560; + default_data[5] = 0xc1c00000; + default_data[6] = 0x1aaabe40; + default_data[7] = 0xbe105554; + default_data[8] = 0x00043007; + + for(i=0; i<9; i++) + { + // check for the done bit to be set + + while (1) + { + read_data=HAL_WORD_REG_READ(0x40028); + if( read_data & BIT31 ) + break; + } + + A_DELAY_USECS(1); + + HAL_WORD_REG_WRITE( 0x40024, default_data[i]); + } + HAL_WORD_REG_WRITE(0x40028, BIT0); +} + +static void turn_off_phy_rc() +{ + + volatile uint32_t default_data[9]; + volatile uint32_t read_data = 0; + uint32_t i=0; + + A_PRINTF("turn_off_phy_rc\n"); + + default_data[0] = 0x9248fd00; + default_data[1] = 0x24924924; + default_data[2] = 0xa8000019; + default_data[3] = 0x13160820;//PwdClk1MHz=0 + default_data[4] = 0x25980560; + default_data[5] = 0xc1c00000; + default_data[6] = 0x1aaabe40; + default_data[7] = 0xbe105554; + default_data[8] = 0x00043007; + + for(i=0; i<9; i++) + { + // check for the done bit to be set + + while (1) + { + read_data=HAL_WORD_REG_READ(0x40028); + if( read_data & BIT31 ) + break; + } + + A_DELAY_USECS(1); + + HAL_WORD_REG_WRITE( 0x40024, default_data[i]); + } + HAL_WORD_REG_WRITE(0x40028, BIT0); +} + +volatile uint32_t gpio_func = 0x0; +volatile uint32_t gpio = 0x0; + +/* + * -- patch zfTurnOffPower -- + * + * . set suspend counter to non-zero value + * . + */ +void zfTurnOffPower_patch(void) +{ + A_PRINTF("+++ goto suspend ......\n"); + + // setting the go suspend here, power down right away... + HAL_WORD_REG_WRITE(0x10000, HAL_WORD_REG_READ(0x10000)|(0x8)); + + A_DELAY_USECS(100); + + // TURN OFF ETH PLL + _fw_power_off(); + + //32clk wait for External ETH PLL stable + A_DELAY_USECS(100); + + HAL_WORD_REG_WRITE(0x52000, 0x70303);//read back 0x703f7 + HAL_WORD_REG_WRITE(0x52008, 0x0e91c);//read back 0x1e948 + + HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(BIT0))); //0x56030 + // wake up, and turn on cpu, eth, pcie and usb pll + _fw_power_on(); + // restore gpio and other settings + _fw_restore_dma_fifo(); + + // clear suspend.................. + HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)&(~BIT0))); + HAL_WORD_REG_WRITE(0x52028, HAL_WORD_REG_READ(0x52028)&(~(BIT8|BIT12|BIT16))); +} + +/* + * -- patch zfResetUSBFIFO_patch -- + * + * . clear ep3/ep4 fifo + * . set suspend magic pattern + * . reset pcie ep phy + * . reset pcie rc phy + * . turn off pcie pll + * . reset all pcie/gmac related registers + * . reset usb dma + */ +void zfResetUSBFIFO_patch(void) +{ + A_PRINTF("0x9808 0x%x ......\n", HAL_WORD_REG_READ(0x10ff9808)); + A_PRINTF("0x7890 0x%x ......\n", HAL_WORD_REG_READ(0x10ff7890)); + A_PRINTF("0x7890 0x%x ......\n", HAL_WORD_REG_READ(0x10ff7890)); + A_PRINTF("0x4088 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088)); + _fw_reset_dma_fifo(); +} + +static void _fw_reset_dma_fifo() +{ + HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10)); + HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100af)|0x10)); + A_PRINTF("_fw_reset_dma_fifo\n"); + + // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!! + mUSB_STATUS_IN_INT_DISABLE(); + + // update magic pattern to indicate this is a suspend + HAL_WORD_REG_WRITE(WATCH_DOG_MAGIC_PATTERN_ADDR, SUS_MAGIC_PATTERN); + + A_PRINTF("org 0x4048 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4048)); + A_PRINTF("org 0x404C 0x%x ......\n", HAL_WORD_REG_READ(0x10ff404C)); + A_PRINTF("org 0x4088 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088)); + + HAL_WORD_REG_WRITE(0x10ff4088,0xaaa6a);//1010.1010.1010.0110.1010 for UB94 + HAL_WORD_REG_WRITE(0x10ff404C,0x0); + + A_DELAY_USECS(1000); + A_PRINTF("0x4048 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4048)); + A_PRINTF("0x404C 0x%x ......\n", HAL_WORD_REG_READ(0x10ff404C)); + A_PRINTF("0x4088 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088)); + + // turn off merlin + turn_off_merlin(); + // pcie ep + A_PRINTF("turn_off_magpie_ep_start ......\n"); + A_DELAY_USECS(measure_time); + HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)|BIT0|(1<<1))); + turn_off_phy(); + HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)&~(BIT0|(1<<1)))); + A_PRINTF("turn_off_magpie_ep_end ......\n"); + + // pcie rc + A_PRINTF("turn_off_magpie_rc_start ......\n"); + A_DELAY_USECS(measure_time); + HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)&(~BIT0))); + turn_off_phy_rc(); + A_PRINTF("turn_off_magpie_rc_end ......down\n"); + A_DELAY_USECS(measure_time); + + A_PRINTF("0x4001C %p ......\n", HAL_WORD_REG_READ(0x4001c)); + A_PRINTF("0x40040 %p ......\n", HAL_WORD_REG_READ(0x40040)); + + // turn off pcie_pll - power down (bit16) + A_PRINTF(" before pwd PCIE PLL CFG:0x5601C %p ......\n", HAL_WORD_REG_READ(0x5601C)); + HAL_WORD_REG_WRITE(0x5601C, (HAL_WORD_REG_READ(0x5601C)|(BIT18))); + A_PRINTF(" after pwd PCIE PLL CFG:0x5601C %p ......\n", HAL_WORD_REG_READ(0x5601C)); + + /* set everything to reset state?, requested by Oligo */ + HAL_WORD_REG_WRITE(0x50010, HAL_WORD_REG_READ(0x50010)|(BIT13|BIT12|BIT11|BIT9|BIT7|BIT6)); + + HAL_WORD_REG_WRITE(0x5C000, 0); + + A_DELAY_USECS(10); + + // reset usb DMA controller + HAL_WORD_REG_WRITE((USB_CTRL_BASE_ADDRESS+0x118), 0x0); + + HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)|(BIT4))); + A_DELAY_USECS(5); + HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)&(~BIT4))); + + + HAL_WORD_REG_WRITE((USB_CTRL_BASE_ADDRESS+0x118), 0x1); +} + +static void _fw_power_off() +{ + /* + * 1. set CPU bypass + * 2. turn off CPU PLL + * 3. turn off ETH PLL + * 4. disable ETH PLL bypass and update + * 4.1 set suspend timeout + * 5. set SUSPEND_ENABLE + */ + + HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4)); //0x56004 + + A_DELAY_USECS(100); // wait for stable + + HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, (BIT16));//0x56000 + + A_DELAY_USECS(100); // wait for stable + + A_UART_HWINIT((40*1000*1000), 19200); + A_CLOCK_INIT(40); + + HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)|(BIT16))); //0x5600c + + HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)|(BIT4|BIT0))); //0x56010 + + HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(0x10<<8))); //0x56030 +} + +static void _fw_power_on() +{ + /* + * 1. turn on CPU PLL + * 2. disable CPU bypass + * 3. turn on ETH PLL + * 4. disable ETH PLL bypass and update + * 5. turn on pcie pll + */ + + HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)&(~BIT16))); + + // deassert eth_pll bypass mode and trigger update bit + HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)&(~(BIT4|BIT0)))); +} + +#define CMD_PCI_RC_RESET_ON() HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \ + (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)| \ + (PCI_RC_PHY_SHIFT_RESET_BIT|PCI_RC_PLL_RESET_BIT|PCI_RC_PHY_RESET_BIT|PCI_RC_RESET_BIT))) + +static void _fw_restore_dma_fifo(void) +{ + HAL_WORD_REG_WRITE(0x5601C, (HAL_WORD_REG_READ(0x5601C)&(~(BIT18)))); + + // reset pcie_rc shift + HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)&(~(BIT10|BIT8|BIT7)))); + A_DELAY_USECS(1); + HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)|(BIT10|BIT8|BIT7))); + + // reset pci_rc phy + CMD_PCI_RC_RESET_ON(); + A_DELAY_USECS(20); + + // enable dma swap function + MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1; + MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1; + MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1; + MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1; +} diff --git a/target_firmware/magpie_fw_dev/target/rompatch/usb_api_patch.c b/target_firmware/magpie_fw_dev/target/rompatch/usb_api_patch.c deleted file mode 100755 index 52c692e..0000000 --- a/target_firmware/magpie_fw_dev/target/rompatch/usb_api_patch.c +++ /dev/null @@ -1,418 +0,0 @@ -/* - * Copyright (c) 2013 Qualcomm Atheros, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of Qualcomm Atheros nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "usb_defs.h" -#include "usb_type.h" -#include "usb_pre.h" -#include "usb_extr.h" -#include "usb_std.h" -#include "reg_defs.h" -#include "athos_api.h" -#include "usbfifo_api.h" - -#include "sys_cfg.h" - -#define measure_time 0 -#define measure_time_pll 10000000 - -extern Action eUsbCxFinishAction; -extern CommandType eUsbCxCommand; -extern BOOLEAN UsbChirpFinish; -extern USB_FIFO_CONFIG usbFifoConf; -extern uint16_t *pu8DescriptorEX; -extern uint16_t u16TxRxCounter; - -void zfTurnOffPower_patch(void); - -static void _fw_reset_dma_fifo(); -static void _fw_restore_dma_fifo(); -static void _fw_power_on(); -static void _fw_power_off(); - -BOOLEAN bEepromExist = TRUE; -BOOLEAN bJumptoFlash = FALSE; - -void _fw_usb_suspend_reboot() -{ - /* reset usb/wlan dma */ - _fw_reset_dma_fifo(); - - /* restore gpio setting and usb/wlan dma state */ - _fw_restore_dma_fifo(); - - /* set clock to bypass mode - 40Mhz from XTAL */ - HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4)); - - A_DELAY_USECS(100); /* wait for stable */ - - HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, (BIT16)); - - A_DELAY_USECS(100); /* wait for stable */ - A_UART_HWINIT((40*1000*1000), 19200); - - A_CLOCK_INIT(40); - - if (!bEepromExist) { /* jump to flash boot (eeprom data in flash) */ - bJumptoFlash = TRUE; - A_PRINTF("Jump to Flash BOOT\n"); - app_start(); - } else { - A_PRINTF("receive the suspend command...\n"); - /* reboot..... */ - A_USB_JUMP_BOOT(); - } - -} - -#define PCI_RC_RESET_BIT BIT6 -#define PCI_RC_PHY_RESET_BIT BIT7 -#define PCI_RC_PLL_RESET_BIT BIT8 -#define PCI_RC_PHY_SHIFT_RESET_BIT BIT10 - -/* - * -- urn_off_merlin -- - * . values suggested from Lalit - * - */ -static void turn_off_merlin() -{ - volatile uint32_t default_data[9]; - uint32_t i=0; - - if(1) - { - A_PRINTF("turn_off_merlin_ep_start ......\n"); - A_DELAY_USECS(measure_time); - default_data[0] = 0x9248fd00; - default_data[1] = 0x24924924; - default_data[2] = 0xa8000019; - default_data[3] = 0x17160820; - default_data[4] = 0x25980560; - default_data[5] = 0xc1c00000; - default_data[6] = 0x1aaabe40; - default_data[7] = 0xbe105554; - default_data[8] = 0x00043007; - - for(i=0; i<9; i++) - { - A_DELAY_USECS(10); - - HAL_WORD_REG_WRITE( 0x10ff4040, default_data[i]); - } - A_DELAY_USECS(10); - HAL_WORD_REG_WRITE(0x10ff4044, BIT0); - A_PRINTF("turn_off_merlin_ep_end ......\n"); - } -} - -/* - * -- turn_off_phy -- - * - * . write shift register to both pcie ep and rc - * . - */ - -static void turn_off_phy() -{ - - volatile uint32_t default_data[9]; - volatile uint32_t read_data = 0; - uint32_t i=0; - - default_data[0] = 0x9248fd00; - default_data[1] = 0x24924924; - default_data[2] = 0xa8000019; - default_data[3] = 0x17160820; - default_data[4] = 0x25980560; - default_data[5] = 0xc1c00000; - default_data[6] = 0x1aaabe40; - default_data[7] = 0xbe105554; - default_data[8] = 0x00043007; - - for(i=0; i<9; i++) - { - // check for the done bit to be set - - while (1) - { - read_data=HAL_WORD_REG_READ(0x40028); - if( read_data & BIT31 ) - break; - } - - A_DELAY_USECS(1); - - HAL_WORD_REG_WRITE( 0x40024, default_data[i]); - } - HAL_WORD_REG_WRITE(0x40028, BIT0); -} - -static void turn_off_phy_rc() -{ - - volatile uint32_t default_data[9]; - volatile uint32_t read_data = 0; - uint32_t i=0; - - A_PRINTF("turn_off_phy_rc\n"); - - default_data[0] = 0x9248fd00; - default_data[1] = 0x24924924; - default_data[2] = 0xa8000019; - default_data[3] = 0x13160820;//PwdClk1MHz=0 - default_data[4] = 0x25980560; - default_data[5] = 0xc1c00000; - default_data[6] = 0x1aaabe40; - default_data[7] = 0xbe105554; - default_data[8] = 0x00043007; - - for(i=0; i<9; i++) - { - // check for the done bit to be set - - while (1) - { - read_data=HAL_WORD_REG_READ(0x40028); - if( read_data & BIT31 ) - break; - } - - A_DELAY_USECS(1); - - HAL_WORD_REG_WRITE( 0x40024, default_data[i]); - } - HAL_WORD_REG_WRITE(0x40028, BIT0); -} - -volatile uint32_t gpio_func = 0x0; -volatile uint32_t gpio = 0x0; - -/* - * -- patch zfTurnOffPower -- - * - * . set suspend counter to non-zero value - * . - */ -void zfTurnOffPower_patch(void) -{ - A_PRINTF("+++ goto suspend ......\n"); - - // setting the go suspend here, power down right away... - HAL_WORD_REG_WRITE(0x10000, HAL_WORD_REG_READ(0x10000)|(0x8)); - - A_DELAY_USECS(100); - - // TURN OFF ETH PLL - _fw_power_off(); - - //32clk wait for External ETH PLL stable - A_DELAY_USECS(100); - - HAL_WORD_REG_WRITE(0x52000, 0x70303);//read back 0x703f7 - HAL_WORD_REG_WRITE(0x52008, 0x0e91c);//read back 0x1e948 - - HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR, - (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(BIT0))); //0x56030 - // wake up, and turn on cpu, eth, pcie and usb pll - _fw_power_on(); - // restore gpio and other settings - _fw_restore_dma_fifo(); - - // clear suspend.................. - HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR, - (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)&(~BIT0))); - HAL_WORD_REG_WRITE(0x52028, HAL_WORD_REG_READ(0x52028)&(~(BIT8|BIT12|BIT16))); -} - -/* - * -- patch zfResetUSBFIFO_patch -- - * - * . clear ep3/ep4 fifo - * . set suspend magic pattern - * . reset pcie ep phy - * . reset pcie rc phy - * . turn off pcie pll - * . reset all pcie/gmac related registers - * . reset usb dma - */ -void zfResetUSBFIFO_patch(void) -{ - A_PRINTF("0x9808 0x%x ......\n", HAL_WORD_REG_READ(0x10ff9808)); - A_PRINTF("0x7890 0x%x ......\n", HAL_WORD_REG_READ(0x10ff7890)); - A_PRINTF("0x7890 0x%x ......\n", HAL_WORD_REG_READ(0x10ff7890)); - A_PRINTF("0x4088 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088)); - _fw_reset_dma_fifo(); -} - -static void _fw_reset_dma_fifo() -{ - HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10)); - HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100af)|0x10)); - A_PRINTF("_fw_reset_dma_fifo\n"); - - // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!! - mUSB_STATUS_IN_INT_DISABLE(); - - // update magic pattern to indicate this is a suspend - HAL_WORD_REG_WRITE(WATCH_DOG_MAGIC_PATTERN_ADDR, SUS_MAGIC_PATTERN); - - A_PRINTF("org 0x4048 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4048)); - A_PRINTF("org 0x404C 0x%x ......\n", HAL_WORD_REG_READ(0x10ff404C)); - A_PRINTF("org 0x4088 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088)); - - HAL_WORD_REG_WRITE(0x10ff4088,0xaaa6a);//1010.1010.1010.0110.1010 for UB94 - HAL_WORD_REG_WRITE(0x10ff404C,0x0); - - A_DELAY_USECS(1000); - A_PRINTF("0x4048 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4048)); - A_PRINTF("0x404C 0x%x ......\n", HAL_WORD_REG_READ(0x10ff404C)); - A_PRINTF("0x4088 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088)); - - // turn off merlin - turn_off_merlin(); - // pcie ep - A_PRINTF("turn_off_magpie_ep_start ......\n"); - A_DELAY_USECS(measure_time); - HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)|BIT0|(1<<1))); - turn_off_phy(); - HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)&~(BIT0|(1<<1)))); - A_PRINTF("turn_off_magpie_ep_end ......\n"); - - // pcie rc - A_PRINTF("turn_off_magpie_rc_start ......\n"); - A_DELAY_USECS(measure_time); - HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)&(~BIT0))); - turn_off_phy_rc(); - A_PRINTF("turn_off_magpie_rc_end ......down\n"); - A_DELAY_USECS(measure_time); - - A_PRINTF("0x4001C %p ......\n", HAL_WORD_REG_READ(0x4001c)); - A_PRINTF("0x40040 %p ......\n", HAL_WORD_REG_READ(0x40040)); - - // turn off pcie_pll - power down (bit16) - A_PRINTF(" before pwd PCIE PLL CFG:0x5601C %p ......\n", HAL_WORD_REG_READ(0x5601C)); - HAL_WORD_REG_WRITE(0x5601C, (HAL_WORD_REG_READ(0x5601C)|(BIT18))); - A_PRINTF(" after pwd PCIE PLL CFG:0x5601C %p ......\n", HAL_WORD_REG_READ(0x5601C)); - - /* set everything to reset state?, requested by Oligo */ - HAL_WORD_REG_WRITE(0x50010, HAL_WORD_REG_READ(0x50010)|(BIT13|BIT12|BIT11|BIT9|BIT7|BIT6)); - - HAL_WORD_REG_WRITE(0x5C000, 0); - - A_DELAY_USECS(10); - - // reset usb DMA controller - HAL_WORD_REG_WRITE((USB_CTRL_BASE_ADDRESS+0x118), 0x0); - - HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)|(BIT4))); - A_DELAY_USECS(5); - HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)&(~BIT4))); - - - HAL_WORD_REG_WRITE((USB_CTRL_BASE_ADDRESS+0x118), 0x1); -} - -static void _fw_power_off() -{ - /* - * 1. set CPU bypass - * 2. turn off CPU PLL - * 3. turn off ETH PLL - * 4. disable ETH PLL bypass and update - * 4.1 set suspend timeout - * 5. set SUSPEND_ENABLE - */ - - HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4)); //0x56004 - - A_DELAY_USECS(100); // wait for stable - - HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, (BIT16));//0x56000 - - A_DELAY_USECS(100); // wait for stable - - A_UART_HWINIT((40*1000*1000), 19200); - A_CLOCK_INIT(40); - - HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR, - (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)|(BIT16))); //0x5600c - - HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR, - (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)|(BIT4|BIT0))); //0x56010 - - HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR, - (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(0x10<<8))); //0x56030 -} - -static void _fw_power_on() -{ - /* - * 1. turn on CPU PLL - * 2. disable CPU bypass - * 3. turn on ETH PLL - * 4. disable ETH PLL bypass and update - * 5. turn on pcie pll - */ - - HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR, - (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)&(~BIT16))); - - // deassert eth_pll bypass mode and trigger update bit - HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR, - (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)&(~(BIT4|BIT0)))); -} - -#define CMD_PCI_RC_RESET_ON() HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \ - (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)| \ - (PCI_RC_PHY_SHIFT_RESET_BIT|PCI_RC_PLL_RESET_BIT|PCI_RC_PHY_RESET_BIT|PCI_RC_RESET_BIT))) - -static void _fw_restore_dma_fifo(void) -{ - HAL_WORD_REG_WRITE(0x5601C, (HAL_WORD_REG_READ(0x5601C)&(~(BIT18)))); - - // reset pcie_rc shift - HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)&(~(BIT10|BIT8|BIT7)))); - A_DELAY_USECS(1); - HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)|(BIT10|BIT8|BIT7))); - - // reset pci_rc phy - CMD_PCI_RC_RESET_ON(); - A_DELAY_USECS(20); - - // enable dma swap function - MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1; - MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1; - MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1; - MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1; -}