*/
static inline __inline bool is_after_msecs(const uint32_t t0, const uint32_t msecs)
{
- return ((get_clock_counter() - t0) / 1000) > (msecs * fw.ticks_per_msec);
+ return ((get_clock_counter() - t0) / 1000) > (msecs * fw.ticks_per_usec);
}
/*
{
uint32_t t1, t2, dt, wt;
- wt = msec * fw.ticks_per_msec;
+ wt = msec * fw.ticks_per_usec;
t1 = get_clock_counter();
while (1) {
while (1) {
t2 = get_clock_counter();
dt = (t2 - t1);
- if (dt >= (usec * fw.ticks_per_msec))
+ if (dt >= (usec * fw.ticks_per_usec))
break;
}
}
orl(AR9170_TIMER_REG_INTERRUPT, BIT(timer));
}
-void clock_set(enum cpu_clock_t _clock, bool on)
+void clock_set(enum cpu_clock_t clock_, bool on)
{
/*
* Word of Warning!
* This setting does more than just mess with the CPU Clock.
* So watch out, if you need _stable_ timer interrupts.
*/
+ if (fw.phy.frequency < 3000000)
+ set(AR9170_PWR_REG_PLL_ADDAC, 0x5163);
+ else
+ set(AR9170_PWR_REG_PLL_ADDAC, 0x5143);
+
+ fw.ticks_per_usec = GET_VAL(AR9170_PWR_PLL_ADDAC_DIV,
+ get(AR9170_PWR_REG_PLL_ADDAC));
+
+ set(AR9170_PWR_REG_CLOCK_SEL, (uint32_t) ((on ? 0x70 : 0x600) | clock_));
+
+ switch (clock_) {
+ case AHB_20_22MHZ:
+ fw.ticks_per_usec >>= 1;
+ case AHB_40MHZ_OSC:
+ case AHB_40_44MHZ:
+ fw.ticks_per_usec >>= 1;
+ case AHB_80_88MHZ:
+ break;
+ }
- fw.ticks_per_msec = GET_VAL(AR9170_PWR_PLL_ADDAC_DIV, get(AR9170_PWR_REG_PLL_ADDAC)) >> 1;
+ timer_init(1, (fw.ticks_per_usec * 25) >> 1);
- set(AR9170_PWR_REG_CLOCK_SEL, (uint32_t) ((on ? 0x70 : 0x600) | _clock));
+ INFO("SET CLOCK c:%d t:%d tt:%d f:%d\n", clock_, fw.ticks_per_usec, (fw.ticks_per_usec * 25) >> 1, fw.phy.frequency);
}
static void init(void)
#endif /* CONFIG_CARL9170FW_DEBUG_LED_HEARTBEAT */
}
+static void timer1_isr(void)
+{
+}
+
static void handle_timer(void)
{
uint32_t intr;
HANDLER(intr, BIT(0), timer0_isr);
+ HANDLER(intr, BIT(1), timer1_isr);
+
if (intr)
DBG("Unhandled Timer Event %x", (unsigned int) intr);
fw.phy.ht_settings = cmd->rf_init.ht_settings;
fw.phy.frequency = cmd->rf_init.freq;
+ /*
+ * Is the clock controlled by the PHY?
+ */
if ((fw.phy.ht_settings & EIGHTY_FLAG) == EIGHTY_FLAG)
clock_set(AHB_80_88MHZ, true);
else
}
}
- if (fw.phy.frequency < 30000000)
+ if (fw.phy.frequency < 3000000)
bank3 |= 0x00800000;
set(0x1c58f0, bank3);