carl9170 firmware: fix inaccurate delay calculation

The internal refclock is set by the driver to either:
	44MHz - when the device operates on a 2.4 GHz channel
	40MHz - 5GHz Band

This patch removes the previously used "80MHz" constant
(that's wrong anyway since this is the HT40 AHB/CPU clock)
and enhance the code so it can deal with the slight clock
speed variations.

Reported-by: Ignacy Gawedzki <i@lri.fr>
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>

diff --git a/carlfw/include/carl9170.h b/carlfw/include/carl9170.h
index 69028168830920647028a24fb906f01f1b043677..b61189bb2bf0530867cb7e661d23dc2c5ed6c893 100644 (file)
--- a/carlfw/include/carl9170.h
+++ b/carlfw/include/carl9170.h
@@ -70,6 +70,7 @@ enum carl9170_mac_reset_state {
 
 struct firmware_context_struct {
        /* timer / clocks */
+       unsigned int ticks_per_msec;
        unsigned int counter;                   /* main() cycles */
 
        /* misc */

diff --git a/carlfw/include/timer.h b/carlfw/include/timer.h
index bf2f310ba07f4cf08c64b4083bf40fd8bc996d4f..d6497199fa0d88b867fdd248fa209dc7af58bcdd 100644 (file)
--- a/carlfw/include/timer.h
+++ b/carlfw/include/timer.h
@@ -35,45 +35,56 @@ enum cpu_clock_t {
        AHB_80_88MHZ    = 3
 };
 
-#define AR9170_TICKS_PER_MICROSECOND   80
-
 static inline __inline uint32_t get_clock_counter(void)
 {
        return (get(AR9170_TIMER_REG_CLOCK_HIGH) << 16) | get(AR9170_TIMER_REG_CLOCK_LOW);
 }
 
-static inline __inline bool is_after_msecs(uint32_t t0, uint32_t msecs)
+/*
+ * works only up to 97 secs [44 MHz] or 107 secs for 40 MHz
+ * Also, the delay wait will be affected by 2.4GHz<->5GHz
+ * band changes.
+ */
+static inline __inline bool is_after_msecs(const uint32_t t0, const uint32_t msecs)
 {
-       return (get_clock_counter() - t0) / (AR9170_TICKS_PER_MICROSECOND * 1000) > msecs;
+       return ((get_clock_counter() - t0) / 1000) > (msecs * fw.ticks_per_msec);
 }
 
-static inline __inline void delay(uint32_t msec)
+/*
+ * Note: Be careful with [u]delay. They won't service the
+ * hardware watchdog timer. It might trigger if you
+ * wait long enough. Also they don't terminate if sec is
+ * above 97 sec [44MHz] or more than 107 sec [40MHz].
+ */
+static inline __inline void delay(const uint32_t msec)
 {
-       uint32_t t1, t2, dt;
+       uint32_t t1, t2, dt, wt;
+
+       wt = msec * fw.ticks_per_msec;
 
        t1 = get_clock_counter();
        while (1) {
                t2 = get_clock_counter();
-               dt = (t2 - t1) / AR9170_TICKS_PER_MICROSECOND / 1000;
-               if (dt >= msec)
+               dt = (t2 - t1) / 1000;
+               if (dt >= wt)
                        break;
        }
 }
 
-static inline __inline void udelay(uint32_t usec)
+static inline __inline void udelay(const uint32_t usec)
 {
        uint32_t t1, t2, dt;
 
        t1 = get_clock_counter();
        while (1) {
                t2 = get_clock_counter();
-               dt = (t2 - t1) / AR9170_TICKS_PER_MICROSECOND;
-               if (dt >= usec)
+               dt = (t2 - t1);
+               if (dt >= (usec * fw.ticks_per_msec))
                        break;
        }
 }
 
-static inline void clock_set(const bool on, const enum cpu_clock_t _clock)
+static inline void clock_set(enum cpu_clock_t _clock, bool on)
 {
        /*
         * Word of Warning!
@@ -81,6 +92,8 @@ static inline void clock_set(const bool on, const enum cpu_clock_t _clock)
         * So watch out, if you need _stable_ timer interrupts.
         */
 
+       fw.ticks_per_msec = GET_VAL(AR9170_PWR_PLL_ADDAC_DIV, get(AR9170_PWR_REG_PLL_ADDAC)) >> 1;
+
        set(AR9170_PWR_REG_CLOCK_SEL, (uint32_t) ((on ? 0x70 : 0x600) | _clock));
 }
 

diff --git a/carlfw/src/main.c b/carlfw/src/main.c
index b9239c8e4969b5fcf5ca3dcc437886d8a613bb47..bf6602a8d8cc29af60916edb97737b4facf9d84f 100644 (file)
--- a/carlfw/src/main.c
+++ b/carlfw/src/main.c
@@ -169,7 +169,7 @@ static void __noreturn main_loop(void)
 
 void start(void)
 {
-       clock_set(true, AHB_40MHZ_OSC);
+       clock_set(AHB_40MHZ_OSC, true);
 
        /* watchdog magic pattern check */
        if ((get(AR9170_PWR_REG_WATCH_DOG_MAGIC) & 0xffff0000) == 0x12340000) {

diff --git a/carlfw/src/rf.c b/carlfw/src/rf.c
index 9bb8394dc1b246646065743bdbe1168d1aea98ce..bb74b817aed2ee7428753b03e138b4ab2dc4a9e2 100644 (file)
--- a/carlfw/src/rf.c
+++ b/carlfw/src/rf.c
@@ -200,9 +200,9 @@ void rf_cmd(const struct carl9170_cmd *cmd, struct carl9170_rsp *resp)
        fw.phy.frequency = cmd->rf_init.freq;
 
        if ((fw.phy.ht_settings & EIGHTY_FLAG) == EIGHTY_FLAG)
-               clock_set(true, AHB_80_88MHZ);
+               clock_set(AHB_80_88MHZ, true);
        else
-               clock_set(true, AHB_40_44MHZ);
+               clock_set(AHB_40_44MHZ, true);
 
        ret = rf_init(le32_to_cpu(cmd->rf_init.delta_slope_coeff_exp),
                      le32_to_cpu(cmd->rf_init.delta_slope_coeff_man),

diff --git a/include/shared/hw.h b/include/shared/hw.h
index 1220c96162d83ee8f2fca858aea4b26a795a882f..90c84a60b69894d0e825ab0da2e92b70a28174f4 100644 (file)
--- a/include/shared/hw.h
+++ b/include/shared/hw.h
@@ -463,6 +463,8 @@
 
 #define        AR9170_PWR_REG_CHIP_REVISION            (AR9170_PWR_REG_BASE + 0x010)
 #define AR9170_PWR_REG_PLL_ADDAC               (AR9170_PWR_REG_BASE + 0x014)
+#define                AR9170_PWR_PLL_ADDAC_DIV_S              2
+#define                AR9170_PWR_PLL_ADDAC_DIV                0xffc
 #define        AR9170_PWR_REG_WATCH_DOG_MAGIC          (AR9170_PWR_REG_BASE + 0x020)
 
 /* Faraday USB Controller */