X-Git-Url: https://jxself.org/git/?a=blobdiff_plain;f=target_firmware%2Fwlan%2Fif_owl.c;h=e891de5456ad164c45c0edfc85006e744971051d;hb=1f81636e222ed01e8073098b55a27da4603831d8;hp=19a945cdfcfe49b707e8255b99ff41c40e596df4;hpb=8c18f096473720783f898f1ada3c4ee880ee1775;p=open-ath9k-htc-firmware.git

diff --git a/target_firmware/wlan/if_owl.c b/target_firmware/wlan/if_owl.c
index 19a945c..e891de5 100755
--- a/target_firmware/wlan/if_owl.c
+++ b/target_firmware/wlan/if_owl.c
@@ -253,7 +253,7 @@ static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
 		} else
 			ds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, i+1);
 
-		ah->ah_fillTxDesc(ah, ds
+		ah->ah_fillTxDesc(ds
 				   , bf->bf_dmamap_info.dma_segs[i].len
 				   , i == 0
 				   , i == (bf->bf_dmamap_info.nsegs - 1)
@@ -277,7 +277,7 @@ static void ath_tx_tgt_setds(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
 		break;
 	}
 
-	ah->ah_set11nTxDesc(ah, ds
+	ah->ah_set11nTxDesc(ds
 			      , bf->bf_pktlen
 			      , bf->bf_atype
 			      , 60
@@ -372,7 +372,6 @@ static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
     HAL_11N_RATE_SERIES series[4];
     a_int32_t i, flags;
     a_uint8_t rix, cix, rtsctsrate;
-    a_uint32_t ctsduration = 0;
     a_int32_t prot_mode = AH_FALSE;
 
     rt = sc->sc_currates;
@@ -387,7 +386,7 @@ static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
 	    cix = rt->info[sc->sc_protrix].controlRate;
 	    prot_mode = AH_TRUE;
     } else {
-	    if (ath_hal_htsupported(ah) && (!bf->bf_ismcast))
+	    if (ath_hal_getcapability(ah, HAL_CAP_HT) && (!bf->bf_ismcast))
 		    flags = HAL_TXDESC_RTSENA;
 
 	    for (i = 4; i--;) {
@@ -444,8 +443,8 @@ static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
     rtsctsrate = rt->info[cix].rateCode |
 	    (bf->bf_shpream ? rt->info[cix].shortPreamble : 0);
 
-    ah->ah_set11nRateScenario(ah, ds, 1,
-				rtsctsrate, ctsduration,
+    ah->ah_set11nRateScenario(ds, 1,
+				rtsctsrate,
 				series, 4,
 				flags);
 }
@@ -557,6 +556,8 @@ void ath_tx_status_update(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
 	if (txs == NULL)
 		return;
 
+	txs->txstatus[txs->cnt].ts_flags = 0;
+
 	txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
 	txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
 
@@ -896,7 +897,7 @@ static void ath_tgt_txq_add_ucast(struct ath_softc_tgt *sc, struct ath_tx_buf *b
 	} else {
 		*txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
 
-		txe_val = OS_REG_READ(ah, 0x840);
+		txe_val = ioread32_mac(0x0840);
 		if (!(txe_val & (1<< txq->axq_qnum)))
 			ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
 	}
@@ -988,9 +989,9 @@ ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
 	struct ath_hal *ah = sc->sc_ah;
 
 	for (bfd = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; bfd++, i++) {
-		ah->ah_clr11nAggr(ah, bfd);
-		ah->ah_set11nBurstDuration(ah, bfd, 0);
-		ah->ah_set11nVirtualMoreFrag(ah, bfd, 0);
+		ah->ah_clr11nAggr(bfd);
+		ah->ah_set11nBurstDuration(bfd, 0);
+		ah->ah_set11nVirtualMoreFrag(bfd, 0);
 	}
 
 	ath_dma_unmap(sc, bf);
@@ -1052,7 +1053,7 @@ ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
 	struct ath_vap_target *avp;
 	struct ath_hal *ah = sc->sc_ah;
 	a_uint8_t rix, txrate, ctsrate, cix = 0xff, *data;
-	a_uint32_t ivlen = 0, icvlen = 0, subtype, flags, ctsduration;
+	a_uint32_t subtype, flags, ctsduration;
 	a_int32_t i, iswep, ismcast, hdrlen, pktlen, try0, len;
 	struct ath_tx_desc *ds=NULL;
 	struct ath_txq *txq=NULL;
@@ -1201,20 +1202,16 @@ ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
 
 	flags |= HAL_TXDESC_INTREQ;
 
-	ah->ah_setupTxDesc(ah, ds
+	ah->ah_setupTxDesc(ds
 			    , pktlen
 			    , hdrlen
 			    , atype
 			    , 60
 			    , txrate, try0
 			    , keyix
-			    , 0
 			    , flags
 			    , ctsrate
-			    , ctsduration
-			    , icvlen
-			    , ivlen
-			    , ATH_COMP_PROC_NO_COMP_NO_CCS);
+			    , ctsduration);
 
 	bf->bf_flags = flags;
 
@@ -1224,7 +1221,7 @@ ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
 	 */
 	if (iswep && (keyix != HAL_TXKEYIX_INVALID) &&
 			(wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH)
-		ah->ah_fillKeyTxDesc(ah, ds, mh->keytype);
+		ah->ah_fillKeyTxDesc(ds, mh->keytype);
 
 	ath_filltxdesc(sc, bf);
 
@@ -1234,7 +1231,7 @@ ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
 		series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
 		series[i].RateFlags = 0;
 	}
-	ah->ah_set11nRateScenario(ah, ds, 0, ctsrate, ctsduration, series, 4, 0);
+	ah->ah_set11nRateScenario(ds, 0, ctsrate, series, 4, 0);
 	ath_tgt_txqaddbuf(sc, txq, bf, bf->bf_lastds);
 
 	return;
@@ -1413,7 +1410,7 @@ ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
 			bf->bf_next = NULL;
 
 			for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
-				ah->ah_clr11nAggr(ah, ds);
+				ah->ah_clr11nAggr(ds);
 
 			ath_buf_set_rate(sc, bf);
 			bf->bf_txq_add(sc, bf);
@@ -1427,12 +1424,12 @@ ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
 
 		bf->bf_isaggr  = 1;
 		ath_buf_set_rate(sc, bf);
-		ah->ah_set11nAggrFirst(ah, bf->bf_desc, bf->bf_al,
+		ah->ah_set11nAggrFirst(bf->bf_desc, bf->bf_al,
 					  bf->bf_ndelim);
 		bf->bf_lastds = bf_last->bf_lastds;
 
 		for (i = 0; i < bf_last->bf_dmamap_info.nsegs; i++)
-			ah->ah_set11nAggrLast(ah, &bf_last->bf_descarr[i]);
+			ah->ah_set11nAggrLast(&bf_last->bf_descarr[i]);
 
 		if (status == ATH_AGGR_8K_LIMITED) {
 			adf_os_assert(0);
@@ -1577,7 +1574,7 @@ int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid,
 		bf_prev = bf;
 
 		for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
-			ah->ah_set11nAggrMiddle(ah, ds, bf->bf_ndelim);
+			ah->ah_set11nAggrMiddle(ds, bf->bf_ndelim);
 
 	} while (!asf_tailq_empty(&tid->buf_q));
 
@@ -1812,9 +1809,9 @@ ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
 	__stats(sc, txaggr_compretries);
 
 	for(ds = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; ds++, i++) {
-		ah->ah_clr11nAggr(ah, ds);
-		ah->ah_set11nBurstDuration(ah, ds, 0);
-		ah->ah_set11nVirtualMoreFrag(ah, ds, 0);
+		ah->ah_clr11nAggr(ds);
+		ah->ah_set11nBurstDuration(ds, 0);
+		ah->ah_set11nVirtualMoreFrag(ds, 0);
 	}
 
 	if (bf->bf_retries >= OWLMAX_RETRIES) {
@@ -2129,7 +2126,7 @@ static void ath_bar_tx(struct ath_softc_tgt *sc,
 	adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
 
 	ds = bf->bf_desc;
-	ah->ah_setupTxDesc(ah, ds
+	ah->ah_setupTxDesc(ds
 			    , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
 			    , 0
 			    , HAL_PKT_TYPE_NORMAL
@@ -2137,18 +2134,16 @@ static void ath_bar_tx(struct ath_softc_tgt *sc,
 			    , min_rate
 			    , ATH_TXMAXTRY
 			    , bf->bf_keyix
-			    , 0
 			    , HAL_TXDESC_INTREQ
 			    | HAL_TXDESC_CLRDMASK
-			    , 0, 0, 0, 0
-			    , ATH_COMP_PROC_NO_COMP_NO_CCS);
+			    , 0, 0);
 
 	skbhead = bf->bf_skbhead;
 	bf->bf_isaggr = 0;
 	bf->bf_next = NULL;
 
 	for (ds0 = ds, i=0; i < bf->bf_dmamap_info.nsegs; ds0++, i++) {
-		ah->ah_clr11nAggr(ah, ds0);
+		ah->ah_clr11nAggr(ds0);
 	}
 
 	ath_filltxdesc(sc, bf);
@@ -2159,6 +2154,6 @@ static void ath_bar_tx(struct ath_softc_tgt *sc,
 		series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
 	}
 
-	ah->ah_set11nRateScenario(ah, bf->bf_desc, 0, 0, 0, series, 4, 4);
+	ah->ah_set11nRateScenario(bf->bf_desc, 0, 0, series, 4, 4);
 	ath_tgt_txq_add_ucast(sc, bf);
 }