X-Git-Url: https://jxself.org/git/?a=blobdiff_plain;f=target_firmware%2Fwlan%2Fif_athvar.h;h=8a53b32322cf34c495d2608691bcc70772d9f82e;hb=bd385aac9d518fae6f9f3410e78fe6b03e9fa9c7;hp=b57c4e03fd0994cf35bcaad29b615e048aa4ff9c;hpb=8804cc94e3b66550797279f540b960d18a78421f;p=open-ath9k-htc-firmware.git

diff --git a/target_firmware/wlan/if_athvar.h b/target_firmware/wlan/if_athvar.h
index b57c4e0..8a53b32 100755
--- a/target_firmware/wlan/if_athvar.h
+++ b/target_firmware/wlan/if_athvar.h
@@ -1,3 +1,38 @@
+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted (subject to the limitations in the
+ * disclaimer below) provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of Qualcomm Atheros nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+ * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
 #ifndef _DEV_ATH_ATHVAR_H
 #define _DEV_ATH_ATHVAR_H
 
@@ -89,8 +124,6 @@ typedef enum {
 #define TARGET_NODE_MAX ATH_NODE_MAX
 #define TARGET_VAP_MAX  ATH_VAP_MAX
 
-#define ATH_NODE_TARGET(_n) ((struct ath_node *)(_n))
-
 #define MAX_RATE_POWER               63
 #define ATH_COMP_PROC_NO_COMP_NO_CCS 3
 
@@ -161,25 +194,30 @@ struct ath_buf_state {
 #define bf_retries        bf_state.bfs_retries
 
 #define ATH_GENERIC_BUF                     \
-    asf_tailq_entry(ath_buf)  bf_list;      \
-    struct ath_buf        *bf_next;	    \
-    struct ath_desc       *bf_desc;	    \
-    struct ath_desc       *bf_descarr;	    \
     adf_os_dma_map_t      bf_dmamap;	    \
     adf_os_dmamap_info_t  bf_dmamap_info;   \
     struct ieee80211_node_target *bf_node;  \
     adf_nbuf_queue_t      bf_skbhead;	    \
-    adf_nbuf_t            bf_skb;	    \
-    struct ath_desc 	  *bf_lastds;
+    adf_nbuf_t            bf_skb;
 
 struct ath_buf
 {
     ATH_GENERIC_BUF
+    asf_tailq_entry(ath_buf)  bf_list;
+    struct ath_buf        *bf_next;
+    struct ath_desc 	  *bf_lastds;
+    struct ath_desc       *bf_desc;
+    struct ath_desc       *bf_descarr;
 };
 
 struct ath_tx_buf
 {
 	ATH_GENERIC_BUF
+	asf_tailq_entry(ath_tx_buf)  bf_list;
+	struct ath_tx_buf	     *bf_next;
+	struct ath_tx_desc	     *bf_desc;
+	struct ath_tx_desc	     *bf_descarr;
+	struct ath_tx_desc	     *bf_lastds;
 	struct ath_buf_state  bf_state;
 	a_uint16_t            bf_flags;
 	HTC_ENDPOINT_ID       bf_endpt;
@@ -190,17 +228,24 @@ struct ath_tx_buf
 struct ath_rx_buf
 {
 	ATH_GENERIC_BUF
+	asf_tailq_entry(ath_rx_buf)  bf_list;
+	struct ath_rx_buf	     *bf_next;
+	struct ath_rx_desc	     *bf_desc;
+	struct ath_rx_desc	     *bf_descarr;
+	struct ath_rx_desc	     *bf_lastds;
 	a_uint32_t            bf_status;
 	struct ath_rx_status  bf_rx_status;
 };
 
-#define ATH_BUF_GET_DESC_PHY_ADDR(bf)                       bf->bf_desc
+#define ATH_BUF_GET_DESC_PHY_ADDR(bf)                       (a_uint32_t)bf->bf_desc
 #define ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, idx)         (adf_os_dma_addr_t)(&bf->bf_descarr[idx])
 #define ATH_BUF_SET_DESC_PHY_ADDR(bf, addr)
 #define ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, idx, addr)
 
 typedef asf_tailq_head(ath_deschead_s, ath_rx_desc) ath_deschead;
 typedef asf_tailq_head(ath_bufhead_s, ath_buf) ath_bufhead;
+typedef asf_tailq_head(ath_rx_bufhead_s, ath_rx_buf) ath_rx_bufhead;
+typedef asf_tailq_head(ath_tx_bufhead_s, ath_tx_buf) ath_tx_bufhead;
 
 #define WME_NUM_TID 8
 #define WME_BA_BMP_SIZE 64
@@ -346,20 +391,20 @@ struct ath_softc_tgt
    	tq_struct         sc_txtotq;
    	tq_struct         sc_fataltq;
 
-	ath_bufhead        sc_rxbuf;
+	ath_rx_bufhead     sc_rxbuf;
 
 	ath_deschead       sc_rxdesc_idle;
 	ath_deschead	   sc_rxdesc;
-	struct ath_desc    *sc_rxdesc_held;
+	struct ath_rx_desc    *sc_rxdesc_held;
 
-   	struct ath_buf    *sc_txbuf_held;
+	struct ath_tx_buf    *sc_txbuf_held;
 
 	struct ath_descdma  sc_rxdma;
    	struct ath_descdma  sc_txdma;
 	struct ath_descdma  sc_bdma;
 
 	a_uint32_t	   *sc_rxlink;
-	ath_bufhead        sc_txbuf;
+	ath_tx_bufhead     sc_txbuf;
   	a_uint8_t          sc_txqsetup;
 
 	struct ath_txq     sc_txq[HAL_NUM_TX_QUEUES];