X-Git-Url: https://jxself.org/git/?a=blobdiff_plain;f=target_firmware%2Fwlan%2Fif_ath.c;h=bea411a58112ec4f5dd1906ea8a61f46f9a9d4ec;hb=24b5105e0730aaeffb8a7b0b6b0d93eec6190b86;hp=f965a2781f9a967bd74ba90a20144fde8be5170a;hpb=724621fb4cb4be9367c804f2eafb5fd6131b9db6;p=open-ath9k-htc-firmware.git diff --git a/target_firmware/wlan/if_ath.c b/target_firmware/wlan/if_ath.c index f965a27..bea411a 100755 --- a/target_firmware/wlan/if_ath.c +++ b/target_firmware/wlan/if_ath.c @@ -56,6 +56,8 @@ #include "if_athvar.h" #include "ah_desc.h" #include "ah.h" +#include "ratectrl.h" +#include "ah_internal.h" static a_int32_t ath_numrxbufs = -1; static a_int32_t ath_numrxdescs = -1; @@ -82,26 +84,36 @@ void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf); void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host); /* - * Extend a 32 bit TSF to 64 bit, taking wrapping into account. + * Extend a 32 bit TSF to nearest 64 bit TSF value. + * When the adapter is a STATION, its local TSF is periodically modified by + * the hardware to match the BSS TSF (as received in beacon packets), and + * rstamp may appear to be from the future or from the past (with reference + * to the current local TSF) because of jitter. This is mostly noticable in + * highly congested channels. The code uses signed modulo arithmetic to + * handle both past/future cases and signed-extension to avoid branches. + * Test cases: + * extend(0x0000001200000004, 0x00000006) == 0x0000001200000006 + * extend(0x0000001200000004, 0x00000002) == 0x0000001200000002 + * extend(0x0000001200000004, 0xfffffffe) == 0x00000011fffffffe ! tsfhigh-- + * extend(0x000000127ffffffe, 0x80000002) == 0x0000001280000002 + * extend(0x0000001280000002, 0x7ffffffe) == 0x000000127ffffffe + * extend(0x00000012fffffffc, 0xfffffffe) == 0x00000012fffffffe + * extend(0x00000012fffffffc, 0xfffffffa) == 0x00000012fffffffa + * extend(0x00000012fffffffc, 0x00000002) == 0x0000001300000002 ! tsfhigh++ */ static u_int64_t ath_extend_tsf(struct ath_softc_tgt *sc, u_int32_t rstamp) { struct ath_hal *ah = sc->sc_ah; u_int64_t tsf; u_int32_t tsf_low; - u_int64_t tsf64; + a_int64_t tsf_delta; /* signed int64 */ tsf = ah->ah_getTsf64(ah); - tsf_low = tsf & 0xffffffff; - tsf64 = (tsf & ~0xffffffffULL) | rstamp; + tsf_low = tsf & 0xffffffffUL; - if (rstamp > tsf_low && (rstamp - tsf_low > 0x10000000)) - tsf64 -= 0x100000000ULL; + tsf_delta = (a_int32_t)((rstamp - tsf_low) & 0xffffffffUL); - if (rstamp < tsf_low && (tsf_low - rstamp > 0x10000000)) - tsf64 += 0x100000000ULL; - - return tsf64; + return (tsf + (u_int64_t)tsf_delta); } static a_int32_t ath_rate_setup(struct ath_softc_tgt *sc, a_uint32_t mode) @@ -1380,6 +1392,23 @@ static void ath_node_update_tgt(void *Context, A_UINT16 Command, wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } +static a_int32_t ath_reg_read_filter(struct ath_hal *ah, a_int32_t addr) +{ + if ((addr & 0xffffe000) == 0x2000) { + /* SEEPROM registers */ + ioread32_mac(addr); + if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) + adf_os_print("SEEPROM Read fail: 0x%08x\n", addr); + + return ioread32_mac(0x407c) & 0x0000ffff; + } else if (addr > 0xffff) + /* SoC registers */ + return ioread32(addr); + else + /* MAC registers */ + return ioread32_mac(addr); +} + static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { @@ -1393,19 +1422,8 @@ static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command, addr = *(a_uint32_t *)(data + i); addr = adf_os_ntohl(addr); - if ((addr & 0xffffe000) == 0x2000) { - /* SEEPROM */ - ath_hal_reg_read_target(ah, addr); - if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) { - adf_os_print("SEEPROM Read fail: 0x%08x\n", addr); - } - val[i/sizeof(a_int32_t)] = (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff); - } else if (addr > 0xffff) { - val[i/sizeof(a_int32_t)] = *(a_uint32_t *)addr; - } else - val[i/sizeof(a_int32_t)] = ath_hal_reg_read_target(ah, addr); - - val[i/sizeof(a_int32_t)] = adf_os_ntohl(val[i/sizeof(a_int32_t)]); + val[i/sizeof(a_int32_t)] = + adf_os_ntohl(ath_reg_read_filter(ah, addr)); } wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &val[0], datalen); @@ -1418,20 +1436,20 @@ static void ath_pll_reset_ones(struct ath_hal *ah) if(reset_pll == 0) { #if defined(PROJECT_K2) /* here we write to core register */ - HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0); + iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0); /* and here to mac register */ - ath_hal_reg_write_target(ah, 0x786c, - ath_hal_reg_read_target(ah,0x786c) | 0x6000000); - ath_hal_reg_write_target(ah, 0x786c, - ath_hal_reg_read_target(ah,0x786c) & (~0x6000000)); + iowrite32_mac(0x786c, + ioread32_mac(0x786c) | 0x6000000); + iowrite32_mac(0x786c, + ioread32_mac(0x786c) & (~0x6000000)); - HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20); + iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20); #elif defined(PROJECT_MAGPIE) && !defined (FPGA) - ath_hal_reg_write_target(ah, 0x7890, - ath_hal_reg_read_target(ah,0x7890) | 0x1800000); - ath_hal_reg_write_target(ah, 0x7890, - ath_hal_reg_read_target(ah,0x7890) & (~0x1800000)); + iowrite32_mac(0x7890, + ioread32_mac(0x7890) | 0x1800000); + iowrite32_mac(0x7890, + ioread32_mac(0x7890) & (~0x1800000)); #endif reset_pll = 1; } @@ -1441,7 +1459,7 @@ static void ath_hal_reg_write_filter(struct ath_hal *ah, a_uint32_t reg, a_uint32_t val) { if(reg > 0xffff) { - HAL_WORD_REG_WRITE(reg, val); + iowrite32(reg, val); #if defined(PROJECT_K2) if(reg == 0x50040) { static uint8_t flg=0; @@ -1460,7 +1478,7 @@ static void ath_hal_reg_write_filter(struct ath_hal *ah, if(reg == 0x7014) ath_pll_reset_ones(ah); - ath_hal_reg_write_target(ah, reg, val); + iowrite32_mac(reg, val); } } @@ -1498,7 +1516,7 @@ static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command, a_uint32_t val; buf = (struct register_rmw *)(data + i); - val = ath_hal_reg_read_target(ah, buf->reg); + val = ath_reg_read_filter(ah, buf->reg); val &= ~buf->clr; val |= buf->set; ath_hal_reg_write_filter(ah, buf->reg, val);