X-Git-Url: https://jxself.org/git/?a=blobdiff_plain;f=target_firmware%2Fwlan%2Fif_ath.c;h=b31fbdb67e866d883732f14ca4171515015bbfbd;hb=83dd3bf0aae9da59ecb39852500f5e25adddef27;hp=4c9e98b16a63d84ac3bfacaff4ff17ca0fe95738;hpb=2ec0193c2fea5edc65f9f36af05b1c170bf4e881;p=open-ath9k-htc-firmware.git diff --git a/target_firmware/wlan/if_ath.c b/target_firmware/wlan/if_ath.c index 4c9e98b..b31fbdb 100755 --- a/target_firmware/wlan/if_ath.c +++ b/target_firmware/wlan/if_ath.c @@ -50,13 +50,14 @@ #include #include -#include "if_ethersubr.h" #include "if_llc.h" #include "ieee80211_var.h" -#include "ieee80211_proto.h" #include "if_athrate.h" #include "if_athvar.h" #include "ah_desc.h" +#include "ah.h" +#include "ratectrl.h" +#include "ah_internal.h" static a_int32_t ath_numrxbufs = -1; static a_int32_t ath_numrxdescs = -1; @@ -73,6 +74,7 @@ uint32_t *init_htc_handle = 0; void owl_tgt_tx_tasklet(TQUEUE_ARG data); static void ath_tgt_send_beacon(struct ath_softc_tgt *sc,adf_nbuf_t bc_hdr,adf_nbuf_t nbuf,HTC_ENDPOINT_ID EndPt); static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen); +static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen); extern struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh); extern void ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t mgt_hdr, adf_nbuf_t skb,HTC_ENDPOINT_ID EndPt); extern HAL_BOOL ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val); @@ -81,37 +83,37 @@ void owl_tgt_node_init(struct ath_node_target * an); void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf); void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host); -/*************/ -/* Utilities */ -/*************/ - -#undef adf_os_cpu_to_le16 - -static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x) -{ - return ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8)); -} - /* - * Extend a 32 bit TSF to 64 bit, taking wrapping into account. + * Extend a 32 bit TSF to nearest 64 bit TSF value. + * When the adapter is a STATION, its local TSF is periodically modified by + * the hardware to match the BSS TSF (as received in beacon packets), and + * rstamp may appear to be from the future or from the past (with reference + * to the current local TSF) because of jitter. This is mostly noticable in + * highly congested channels. The code uses signed modulo arithmetic to + * handle both past/future cases and signed-extension to avoid branches. + * Test cases: + * extend(0x0000001200000004, 0x00000006) == 0x0000001200000006 + * extend(0x0000001200000004, 0x00000002) == 0x0000001200000002 + * extend(0x0000001200000004, 0xfffffffe) == 0x00000011fffffffe ! tsfhigh-- + * extend(0x000000127ffffffe, 0x80000002) == 0x0000001280000002 + * extend(0x0000001280000002, 0x7ffffffe) == 0x000000127ffffffe + * extend(0x00000012fffffffc, 0xfffffffe) == 0x00000012fffffffe + * extend(0x00000012fffffffc, 0xfffffffa) == 0x00000012fffffffa + * extend(0x00000012fffffffc, 0x00000002) == 0x0000001300000002 ! tsfhigh++ */ static u_int64_t ath_extend_tsf(struct ath_softc_tgt *sc, u_int32_t rstamp) { + struct ath_hal *ah = sc->sc_ah; u_int64_t tsf; u_int32_t tsf_low; - u_int64_t tsf64; + a_int64_t tsf_delta; /* signed int64 */ - tsf = ath_hal_gettsf64(sc->sc_ah); - tsf_low = tsf & 0xffffffff; - tsf64 = (tsf & ~0xffffffffULL) | rstamp; + tsf = ah->ah_getTsf64(ah); + tsf_low = tsf & 0xffffffffUL; - if (rstamp > tsf_low && (rstamp - tsf_low > 0x10000000)) - tsf64 -= 0x100000000ULL; + tsf_delta = (a_int32_t)((rstamp - tsf_low) & 0xffffffffUL); - if (rstamp < tsf_low && (tsf_low - rstamp > 0x10000000)) - tsf64 += 0x100000000ULL; - - return tsf64; + return (tsf + (u_int64_t)tsf_delta); } static a_int32_t ath_rate_setup(struct ath_softc_tgt *sc, a_uint32_t mode) @@ -121,10 +123,10 @@ static a_int32_t ath_rate_setup(struct ath_softc_tgt *sc, a_uint32_t mode) switch (mode) { case IEEE80211_MODE_11NA: - sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11NA); + sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NA); break; case IEEE80211_MODE_11NG: - sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11NG); + sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NG); break; default: return 0; @@ -266,18 +268,16 @@ static a_int32_t ath_rxdesc_init(struct ath_softc_tgt *sc, struct ath_rx_desc *d ds->ds_link = 0; adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen); - ath_hal_setuprxdesc(ah, ds, - adf_nbuf_tailroom(ds->ds_nbuf), - 0); + ah->ah_setupRxDesc(ds, adf_nbuf_tailroom(ds->ds_nbuf), 0); if (sc->sc_rxlink == NULL) { - ath_hal_putrxbuf(ah, ds->ds_daddr); + ah->ah_setRxDP(ah, ds->ds_daddr); } else { *sc->sc_rxlink = ds->ds_daddr; } sc->sc_rxlink = &ds->ds_link; - ath_hal_rxena(ah); + ah->ah_enableReceive(ah); return 0; } @@ -329,13 +329,11 @@ static void ath_uapsd_processtriggers(struct ath_softc_tgt *sc) a_int32_t retval; a_uint32_t cnt = 0; a_uint16_t frame_len = 0; - a_uint64_t tsf; #define PA2DESC(_sc, _pa) \ ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) - tsf = ath_hal_gettsf64(ah); bf = asf_tailq_first(&sc->sc_rxbuf); ds = asf_tailq_first(&sc->sc_rxdesc); @@ -386,7 +384,7 @@ static void ath_uapsd_processtriggers(struct ath_softc_tgt *sc) continue; } - retval = ath_hal_rxprocdescfast(ah, ds, ds->ds_daddr, + retval = ah->ah_procRxDescFast(ah, ds, ds->ds_daddr, PA2DESC(sc, ds->ds_link), &bf->bf_rx_status); if (HAL_EINPROGRESS == retval) { break; @@ -472,7 +470,7 @@ static a_int32_t ath_startrecv(struct ath_softc_tgt *sc) } ds = asf_tailq_first(&sc->sc_rxdesc); - ath_hal_putrxbuf(ah, ds->ds_daddr); + ah->ah_setRxDP(ah, ds->ds_daddr); return 0; } @@ -522,7 +520,7 @@ static void ath_tgt_rx_tasklet(TQUEUE_ARG data) } while(1); sc->sc_imask |= HAL_INT_RX; - ath_hal_intrset(ah, sc->sc_imask); + ah->ah_setInterrupts(ah, sc->sc_imask); } /*******************/ @@ -555,22 +553,18 @@ static void ath_beacon_setup(struct ath_softc_tgt *sc, rt = sc->sc_currates; rate = rt->info[rix].rateCode; - ath_hal_setuptxdesc(ah, ds + ah->ah_setupTxDesc(ds , adf_nbuf_len(skb) + IEEE80211_CRC_LEN , sizeof(struct ieee80211_frame) , HAL_PKT_TYPE_BEACON , MAX_RATE_POWER , rate, 1 , HAL_TXKEYIX_INVALID - , 0 , flags , 0 - , 0 - , 0 - , 0 - , ATH_COMP_PROC_NO_COMP_NO_CCS); + , 0); - ath_hal_filltxdesc(ah, ds + ah->ah_fillTxDesc(ds , asf_roundup(adf_nbuf_len(skb), 4) , AH_TRUE , AH_TRUE @@ -580,7 +574,7 @@ static void ath_beacon_setup(struct ath_softc_tgt *sc, series[0].Rate = rate; series[0].ChSel = sc->sc_ic.ic_tx_chainmask; series[0].RateFlags = 0; - ath_hal_set11n_ratescenario(ah, ds, 0, 0, 0, series, 4, 0); + ah->ah_set11nRateScenario(ds, 0, 0, series, 4, 0); } static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr, @@ -590,9 +584,7 @@ static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr, struct ath_tx_buf *bf; a_uint8_t vap_index, *anbdata; ath_beacon_hdr_t *bhdr; - struct ieee80211vap_target *vap; a_uint32_t anblen; - struct ieee80211_frame *wh; if (!bc_hdr) { adf_nbuf_peek_header(nbuf, &anbdata, &anblen); @@ -603,10 +595,8 @@ static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr, vap_index = bhdr->vap_index; adf_os_assert(vap_index < TARGET_VAP_MAX); - vap = &sc->sc_vap[vap_index].av_vap; - wh = (struct ieee80211_frame *)adf_nbuf_pull_head(nbuf, - sizeof(ath_beacon_hdr_t)); + adf_nbuf_pull_head(nbuf, sizeof(ath_beacon_hdr_t)); bf = sc->sc_vap[vap_index].av_bcbuf; adf_os_assert(bf); @@ -624,9 +614,9 @@ static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr, adf_nbuf_dmamap_info(bf->bf_dmamap,&bf->bf_dmamap_info); ath_beacon_setup(sc, bf, &sc->sc_vap[vap_index]); - ath_hal_stoptxdma(ah, sc->sc_bhalq); - ath_hal_puttxbuf(ah, sc->sc_bhalq, ATH_BUF_GET_DESC_PHY_ADDR(bf)); - ath_hal_txstart(ah, sc->sc_bhalq); + ah->ah_stopTxDma(ah, sc->sc_bhalq); + ah->ah_setTxDP(ah, sc->sc_bhalq, ATH_BUF_GET_DESC_PHY_ADDR(bf)); + ah->ah_startTxDma(ah, sc->sc_bhalq); } /******/ @@ -637,7 +627,7 @@ static void ath_tx_stopdma(struct ath_softc_tgt *sc, struct ath_txq *txq) { struct ath_hal *ah = sc->sc_ah; - (void) ath_hal_stoptxdma(ah, txq->axq_qnum); + ah->ah_stopTxDma(ah, txq->axq_qnum); } static void owltgt_txq_drain(struct ath_softc_tgt *sc, struct ath_txq *txq) @@ -660,7 +650,7 @@ static void ath_draintxq(struct ath_softc_tgt *sc, HAL_BOOL drain_softq) ath_tx_status_clear(sc); sc->sc_tx_draining = 1; - (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); + ah->ah_stopTxDma(ah, sc->sc_bhalq); for (i = 0; i < HAL_NUM_TX_QUEUES; i++) if (ATH_TXQ_SETUP(sc, i)) @@ -785,7 +775,7 @@ static void tgt_HTCRecv_cabhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf, a_uint32_t tmp; #ifdef ATH_ENABLE_CABQ - tsf = ath_hal_gettsf64(ah); + tsf = ah->ah_getTsf64(ah); tmp = tsf - sc->sc_swba_tsf; if ( tmp > ATH_CABQ_HANDLING_THRESHOLD ) { @@ -880,7 +870,6 @@ static void ath_descdma_cleanup(struct ath_softc_tgt *sc, ath_bufhead *head, a_int32_t dir) { struct ath_buf *bf; - struct ieee80211_node_target *ni; asf_tailq_foreach(bf, head, bf_list) { if (adf_nbuf_queue_len(&bf->bf_skbhead) != 0) { @@ -898,7 +887,6 @@ static void ath_descdma_cleanup(struct ath_softc_tgt *sc, adf_nbuf_dmamap_destroy(sc->sc_dev, bf->bf_dmamap); - ni = bf->bf_node; bf->bf_node = NULL; } @@ -1021,24 +1009,24 @@ adf_os_irq_resp_t ath_intr(adf_drv_handle_t hdl) if (sc->sc_invalid) return ADF_OS_IRQ_NONE; - if (!ath_hal_intrpend(ah)) + if (!ah->ah_isInterruptPending(ah)) return ADF_OS_IRQ_NONE; - ath_hal_getisr(ah, &status); + ah->ah_getPendingInterrupts(ah, &status); status &= sc->sc_imask; if (status & HAL_INT_FATAL) { - ath_hal_intrset(ah, 0); + ah->ah_setInterrupts(ah, 0); ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_fataltq); } else { if (status & HAL_INT_SWBA) { WMI_SWBA_EVENT swbaEvt; struct ath_txq *txq = ATH_TXQ(sc, 8); - swbaEvt.tsf = ath_hal_gettsf64(ah); - swbaEvt.beaconPendingCount = ath_hal_numtxpending(ah, sc->sc_bhalq); - sc->sc_swba_tsf = ath_hal_gettsf64(ah); + swbaEvt.tsf = ah->ah_getTsf64(ah); + swbaEvt.beaconPendingCount = ah->ah_numTxPending(ah, sc->sc_bhalq); + sc->sc_swba_tsf = ah->ah_getTsf64(ah); wmi_event(sc->tgt_wmi_handle, WMI_SWBA_EVENTID, @@ -1061,14 +1049,14 @@ adf_os_irq_resp_t ath_intr(adf_drv_handle_t hdl) ath_uapsd_processtriggers(sc); sc->sc_imask &= ~HAL_INT_RX; - ath_hal_intrset(ah, sc->sc_imask); + ah->ah_setInterrupts(ah, sc->sc_imask); ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_rxtq); } if (status & HAL_INT_TXURN) { sc->sc_int_stats.ast_txurn++; - ath_hal_updatetxtriglevel(ah, AH_TRUE); + ah->ah_updateTxTrigLevel(ah, AH_TRUE); } ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_txtq); @@ -1110,9 +1098,9 @@ static void ath_enable_intr_tgt(void *Context, A_UINT16 Command, { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ath_hal *ah = sc->sc_ah; - a_uint32_t intr; + a_uint32_t intr = 0; - if (data) + if (datalen == 4) intr = (*(a_uint32_t *)data); intr = adf_os_ntohl(intr); @@ -1127,7 +1115,7 @@ static void ath_enable_intr_tgt(void *Context, A_UINT16 Command, sc->sc_imask |= HAL_INT_BMISS; } - ath_hal_intrset(ah, sc->sc_imask); + ah->ah_setInterrupts(ah, sc->sc_imask); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0); } @@ -1143,11 +1131,11 @@ static void ath_init_tgt(void *Context, A_UINT16 Command, sc->sc_imask |= HAL_INT_GTT; - if (ath_hal_htsupported(ah)) + if (ath_hal_getcapability(ah, HAL_CAP_HT)) sc->sc_imask |= HAL_INT_CST; adf_os_setup_intr(sc->sc_dev, ath_intr); - ath_hal_intrset(ah, sc->sc_imask); + ah->ah_setInterrupts(ah, sc->sc_imask); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } @@ -1396,6 +1384,23 @@ static void ath_node_update_tgt(void *Context, A_UINT16 Command, wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } +static a_int32_t ath_reg_read_filter(struct ath_hal *ah, a_int32_t addr) +{ + if ((addr & 0xffffe000) == 0x2000) { + /* SEEPROM registers */ + ioread32_mac(addr); + if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) + adf_os_print("SEEPROM Read fail: 0x%08x\n", addr); + + return ioread32_mac(0x407c) & 0x0000ffff; + } else if (addr > 0xffff) + /* SoC registers */ + return ioread32(addr); + else + /* MAC registers */ + return ioread32_mac(addr); +} + static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { @@ -1409,24 +1414,66 @@ static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command, addr = *(a_uint32_t *)(data + i); addr = adf_os_ntohl(addr); - if ((addr & 0xffffe000) == 0x2000) { - /* SEEPROM */ - ath_hal_reg_read_target(ah, addr); - if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) { - adf_os_print("SEEPROM Read fail: 0x%08x\n", addr); - } - val[i/sizeof(a_int32_t)] = (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff); - } else if (addr > 0xffff) { - val[i/sizeof(a_int32_t)] = *(a_uint32_t *)addr; - } else - val[i/sizeof(a_int32_t)] = ath_hal_reg_read_target(ah, addr); - - val[i/sizeof(a_int32_t)] = adf_os_ntohl(val[i/sizeof(a_int32_t)]); + val[i/sizeof(a_int32_t)] = + adf_os_ntohl(ath_reg_read_filter(ah, addr)); } wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &val[0], datalen); } +static void ath_pll_reset_ones(struct ath_hal *ah) +{ + static uint8_t reset_pll = 0; + + if(reset_pll == 0) { +#if defined(PROJECT_K2) + /* here we write to core register */ + iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0); + /* and here to mac register */ + iowrite32_mac(0x786c, + ioread32_mac(0x786c) | 0x6000000); + iowrite32_mac(0x786c, + ioread32_mac(0x786c) & (~0x6000000)); + + iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20); + +#elif defined(PROJECT_MAGPIE) && !defined (FPGA) + iowrite32_mac(0x7890, + ioread32_mac(0x7890) | 0x1800000); + iowrite32_mac(0x7890, + ioread32_mac(0x7890) & (~0x1800000)); +#endif + reset_pll = 1; + } +} + +static void ath_hal_reg_write_filter(struct ath_hal *ah, + a_uint32_t reg, a_uint32_t val) +{ + if(reg > 0xffff) { + iowrite32(reg, val); +#if defined(PROJECT_K2) + if(reg == 0x50040) { + static uint8_t flg=0; + + if(flg == 0) { + /* reinit clock and uart. + * TODO: Independent on what host will + * here set. We do our own decision. Why? */ + A_CLOCK_INIT(117); + A_UART_HWINIT(117*1000*1000, 19200); + flg = 1; + } + } +#endif + } else { + if(reg == 0x7014) + ath_pll_reset_ones(ah); + + iowrite32_mac(reg, val); + } +} + static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { @@ -1441,58 +1488,31 @@ static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, for (i = 0; i < datalen; i += sizeof(struct registerWrite)) { t = (struct registerWrite *)(data+i); - if( t->reg > 0xffff ) { - a_uint32_t *pReg = (a_uint32_t *)t->reg; + ath_hal_reg_write_filter(ah, t->reg, t->val); + } - *pReg = t->val; + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} -#if defined(PROJECT_K2) - if( t->reg == 0x50040 ) { - static uint8_t flg=0; +static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, + a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct ath_hal *ah = sc->sc_ah; + struct register_rmw *buf = (struct register_rmw *)data; + int i; - if( flg == 0 ) { - A_CLOCK_INIT(117); - A_UART_HWINIT(117*1000*1000, 19200); - flg = 1; - } - } -#endif - } else { -#if defined(PROJECT_K2) - if( t->reg == 0x7014 ) { - static uint8_t resetPLL = 0; - a_uint32_t *pReg; - - if( resetPLL == 0 ) { - t->reg = 0x50044; - pReg = (a_uint32_t *)t->reg; - *pReg = 0; - ath_hal_reg_write_target(ah, 0x786c, - ath_hal_reg_read_target(ah,0x786c) | 0x6000000); - ath_hal_reg_write_target(ah, 0x786c, - ath_hal_reg_read_target(ah,0x786c) & (~0x6000000)); - *pReg = 0x20; - resetPLL = 1; - } - t->reg = 0x7014; - } -#elif defined(PROJECT_MAGPIE) && !defined (FPGA) - if( t->reg == 0x7014 ){ - static uint8_t resetPLL = 0; - - if( resetPLL == 0 ) { - ath_hal_reg_write_target(ah, 0x7890, - ath_hal_reg_read_target(ah,0x7890) | 0x1800000); - ath_hal_reg_write_target(ah, 0x7890, - ath_hal_reg_read_target(ah,0x7890) & (~0x1800000)); - resetPLL = 1; - } - } -#endif - ath_hal_reg_write_target(ah,t->reg,t->val); - } - } + for (i = 0; i < datalen; + i += sizeof(struct register_rmw)) { + a_uint32_t val; + buf = (struct register_rmw *)(data + i); + val = ath_reg_read_filter(ah, buf->reg); + val &= ~buf->clr; + val |= buf->set; + ath_hal_reg_write_filter(ah, buf->reg, val); + } wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } @@ -1516,7 +1536,7 @@ static void ath_disable_intr_tgt(void *Context, A_UINT16 Command, struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ath_hal *ah = sc->sc_ah; - ath_hal_intrset(ah, 0); + ah->ah_setInterrupts(ah, 0); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0); } @@ -1565,8 +1585,9 @@ static void ath_aborttx_dma_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) { struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct ath_hal *ah = sc->sc_ah; - ath_hal_aborttxdma(sc->sc_ah); + ah->ah_abortTxDma(sc->sc_ah); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } @@ -1596,7 +1617,7 @@ static void ath_stop_tx_dma_tgt(void *Context, A_UINT16 Command, q = *(a_uint32_t *)data; q = adf_os_ntohl(q); - ath_hal_stoptxdma(ah, q); + ah->ah_stopTxDma(ah, q); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); } @@ -1616,9 +1637,9 @@ static void ath_stoprecv_tgt(void *Context, A_UINT16 Command, struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; struct ath_hal *ah = sc->sc_ah; - ath_hal_stoppcurecv(ah); - ath_hal_setrxfilter(ah, 0); - ath_hal_stopdmarecv(ah); + ah->ah_stopPcuReceive(ah); + ah->ah_setRxFilter(ah, 0); + ah->ah_stopDmaReceive(ah); sc->sc_rxlink = NULL; wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); @@ -1645,7 +1666,7 @@ static void ath_detach_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, struct ath_hal *ah = sc->sc_ah; ath_desc_free(sc); - ath_hal_detach(ah); + ah->ah_detach(ah); wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); adf_os_mem_free(sc); } @@ -1754,6 +1775,7 @@ static WMI_DISPATCH_ENTRY Magpie_Sys_DispatchEntries[] = {ath_tx_stats_tgt, WMI_TX_STATS_CMDID, 0}, {ath_rx_stats_tgt, WMI_RX_STATS_CMDID, 0}, {ath_rc_mask_tgt, WMI_BITRATE_MASK_CMDID, 0}, + {ath_hal_reg_rmw_tgt, WMI_REG_RMW_CMDID, 0}, }; /*****************/ @@ -1930,14 +1952,14 @@ a_int32_t ath_tgt_attach(a_uint32_t devid, struct ath_softc_tgt *sc, adf_os_devi ath_tgt_txq_setup(sc); sc->sc_imask =0; - ath_hal_intrset(ah,0); + ah->ah_setInterrupts(ah, 0); return 0; bad: bad2: ath_desc_free(sc); if (ah) - ath_hal_detach(ah); + ah->ah_detach(ah); } static void tgt_hif_htc_wmi_shutdown(struct ath_softc_tgt *sc)